RTEMS | Deterministic Hedged Read Library (DHRL) for DRAM Tail Latency Mitigation (#5548)

[Chris Johns (@chris)]

Chris Johns commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5548#note_148282


1. Does a library exist or is this bring written as part of this effort?
2. It mentions AXI bus? This is library limited to that AXI architecture?
3. Do you have any metrics on the period of time a controller locks a DRAM bank for?

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5548#note_148282
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