RTEMS | riscv/riscv clockdrv may bsp_fatal even with correct behaviour/initialization (#5486)

Thu Feb 12 12:18:45 UTC 2026

Lucian Silistru commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5486#note_142482

I tried to and turns out the frequency ratios are not enough for the issue; it was a simulator issue not updating mtime correctly on harts other than 0 when hart 0 is in wfi.

As an aside, what I did find was that there were ~92 instructions between the mtime reads in the pc trace. While very unlikely (silicon will add a lot of other latencies) some cpus we use do have >100:1 mcycle:mtime frequency ratios.

So, not an issue for now. Can close this.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5486#note_142482
You're receiving this email because of your account on gitlab.rtems.org.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20260212/5ae19c4d/attachment.htm>