RTEMS | risc-v: support running in s-mode (!1086)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086

* fd017c46...3d396291 - 2 commits from branch `main`

* 4f3af6b6 - spec/build: add RISCV_USE_S_MODE option
* ca4bef77 - riscv: support s-mode during boot
* c2ddd9c5 - bsps/riscv: support SMP secondary processors
* 338e6465 - bsps/riscv: support s-mode timer in clock driver
* 212083a6 - bsps/riscv: support s-mode irq handling
* c2b5e338 - riscv: enable s-mode in CPU port
* c191bc70 - cpukit/riscv: remove s/m prefix on frame context regs
* 05db72aa - riscv/riscv: refactor clock driver
* bdda8c5d - riscv/riscv: add clock driver using stimecmp
* 831678d0 - riscv: support CPU counter in s-mode
* 1c9d588f - riscv: use software irq in tm27 with s-mode
* 05a18c31 - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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