Documentation | user/bsps/arm: Add documentation for Xilinx Versal RPU BSP (!209)

[Kinsey Moore (@opticron)]

Kinsey Moore commented on a discussion on user/bsps/arm/xilinx-versal-rpu.md: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/209#note_138490

 > +# Xilinx Versal RPU
 > +
 > +This BSP supports the Real-time Processing Unit (RPU) on Xilinx Versal
 > + Adaptive SoCs. The RPU has two Cortex-R5 cores which can operate in lock-step
 > + or split mode. Basic hardware initialization is performed by the Cortex-R5
 > + BSP. This BSP supports the GICv2 interrupt controller available to the RPU
 > + subsystem. Since the RPU subsystem only varies in speed, this BSP should be
 > + functional across all chip variants as well as on Xilinx's QEMU branch.
 > +There are three BSP variants available for customization:
 > +
 > +- `versal_rpu_lock_step`
 > +- `versal_rpu_split_0`
 > +- `versal_rpu_split_1`
 > +
 > +The `versal_rpu_lock_step` BSP variant is intended to be used for the RPU in
 > +lock-step mode. In this case, the ATCM and BTCM could be used as a combined

Before the first use, yes.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/209#note_138490
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