RTEMS | [sparc] Implement _CPU_Spin_wait() in cpu.h for SMP spin-loop throttling (#5645)

[Wayne Thornton (@wmthornton-dev)]

Issue created by Wayne Thornton: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5645



## Description:
We have introduced a new Super Core architecture hook, `_CPU_Spin_wait()`, to mitigate aggressive speculative execution penalties, reduce thermal load, and lower bus contention during SMP spin-wait polling loops. The reference template is currently documented in `cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h` and natively implemented for `x86_64` upon merging of rtems/rtos/rtems!1256.

The sparc architecture port (targeting SMP-capable processors such as LEON3 and LEON4) needs to explicitly define this interface in `cpukit/score/cpu/sparc/include/rtems/score/cpu.h`.

Suggested Implementation:
Evaluate whether LEON3/LEON4 processor models provide a hardware-specific yield or pipeline stall hint. If no dedicated hardware throttling instruction is available for the target ASIC/FPGA implementation, the port should explicitly formalize the compiler memory barrier fallback:

```
static inline void _CPU_Spin_wait( void )
{
  RTEMS_COMPILER_MEMORY_BARRIER();
}
#define _CPU_Spin_wait _CPU_Spin_wait
```

Verification:
Validate that the implementation compiles cleanly on `sparc/leon3` and `sparc/leon4` and passes the standalone SMP spin-wait test suite: `testsuites/smptests/smpspinwait01`. Once defined, the preprocessor will automatically override the temporary test-level fallback in `init.c`.

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-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5645
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