RTEMS | risc-v: support running in s-mode (!1086)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086

* a41583c3...ea1d5dcd - 2 commits from branch `main`

* ea31fe6c - spec/build: add RISCV_USE_S_MODE option
* b5264e46 - riscv: support s-mode during boot
* d7ff9f4d - bsps/riscv: support SMP secondary processors
* aed36816 - bsps/riscv: support s-mode timer in clock driver
* cdb253ba - bsps/riscv: support s-mode irq handling
* 598332c7 - riscv: enable s-mode in CPU port
* 348e855f - cpukit/riscv: remove s/m prefix on frame context regs
* 8ed01d70 - riscv/riscv: refactor clock driver
* 7f46d3ca - riscv/riscv: add clock driver using stimecmp
* 7209cd44 - riscv: support CPU counter in s-mode
* 95a9e7ae - riscv: use software irq in tm27 with s-mode
* dda1d34e - riscv: avoid accessing per_cpu mtime variable in s-mode
* e8d948eb - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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