RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

[saksham balsane (@sak8644)]

saksham balsane created a merge request: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124

Project:Branches: sak8644/rtems:fix-riscv-spurious-interrupt to rtems/rtos/rtems:main
Author:   saksham balsane



## Summary

The RISC-V S-mode BSP incorrectly uses `SIP_STIP` when enabling and disabling the software interrupt vector.

In the software interrupt path (`RISCV_INTERRUPT_VECTOR_SOFTWARE`), the correct CSR bit is `SIP_SSIP`. Using `SIP_STIP` instead manipulates the supervisor timer interrupt bit, which can lead to spurious interrupts when `CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER` is not defined.

This patch replaces `SIP_STIP` with `SIP_SSIP` in the following functions:

- `bsp_interrupt_vector_enable()`
- `bsp_interrupt_vector_disable()`

The timer interrupt handling section (`RISCV_INTERRUPT_VECTOR_TIMER`) remains unchanged.

## Impact

This ensures that the BSP correctly enables and disables the supervisor software interrupt instead of accidentally manipulating the timer interrupt bit, which may cause `RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT`.

## Testing

The RTEMS build completed successfully after applying the change.

Fixes: #5522 

## Generative AI

AI assistance was used to help draft the merge request description. The code change itself was implemented and verified manually.

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