RTEMS | RISC-V S-mode BSP can trigger spurious interrupts (#5522)

[saksham balsane (@sak8644)]

saksham balsane commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5522#note_145658


hi @matteo.concas ,Could you please take a look at this MR It fixes the use of `SIP_STIP` in the RISC-V S-mode BSP software interrupt path and replaces it with the correct CSR bit `SIP_SSIP`. The BSP builds successfully after the change.

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5522#note_145658
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