RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

[Kinsey Moore (@opticron)]

Kinsey Moore started a new discussion on bsps/riscv/riscv/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145705

 >  
 >    if (vector == RISCV_INTERRUPT_VECTOR_TIMER) {
 >  #ifdef RISCV_USE_S_MODE
 > -    *pending = (read_csr(sip) & SIP_STIP) != 0;
 > +  set_csr(sie, SIP_SSIP);
 >  #else
 > -    *pending = (read_csr(mip) & MIP_MTIP) != 0;
 > +  set_csr(mie, MIP_MSIP);

Why are these now setting the CSR instead of reading from it?

If this is an action taken relating to a timer interrupt vector, why is this now adjustig the software interrupt vector?

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145705
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