RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

Tue Mar 17 16:09:29 UTC 2026

saksham balsane commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145864

hi @gedare  i have performed the runtime testing using  QEMU with the RISC-V `rv64imac` BSP I built RTEMS with the RISC-V toolchain and executed the `hello` sample on the build and execution completed successfully confirming that the system runs correctly with the updated logic

![image.png](/uploads/ba046e166c8c8b2eae52c57339c44150/image.png){width=664 height=197}

i planning to extend this further to explicitly trigger and observe the software interrupt behavior if needed.

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145864
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