RTEMS | ESP-32 C5 and C6 (#5527)

[Amar Takhar (@amar)]

Amar Takhar created an issue: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527



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## Summary

There is initial work for the ESP-32 C3 by @opticron located here:

* [https://gitlab.rtems.org/opticron/rtems/-/tree/brmain-add-esp32c3-bsp](https://gitlab.rtems.org/opticron/rtems/-/tree/brmain-add-esp32c3-bsp "https://gitlab.rtems.org/opticron/rtems/-/tree/brmain-add-esp32c3-bsp")

The goal of this project would be to port this effort over to the ESP-32 C5 and C6 with at least support for:

* Booting and running tests
* Partial or full GPIO support
  * To be determined by person completing the project
* sysctl access to ESP32 internals

The heavy lifting has been done by the ESP-32 C3 project though the interrupts are different for C5,C6 both of these two boards are extremely similar.

Note:  You must have these boards in your hand before GSoC starts and demonstrate the ability to run any type of software on it.  This could be esphome an arduino sketch or micropython.  It does not matter what you pick.

If you can show to us these are ordered but not arrive in time we can find an alternate way for you to complete this, reach out to us.

## Approach

<!--Describe the general techniques to use to complete the project.-->

Use the ESP32 C3 BSP as an example.

## Knowledge/Skills

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A general knowledge of C is required.

## Possible Mentors

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@ppisa  @opticron @amar

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527
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