RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Gedare Bloom (@gedare)]

Gedare Bloom started a new discussion on bsps/riscv/esp32/start/bspstart.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147636

 > +#define TIMG_WDTCONFIG0_REG (uintptr_t) 0x48
 > +#define TIMG_WDTCONFIG0_EN BSP_BIT32(31)
 > +
 > +#define TIMG_READ(reg) READ_REG(TIMG_BASE, reg)
 > +#define TIMG_WRITE(reg, value) WRITE_REG(TIMG_BASE, reg, value)
 > +
 > +#define READ_REG(base, reg) *(volatile uint32_t *)(base + reg)
 > +#define WRITE_REG(base, reg, value) *(volatile uint32_t *)(base + reg) = value
 > +
 > +void bsp_start(void)
 > +{
 > +  /* disable RTC watchdog write protection */
 > +  RTC_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDTWPROTECT_KEY);
 > +
 > +  /* disable the RTC watchdog */
 > +  uint32_t wdt_config0 = RTC_READ(RTC_CNTL_WDTCONFIG0_REG);

put decls at start of block

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147636
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