RTEMS | Support RISC-V MMU in S-Mode (#5540)

[Gedare Bloom (@gedare)]

Gedare Bloom created an issue: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5540

Assignee: Gedare Bloom

## Summary
<!--
Please provide as much information as possible such as error messages or attaching logs
-->

Now that S-mode is supported (#3337) we can configure and enable the MMU for RISC-V when executing in S-mode. The goal of this issue is to enable a static identity mapping for RISC-V with S-Mode supporting 32-bit (Sv32) and 64-bit (Sv39) MMU configurations. Extension to Sv48 should also be considered, and the design should stick close to established BSP-layer APIs for MMU management like in the Arm and Aarch64 BSPs.

## Steps to reproduce


<!-- Pre-set options
- milestone
-->

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5540
You're receiving this email because of your account on gitlab.rtems.org.


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20260331/9342c0fd/attachment.htm>