RTEMS | bsps/riscv: Use the time CSR on the GR765 (!1571)

[Matteo Concas (@matteo.concas)]

Matteo Concas started a new discussion on spec/build/cpukit/optriscvusetimecsr.yml: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1571#note_162386

 > +- env-enable: null
 > +- define-condition: null
 > +build-type: option
 > +copyrights:
 > +- Copyright (C) 2026 embedded brains GmbH & Co. KG
 > +default:
 > +- enabled-by: riscv/gr765
 > +  value: true
 > +- enabled-by: true
 > +  value: false
 > +description: |
 > +  If set to true, then the CPU counter and the clock driver read the time CSR.
 > +  Set it only if the processor executes a read of the time CSR without a trap
 > +  and if all harts read the same value.  If set to false, then in machine mode
 > +  the CPU counter and the clock driver read the mtime register of the CLINT.
 > +  The GR765 implements the time CSR, see GR765-DSUM, section 12.1.1, table 54.

I don't think BSP specific information belong here.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1571#note_162386
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