RTEMS | bsps/aarch64: The cache size functions report wrong sizes (#5805)

[Sebastian Huber (@sebhub)]

Issue created by Sebastian Huber: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5805



The cache size functions of the AArch64 BSPs in `bsps/aarch64/shared/cache/cache.c` report wrong sizes. The table lists the defects.

| Defect | Effect |
| ------ | ------ |
| The functions add the offset of four to the line size field of `CCSIDR_EL1` twice. | Each cache level reports 16 times its size. |
| Level zero writes the reserved level field seven into `CSSELR_EL1`. | The size of level zero depends on the core. |
| The instruction cache size of a unified level selects an instruction cache. | The function reads the geometry of a cache which does not exist. |

`rtems_cache_get_data_cache_size( 0 )` sizes the chunk of the runtime measurement framework `T_measure_runtime()`. On the LS1046A, the framework dirtied 64 MiB instead of 4 MiB per sample, so a performance test ran for a multiple of its expected time.

The validation test `tc-cache.c` calls the cache size directives and checks no value.

Found while measuring the runtime of the red-black tree on AArch64 boards. This description was created with Claude Code assistance.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5805
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