RTEMS | bsps/aarch64: Fix the cache size functions (!1525)

[Sebastian Huber (@sebhub)]

Sebastian Huber created a merge request: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1525

Project:Branches: sebhub/rtems:up/aarch64-cache-size to rtems/rtos/rtems:main
Author: Sebastian Huber

## Summary

Issue #5805: The cache size functions report wrong sizes

Add the line size offset once, map level zero to the level of
coherency, and select the data, the instruction or the unified cache
of a level by the cache type in `CLIDR_EL1`.  The validation test
`tc-cache.c` checks each level against the size which the cache
geometry registers specify.

`ts-validation-cache` and `ts-validation-0` pass on the ZCU104 and the
LS1046A boards and on Qemu.

**BSP** `aarch64/zynqmp_apu` · **Simulator** Qemu, `-machine xlnx-zcu102`

## AI Details
<!-- Make sure you have read our statement at https://www.rtems.org/generative-ai/ -->

### Prompt used

None as a single prompt.  The work was done in an interactive Claude Code
session on the RTEMS tree.  The task was to find why a performance test
ran for a multiple of its expected time on an AArch64 board, and to fix
the cause.  Each change was directed and reviewed.

### AI model used

Claude Opus 5.5 (claude-opus-5-5), through Claude Code.

### How AI was used for the contribution

- ( ) Formatting
- (x) Test creation.
- (x) Code comments.
- ( ) The entire contribution was generated using AI
- ( ) AI code completion such as Copilot in VSCode.

The diagnosis, the test and the implementation were produced in that
session under my direction, and the commit message was drafted there.

### Access

I have not used a product which claims copyright in its output, and I have
legitimate access to the one I used.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1525
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