RTEMS | bsps/riscv: Share the CLINT, PLIC and clock drivers (!1520)

[Sebastian Huber (@sebhub)]

Sebastian Huber commented on a discussion on bsps/riscv/include/bsp/riscv-fdt-irq.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1520#note_160969

 > + *   indicates a processor without a CLINT index.
 > + */
 > +static inline uint32_t riscv_clint_get_index( uint32_t cpu_index )
 > +{
 > +  if ( cpu_index >= RISCV_FDT_PROCESSOR_MAXIMUM ) {
 > +    return UINT32_MAX;
 > +  }
 > +
 > +  return riscv_fdt_clint_index[ cpu_index ];
 > +}
 > +#endif
 > +
 > +/**
 > + * @brief This define indicates that the system may have no PLIC.
 > + */
 > +#define RISCV_PLIC_MAY_BE_ABSENT

The difference is only pointer versus sentinel value. The documentation speaks of a missing item in all three cases. I will name them RISCV_CLINT_INDEX_MAY_BE_ABSENT, RISCV_PLIC_CONTEXT_MAY_BE_ABSENT and RISCV_PLIC_MAY_BE_ABSENT.

I would keep three defines, because each one removes a different check in irq.c. A BSP with a fixed PLIC may still have a hart without a PLIC context, for example the E51 hart of the PolarFire SoC in S-mode. I would move the defines into one block at the top of the header, with one description of the contract.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1520#note_160969
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