Build Linux: FAILED devel/spike on x86_64-linux-gnu (spike-1.1.0-x86_64-linux-gnu-1)
joel at rtems.org
joel at rtems.org
Sat Aug 24 03:37:16 UTC 2019
RTEMS Source Builder - Set Builder, 5 (4c51cd9c4b55)
Host: Linux-4.15.0-58-generic-x86_64-with-Ubuntu-18.04-bionic
Linux rtbf64a 4.15.0-58-generic #64-Ubuntu SMP Tue Aug 6 11:12:41 UTC
2019 x86_64 x86_64
Build Time: 0:00:07.608207
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
Build FAILED: spike-1.1.0-x86_64-linux-gnu-1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sd.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sfence_vma.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sh.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sll.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/slli.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/slliw.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sllw.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/slt.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/slti.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sltiu.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sltu.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sra.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/srai.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sraiw.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sraw.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sret.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/srl.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/srli.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/srliw.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/srlw.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sub.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/subw.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/sw.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/wfi.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/xor.h
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/insns/xori.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/interactive.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/jtag_dtm.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/jtag_dtm.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/memtracer.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/mmu.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/mmu.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/mulhi.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/opcodes.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/processor.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/processor.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/regnames.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/remote_bitbang.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/remote_bitbang.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/riscv.ac
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/riscv.mk.in
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/rocc.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/rocc.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/rom.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/sim.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/sim.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/simif.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/tracer.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/trap.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/riscv/trap.h
creating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/config.guess
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/config.sub
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/install.sh
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/mk-install-dirs.sh
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/scripts/vcs-version.sh
creating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_add.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_classify.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_div.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_eq.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_eq_signaling.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_isSignalingNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_le.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_le_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_lt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_lt_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_mul.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_mulAdd.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_rem.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_roundToInt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_sqrt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_sub.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_i32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_i32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_i64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_i64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_ui32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_ui32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_ui64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f128_to_ui64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_add.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_div.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_eq.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_eq_signaling.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_isSignalingNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_le.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_le_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_lt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_lt_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_mul.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_mulAdd.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_rem.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_roundToInt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_sqrt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_sub.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_i32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_i32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_i64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_i64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_ui32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_ui32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_ui64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f16_to_ui64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_add.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_classify.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_div.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_eq.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_eq_signaling.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_isSignalingNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_le.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_le_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_lt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_lt_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_mul.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_mulAdd.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_rem.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_roundToInt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_sqrt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_sub.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_i32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_i32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_i64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_i64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_ui32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_ui32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_ui64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f32_to_ui64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_add.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_classify.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_div.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_eq.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_eq_signaling.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_isSignalingNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_le.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_le_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_lt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_lt_quiet.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_mul.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_mulAdd.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_rem.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_roundToInt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_sqrt.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_sub.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_i32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_i32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_i64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_i64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_ui32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_ui32_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_ui64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/f64_to_ui64_r_minMag.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i32_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i32_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i32_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i32_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i64_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i64_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i64_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/i64_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/internals.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/platform.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/primitiveTypes.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/primitives.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_add128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_add256M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addCarryM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addComplCarryM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addMagsF128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addMagsF16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addMagsF32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_addMagsF64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_approxRecip32_1.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_approxRecipSqrt32_1.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_approxRecipSqrt_1Ks.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_approxRecip_1Ks.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_commonNaNToF128UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_commonNaNToF16UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_commonNaNToF32UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_commonNaNToF64UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_compare128M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_compare96M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_countLeadingZeros16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_countLeadingZeros32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_countLeadingZeros64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_countLeadingZeros8.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_eq128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_f128UIToCommonNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_f16UIToCommonNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_f32UIToCommonNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_f64UIToCommonNaN.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_le128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_lt128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul128By32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul128MTo256M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul128To256M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul64ByShifted32To128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul64To128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mul64To128M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mulAddF128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mulAddF16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mulAddF32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_mulAddF64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_negXM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normRoundPackToF128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normRoundPackToF16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normRoundPackToF32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normRoundPackToF64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normSubnormalF128Sig.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normSubnormalF16Sig.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normSubnormalF32Sig.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_normSubnormalF64Sig.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_propagateNaNF128UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_propagateNaNF16UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_propagateNaNF32UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_propagateNaNF64UI.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_remStepMBy32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundMToI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundMToUI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackMToI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackMToUI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToF128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToF16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToF32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToF64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToI32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToUI32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundPackToUI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundToI32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundToI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundToUI32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_roundToUI64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam128Extra.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam256M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shiftRightJam64Extra.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftLeft128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftLeft64To96M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRight128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightExtendM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightJam128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightJam128Extra.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightJam64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightJam64Extra.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_shortShiftRightM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_sub128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_sub1XM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_sub256M.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_subM.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_subMagsF128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_subMagsF16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_subMagsF32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/s_subMagsF64.c
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat.ac
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat.mk.in
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat_raiseFlags.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat_state.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/softfloat_types.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/specialize.h
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui32_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui32_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui32_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui32_to_f64.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui64_to_f128.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui64_to_f16.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui64_to_f32.c
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/softfloat/ui64_to_f64.c
creating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/disasm.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/spike-dasm.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/spike.cc
extracting: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/spike_main.ac
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/spike_main.mk.in
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/termios-xspike.cc
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/spike_main/xspike.cc
creating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/tests/
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/tests/ebreak.py
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/tests/ebreak.s
inflating: riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/tests/testlib.py
+ cd riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1
+ /bin/chmod -R a+rX,g-w,o-w .
+ cd /home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-1.1.0-x86_64-linux-gnu-1
+ SB_CXC=no
+ echo ==> clean %{buildroot}: /home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-1.1.0-x86_64-linux-gnu-1-joel
+ /bin/rm -rf /home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-1.1.0-x86_64-linux-gnu-1-joel
==> clean %{buildroot}: /home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-1.1.0-x86_64-linux-gnu-1-joel
+ /bin/mkdir -p /home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-1.1.0-x86_64-linux-gnu-1-joel
+ echo ==> %build:
==> %build:
+ pwd
+ build_top=/home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-1.1.0-x86_64-linux-gnu-1
+ cd riscv-fesvr-8d108a0a647901550d95925549337c2c3aec9ac8
+ ../riscv-fesvr-8d108a0a647901550d95925549337c2c3aec9ac8/configure --prefix=/home/joel/rtems-cron-5/tools/5
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking for g++... g++
checking whether we are using the GNU C++ compiler... yes
checking whether g++ accepts -g... yes
checking for ar... ar
checking for ranlib... ranlib
checking for a BSD-compatible install... /usr/bin/install -c
checking how to run the C preprocessor... gcc -E
checking for grep that handles long lines and -e... /bin/grep
checking for egrep... /bin/grep -E
checking for ANSI C header files... yes
configure: configuring default subproject : fesvr
checking for pthread_create in -lpthread... yes
configure: creating ./config.status
config.status: creating fesvr.mk
config.status: creating Makefile
config.status: creating riscv-fesvr.pc
config.status: creating config.h
+ make -j 4 all$
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/elfloader.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/htif.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/memif.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/dtm.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/syscall.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/device.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/rfb.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/context.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/htif_pthread.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/htif_hexwriter.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/dummy.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/option_parser.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/term.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/tsi.cc
g++ -fPIC -MMD -MP -Wall -O2 -std=c++11 -DPREFIX=\"/home/joel/rtems-cron-5/tools/5\" -I. -I./fesvr -c ./fesvr/elf2hex.cc
g++ -L. -Wl,-rpath,/home/joel/rtems-cron-5/tools/5/lib -shared -o libfesvr.so elfloader.o htif.o memif.o dtm.o syscall.o device.o rfb.o context.o htif_pthread.o htif_hexwriter.o dummy.o option_parser.o term.o tsi.o -lpthread
g++ -L. -Wl,-rpath,/home/joel/rtems-cron-5/tools/5/lib -o elf2hex elf2hex.o -lfesvr -lpthread
+ make install
./scripts/mk-install-dirs.sh /home/joel/rtems-cron-5/tools/5/include/fesvr
for file in fesvr/elf.h fesvr/elfloader.h fesvr/htif.h fesvr/dtm.h fesvr/memif.h fesvr/syscall.h fesvr/context.h fesvr/htif_pthread.h fesvr/htif_hexwriter.h fesvr/option_parser.h fesvr/term.h fesvr/device.h fesvr/rfb.h fesvr/tsi.h; \
do \
/usr/bin/install -c -m 444 $file /home/joel/rtems-cron-5/tools/5/include/fesvr; \
done
./scripts/mk-install-dirs.sh /home/joel/rtems-cron-5/tools/5/lib
for file in libfesvr.so; \
do \
/usr/bin/install -c -m 644 $file /home/joel/rtems-cron-5/tools/5/lib; \
done
./scripts/mk-install-dirs.sh /home/joel/rtems-cron-5/tools/5/bin
for file in elf2hex; \
do \
/usr/bin/install -c -m 555 $file /home/joel/rtems-cron-5/tools/5/bin; \
done
./scripts/mk-install-dirs.sh /home/joel/rtems-cron-5/tools/5/lib/pkgconfig/
for file in riscv-fesvr.pc; \
do \
/usr/bin/install -c -m 444 $file /home/joel/rtems-cron-5/tools/5/lib/pkgconfig/; \
done
+ cd ../riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1
+ ../riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/configure --prefix=/home/joel/rtems-cron-5/tools/5 --with-fesvr=/home/joel/rtems-cron-5/tools/5
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking for g++... g++
checking whether we are using the GNU C++ compiler... yes
checking whether g++ accepts -g... yes
checking for ar... ar
checking for ranlib... ranlib
checking for dtc... no
configure: error: device-tree-compiler not found
shell cmd failed: /bin/sh -ex /home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-1.1.0-x86_64-linux-gnu-1/do-build
error: building spike-1.1.0-x86_64-linux-gnu-1
See error report: rsb-report-spike-1.1.0-x86_64-linux-gnu-1.txt
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Sizes
=====
No packages built
Output
======
config: devel/spike-1.1.0.cfg
package: spike-1.1.0-x86_64-linux-gnu-1
building: spike-1.1.0-x86_64-linux-gnu-1
error: building spike-1.1.0-x86_64-linux-gnu-1
Build FAILED
See error report: rsb-report-spike-1.1.0-x86_64-linux-gnu-1.txt
error: building spike-1.1.0-x86_64-linux-gnu-1
Mailing report: build at rtems.org
Report
======
More information about the build
mailing list