Build FreeBSD: FAILED devel/spike on x86_64-freebsd12.1 (spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1)

joel at rtems.org joel at rtems.org
Fri Mar 13 07:14:05 UTC 2020


RTEMS Source Builder - Set Builder, 5 (af7f19889e4d)

Host: FreeBSD-12.1-RELEASE-p2-amd64-64bit-ELF
       FreeBSD rtbf64b 12.1-RELEASE-p2 FreeBSD 12.1-RELEASE-p2 GENERIC amd64
       amd64

Build Time: 0:00:11.620080

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Build FAILED: spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
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x -rw-rw-r--  0 root   root      359 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vsxe_v.h
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x -rw-rw-r--  0 root   root      117 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwadd_vv.h
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x -rw-rw-r--  0 root   root      138 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmaccsu_vv.h
x -rw-rw-r--  0 root   root      139 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmaccsu_vx.h
x -rw-rw-r--  0 root   root      123 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmaccu_vv.h
x -rw-rw-r--  0 root   root      124 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmaccu_vx.h
x -rw-rw-r--  0 root   root      139 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmaccus_vx.h
x -rw-rw-r--  0 root   root      117 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmul_vv.h
x -rw-rw-r--  0 root   root      118 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmul_vx.h
x -rw-rw-r--  0 root   root      413 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmulsu_vv.h
x -rw-rw-r--  0 root   root      414 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmulsu_vx.h
x -rw-rw-r--  0 root   root      119 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmulu_vv.h
x -rw-rw-r--  0 root   root      119 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwmulu_vx.h
x -rw-rw-r--  0 root   root       79 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwredsum_vs.h
x -rw-rw-r--  0 root   root       80 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwredsumu_vs.h
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x -rw-rw-r--  0 root   root       60 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsmaccsu_vv.h
x -rw-rw-r--  0 root   root       60 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsmaccsu_vx.h
x -rw-rw-r--  0 root   root       57 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsmaccu_vv.h
x -rw-rw-r--  0 root   root       54 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsmaccu_vx.h
x -rw-rw-r--  0 root   root       61 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsmaccus_vx.h
x -rw-rw-r--  0 root   root      117 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsub_vv.h
x -rw-rw-r--  0 root   root      118 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsub_vx.h
x -rw-rw-r--  0 root   root       99 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsub_wv.h
x -rw-rw-r--  0 root   root      100 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsub_wx.h
x -rw-rw-r--  0 root   root      119 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsubu_vv.h
x -rw-rw-r--  0 root   root      120 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsubu_vx.h
x -rw-rw-r--  0 root   root      101 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsubu_wv.h
x -rw-rw-r--  0 root   root      102 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vwsubu_wx.h
x -rw-rw-r--  0 root   root       45 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vxor_vi.h
x -rw-rw-r--  0 root   root       43 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/riscv/insns/vxor_vv.h
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x -rwxrwxr-x  0 root   root     4772 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/scripts/install.sh
x -rwxrwxr-x  0 root   root      736 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/scripts/mk-install-dirs.sh
x -rwxrwxr-x  0 root   root     4117 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/scripts/vcs-version.sh
x drwxrwxr-x  0 root   root        0 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/
x -rw-rw-r--  0 root   root     2892 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_add.c
x -rwxrwxr-x  0 root   root     1220 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_classify.c
x -rw-rw-r--  0 root   root     7769 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_div.c
x -rw-rw-r--  0 root   root     2690 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_eq.c
x -rw-rw-r--  0 root   root     2527 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_eq_signaling.c
x -rw-rw-r--  0 root   root     2071 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_isSignalingNaN.c
x -rw-rw-r--  0 root   root     2748 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_le.c
x -rw-rw-r--  0 root   root     2927 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_le_quiet.c
x -rw-rw-r--  0 root   root     2744 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_lt.c
x -rw-rw-r--  0 root   root     2923 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_lt_quiet.c
x -rw-rw-r--  0 root   root     6117 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_mul.c
x -rw-rw-r--  0 root   root     2395 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_mulAdd.c
x -rw-rw-r--  0 root   root     7468 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_rem.c
x -rw-rw-r--  0 root   root     6600 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_roundToInt.c
x -rw-rw-r--  0 root   root     8649 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_sqrt.c
x -rw-rw-r--  0 root   root     2892 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_sub.c
x -rw-rw-r--  0 root   root     3837 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_to_f16.c
x -rw-rw-r--  0 root   root     3845 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_to_f32.c
x -rw-rw-r--  0 root   root     3977 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f128_to_f64.c
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x -rw-rw-r--  0 root   root     2607 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f16_add.c
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x -rw-rw-r--  0 root   root     2462 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f16_eq.c
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x -rw-rw-r--  0 root   root     2477 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/f16_le.c
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x -rw-rw-r--  0 root   root     2352 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_negXM.c
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x -rw-rw-r--  0 root   root     2382 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normRoundPackToF16.c
x -rw-rw-r--  0 root   root     2382 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normRoundPackToF32.c
x -rw-rw-r--  0 root   root     2385 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normRoundPackToF64.c
x -rw-rw-r--  0 root   root     2579 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normSubnormalF128Sig.c
x -rw-rw-r--  0 root   root     2144 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normSubnormalF16Sig.c
x -rw-rw-r--  0 root   root     2146 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normSubnormalF32Sig.c
x -rw-rw-r--  0 root   root     2147 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_normSubnormalF64Sig.c
x -rw-rw-r--  0 root   root     3012 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_propagateNaNF128UI.c
x -rw-rw-r--  0 root   root     2604 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_propagateNaNF16UI.c
x -rw-rw-r--  0 root   root     2598 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_propagateNaNF32UI.c
x -rw-rw-r--  0 root   root     2598 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_propagateNaNF64UI.c
x -rw-rw-r--  0 root   root     3169 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_remStepMBy32.c
x -rw-rw-r--  0 root   root     3514 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundMToI64.c
x -rw-rw-r--  0 root   root     3408 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundMToUI64.c
x -rw-rw-r--  0 root   root     3513 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackMToI64.c
x -rw-rw-r--  0 root   root     3407 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackMToUI64.c
x -rw-rw-r--  0 root   root     6709 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToF128.c
x -rw-rw-r--  0 root   root     4763 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToF16.c
x -rw-rw-r--  0 root   root     4778 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToF32.c
x -rw-rw-r--  0 root   root     4880 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToF64.c
x -rw-rw-r--  0 root   root     3434 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToI32.c
x -rw-rw-r--  0 root   root     3459 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToI64.c
x -rw-rw-r--  0 root   root     3303 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToUI32.c
x -rw-rw-r--  0 root   root     3348 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundPackToUI64.c
x -rw-rw-r--  0 root   root     3441 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundToI32.c
x -rw-rw-r--  0 root   root     3460 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundToI64.c
x -rw-rw-r--  0 root   root     3310 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundToUI32.c
x -rw-rw-r--  0 root   root     3349 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_roundToUI64.c
x -rw-rw-r--  0 root   root     2562 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam128.c
x -rw-rw-r--  0 root   root     2758 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam128Extra.c
x -rw-rw-r--  0 root   root     4022 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam256M.c
x -rw-rw-r--  0 root   root     2076 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam32.c
x -rw-rw-r--  0 root   root     2076 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam64.c
x -rw-rw-r--  0 root   root     2290 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shiftRightJam64Extra.c
x -rw-rw-r--  0 root   root     2137 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftLeft128.c
x -rw-rw-r--  0 root   root     2183 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftLeft64To96M.c
x -rw-rw-r--  0 root   root     2140 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRight128.c
x -rw-rw-r--  0 root   root     2614 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightExtendM.c
x -rw-rw-r--  0 root   root     2265 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightJam128.c
x -rw-rw-r--  0 root   root     2295 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightJam128Extra.c
x -rw-rw-r--  0 root   root     2061 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightJam64.c
x -rw-rw-r--  0 root   root     2171 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightJam64Extra.c
x -rw-rw-r--  0 root   root     2543 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_shortShiftRightM.c
x -rw-rw-r--  0 root   root     2109 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_sub128.c
x -rw-rw-r--  0 root   root     2293 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_sub1XM.c
x -rw-rw-r--  0 root   root     2405 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_sub256M.c
x -rw-rw-r--  0 root   root     2496 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_subM.c
x -rw-rw-r--  0 root   root     4748 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_subMagsF128.c
x -rw-rw-r--  0 root   root     7061 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_subMagsF16.c
x -rw-rw-r--  0 root   root     5481 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_subMagsF32.c
x -rw-rw-r--  0 root   root     5533 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/s_subMagsF64.c
x -rw-rw-r--  0 root   root        0 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat.ac
x -rw-rw-r--  0 root   root    17886 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat.h
x -rw-rw-r--  0 root   root     4473 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat.mk.in
x -rw-rw-r--  0 root   root     2390 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat_raiseFlags.c
x -rw-rw-r--  0 root   root     2253 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat_state.c
x -rw-rw-r--  0 root   root     4046 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/softfloat_types.h
x -rw-rw-r--  0 root   root    21362 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/specialize.h
x -rw-rw-r--  0 root   root     2305 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui32_to_f128.c
x -rw-rw-r--  0 root   root     2547 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui32_to_f16.c
x -rw-rw-r--  0 root   root     2202 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui32_to_f32.c
x -rw-rw-r--  0 root   root     2269 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui32_to_f64.c
x -rw-rw-r--  0 root   root     2551 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui64_to_f128.c
x -rw-rw-r--  0 root   root     2521 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui64_to_f16.c
x -rw-rw-r--  0 root   root     2521 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui64_to_f32.c
x -rw-rw-r--  0 root   root     2276 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/softfloat/ui64_to_f64.c
x drwxrwxr-x  0 root   root        0 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/
x -rw-rw-r--  0 root   root    40023 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/disasm.cc
x -rw-rw-r--  0 root   root     1556 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/spike-dasm.cc
x -rw-rw-r--  0 root   root     1542 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/spike-log-parser.cc
x -rw-rw-r--  0 root   root    12007 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/spike.cc
x -rw-rw-r--  0 root   root        0 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/spike_main.ac
x -rw-rw-r--  0 root   root      224 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/spike_main.mk.in
x -rw-rw-r--  0 root   root      611 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/termios-xspike.cc
x -rw-rw-r--  0 root   root     2064 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/spike_main/xspike.cc
x drwxrwxr-x  0 root   root        0 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/tests/
x -rwxrwxr-x  0 root   root      715 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/tests/ebreak.py
x -rw-rw-r--  0 root   root       76 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/tests/ebreak.s
x -rw-rw-r--  0 root   root     3439 Oct 18 17:20 riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a/tests/testlib.py
+ tar_exit=0
+ cd riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a
+ /bin/chmod -R a+rX,g-w,o-w .
+ cd /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
==> clean %{buildroot}: /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1-1002
+ SB_CXC=no
+ echo '==> clean %{buildroot}: /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1-1002'
+ /bin/rm -rf /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1-1002
+ /bin/mkdir -p /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1-1002
+ echo '==> %build:'
==> %build:
+ pwd
+ build_top=/usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
+ cd riscv-isa-sim-fb27391bf65ed867b62ef40b726a21ac839fa37a
+ ./configure '--prefix=/home/joel/rtems-cron-5/tools/5' '--with-fesvr=/home/joel/rtems-cron-5/tools/5'
configure: WARNING: unrecognized options: --with-fesvr
checking build system type... x86_64-unknown-freebsd12.1
checking host system type... x86_64-unknown-freebsd12.1
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables... 
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking for g++... g++
checking whether we are using the GNU C++ compiler... yes
checking whether g++ accepts -g... yes
checking for ar... ar
checking for ranlib... ranlib
checking for dtc... /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/tmp/sb-1002/devel/spike/home/joel/rtems-cron-5/tools/5/bin/dtc
checking how to run the C++ preprocessor... g++ -E
checking for grep that handles long lines and -e... /usr/bin/grep
checking for egrep... /usr/bin/grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking whether byte ordering is bigendian... no
checking for a BSD-compatible install... /usr/bin/install -c
checking for ANSI C header files... (cached) yes
checking for __int128_t... yes
checking whether the linker accepts -Wl,--export-dynamic... yes
configure: configuring default subproject : fesvr
checking for pthread_create in -lpthread... yes
configure: configuring default subproject : riscv
checking for library containing dlopen... none required
checking for pthread_create in -lpthread... (cached) yes
configure: configuring default subproject : dummy_rocc
configure: configuring default subproject : softfloat
configure: configuring default subproject : spike_main
configure: creating ./config.status
config.status: creating fesvr.mk
config.status: creating riscv.mk
config.status: creating dummy_rocc.mk
config.status: creating softfloat.mk
config.status: creating spike_main.mk
config.status: creating Makefile
config.status: creating riscv-spike.pc
config.status: creating riscv-riscv.pc
config.status: creating riscv-fesvr.pc
config.status: creating riscv-softfloat.pc
config.status: creating riscv-dummy_rocc.pc
config.status: creating riscv-spike_main.pc
config.status: creating config.h
configure: WARNING: unrecognized options: --with-fesvr
+ gmake -j 4 'all$'
gmake: *** No rule to make target 'all$'.  Stop.
shell cmd failed: /bin/sh -ex  /usr/home/joel/rtems-cron-5/rtems-source-builder/bare/build/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1/do-build
error: building spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
  See error report: rsb-report-spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1.txt
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 


Output
======

Build Set: devel/spike
config: devel/dtc-1.4.1-1.cfg
package: dtc-1.4.1-x86_64-freebsd12.1-1
download: https://www.kernel.org/pub/software/utils/dtc/dtc-1.4.1.tar.gz -> sources/dtc-1.4.1.tar.gz
 redirect: https://mirrors.edge.kernel.org/pub/software/utils/dtc/dtc-1.4.1.tar.gz
building: dtc-1.4.1-x86_64-freebsd12.1-1
sizes: dtc-1.4.1-x86_64-freebsd12.1-1: 3.100MB (installed: 885.144KB)
cleaning: dtc-1.4.1-x86_64-freebsd12.1-1
reporting: devel/dtc-1.4.1-1.cfg -> dtc-1.4.1-x86_64-freebsd12.1-1.txt
reporting: devel/dtc-1.4.1-1.cfg -> dtc-1.4.1-x86_64-freebsd12.1-1.xml
config: devel/spike-1.1.0.cfg
package: spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
download: https://github.com/riscv/riscv-isa-sim/archive/fb27391bf65ed867b62ef40b726a21ac839fa37a.tar.gz -> sources/spike-fb27391bf65ed867b62ef40b726a21ac839fa37a.tar.gz
 redirect: https://codeload.github.com/riscv/riscv-isa-sim/tar.gz/fb27391bf65ed867b62ef40b726a21ac839fa37a
building: spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
error: building spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
Build FAILED
  See error report: rsb-report-spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1.txt
error: building spike-fb27391bf65ed867b62ef40b726a21ac839fa37a-x86_64-freebsd12.1-1
Mailing report: build at rtems.org

Report
======

==============================================================================
RTEMS Tools Project <users at rtems.org> Fri Mar 13 02:14:01 2020
==============================================================================
Report: devel/dtc-1.4.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
   1: origin: git://git.rtems.org/rtems-source-builder.git
 Status:
  Clean
 Head:
  Commit: af7f19889e4d0787d40929a5cc7e4eb873b1d8fc
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.4.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.4.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.4.1-x86_64-freebsd12.1-1
 Config: devel/dtc-1.4.1-1.cfg
 Summary:
  Device Tree Compiler v1.4.1 for target  on host x86_64-freebsd12.1
 URL:
  http://www.jdl.com/software/
 Version:
  1.4.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.4.1.tar.gz
       sha256: 03e74e4ee9378be15f19eb24197dfa32070efc3c85e93269e56d7ade133e359f
  Patches: 0
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.4.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.4.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "/usr/bin/cc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "/usr/bin/c++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  gmake PREFIX=/home/joel/rtems-cron-5/tools/5
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.4.1
  gmake DESTDIR=$SB_BUILD_ROOT PREFIX=/home/joel/rtems-cron-5/tools/5 install
  cd ${build_top}
==============================================================================
RTEMS Tools Project <users at rtems.org> Fri Mar 13 02:14:01 2020
==============================================================================
Report: devel/dtc-1.4.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
   1: origin: git://git.rtems.org/rtems-source-builder.git
 Status:
  Clean
 Head:
  Commit: af7f19889e4d0787d40929a5cc7e4eb873b1d8fc
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.4.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.4.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.4.1-x86_64-freebsd12.1-1
 Config: devel/dtc-1.4.1-1.cfg
 Summary:
  Device Tree Compiler v1.4.1 for target  on host x86_64-freebsd12.1
 URL:
  http://www.jdl.com/software/
 Version:
  1.4.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.4.1.tar.gz
       sha256: 03e74e4ee9378be15f19eb24197dfa32070efc3c85e93269e56d7ade133e359f
  Patches: 0
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.4.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.4.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "/usr/bin/cc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "/usr/bin/c++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  gmake PREFIX=/home/joel/rtems-cron-5/tools/5
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.4.1
  gmake DESTDIR=$SB_BUILD_ROOT PREFIX=/home/joel/rtems-cron-5/tools/5 install
  cd ${build_top}


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