Build Linux: FAILED devel/spike on x86_64-linux-gnu (spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1)
OAR Tester
rtems-tester at oarcorp.com
Sat Feb 19 10:54:08 UTC 2022
RTEMS Source Builder - Set Builder, 5 (52ca7d38aae2)
Host: Linux-5.11.0-49-generic-x86_64-with-Ubuntu-21.04-hirsute
Linux VM-Ubuntu21.rtems.com 5.11.0-49-generic #55-Ubuntu SMP Wed Jan 12
17:36:34 UTC 2022 x86_64 x86_64
Build Time: 0:00:06.841906
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Build FAILED: spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
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drwxrwxr-x root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/
-rwxrwxr-x root/root 44892 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/config.guess
-rwxrwxr-x root/root 33463 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/config.sub
-rwxrwxr-x root/root 4772 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/install.sh
-rwxrwxr-x root/root 736 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/mk-install-dirs.sh
-rwxrwxr-x root/root 4117 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/scripts/vcs-version.sh
drwxrwxr-x root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/
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-rw-rw-r-- root/root 3434 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundPackToI32.c
-rw-rw-r-- root/root 3459 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundPackToI64.c
-rw-rw-r-- root/root 3303 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundPackToUI32.c
-rw-rw-r-- root/root 3348 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundPackToUI64.c
-rw-rw-r-- root/root 3441 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundToI32.c
-rw-rw-r-- root/root 3460 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundToI64.c
-rw-rw-r-- root/root 3310 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundToUI32.c
-rw-rw-r-- root/root 3349 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_roundToUI64.c
-rw-rw-r-- root/root 2562 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam128.c
-rw-rw-r-- root/root 2758 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam128Extra.c
-rw-rw-r-- root/root 4022 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam256M.c
-rw-rw-r-- root/root 2076 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam32.c
-rw-rw-r-- root/root 2076 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam64.c
-rw-rw-r-- root/root 2290 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shiftRightJam64Extra.c
-rw-rw-r-- root/root 2137 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftLeft128.c
-rw-rw-r-- root/root 2183 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftLeft64To96M.c
-rw-rw-r-- root/root 2140 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRight128.c
-rw-rw-r-- root/root 2614 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightExtendM.c
-rw-rw-r-- root/root 2265 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightJam128.c
-rw-rw-r-- root/root 2295 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightJam128Extra.c
-rw-rw-r-- root/root 2061 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightJam64.c
-rw-rw-r-- root/root 2171 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightJam64Extra.c
-rw-rw-r-- root/root 2543 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_shortShiftRightM.c
-rw-rw-r-- root/root 2109 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_sub128.c
-rw-rw-r-- root/root 2293 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_sub1XM.c
-rw-rw-r-- root/root 2405 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_sub256M.c
-rw-rw-r-- root/root 2496 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_subM.c
-rw-rw-r-- root/root 4748 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_subMagsF128.c
-rw-rw-r-- root/root 7061 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_subMagsF16.c
-rw-rw-r-- root/root 5481 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_subMagsF32.c
-rw-rw-r-- root/root 5533 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/s_subMagsF64.c
-rw-rw-r-- root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat.ac
-rw-rw-r-- root/root 17886 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat.h
-rw-rw-r-- root/root 4473 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat.mk.in
-rw-rw-r-- root/root 2390 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat_raiseFlags.c
-rw-rw-r-- root/root 2253 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat_state.c
-rw-rw-r-- root/root 4046 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/softfloat_types.h
-rw-rw-r-- root/root 21362 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/specialize.h
-rw-rw-r-- root/root 2305 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui32_to_f128.c
-rw-rw-r-- root/root 2547 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui32_to_f16.c
-rw-rw-r-- root/root 2202 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui32_to_f32.c
-rw-rw-r-- root/root 2269 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui32_to_f64.c
-rw-rw-r-- root/root 2551 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui64_to_f128.c
-rw-rw-r-- root/root 2521 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui64_to_f16.c
-rw-rw-r-- root/root 2521 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui64_to_f32.c
-rw-rw-r-- root/root 2276 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/softfloat/ui64_to_f64.c
drwxrwxr-x root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/
-rw-rw-r-- root/root 40812 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/disasm.cc
-rw-rw-r-- root/root 1957 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/spike-dasm.cc
-rw-rw-r-- root/root 1556 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/spike-log-parser.cc
-rw-rw-r-- root/root 13687 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/spike.cc
-rw-rw-r-- root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/spike_main.ac
-rw-rw-r-- root/root 224 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/spike_main.mk.in
-rw-rw-r-- root/root 611 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/termios-xspike.cc
-rw-rw-r-- root/root 2064 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/spike_main/xspike.cc
drwxrwxr-x root/root 0 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/tests/
-rwxrwxr-x root/root 715 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/tests/ebreak.py
-rw-rw-r-- root/root 76 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/tests/ebreak.s
-rw-rw-r-- root/root 3439 2020-03-24 16:45 riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd/tests/testlib.py
+ tar_exit=0
+ cd riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd
+ /bin/chmod -R a+rX,g-w,o-w .
==> clean %{buildroot}: /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1-1002
+ cd /home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
+ SB_CXC=no
+ echo ==> clean %{buildroot}: /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1-1002
+ /bin/rm -rf /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1-1002
+ /bin/mkdir -p /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1-1002
+ echo ==> %build:
==> %build:
+ pwd
+ build_top=/home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
+ cd riscv-isa-sim-66b44bfbedda562a32e4a2cd0716afbf731b69cd
+ ./configure --prefix=/home/tester/rtems-cron-5/tools/5
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking for g++... g++
checking whether we are using the GNU C++ compiler... yes
checking whether g++ accepts -g... yes
checking for ar... ar
checking for ranlib... ranlib
checking for dtc... /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/sb-1002-staging/bin/dtc
checking how to run the C++ preprocessor... g++ -E
checking for grep that handles long lines and -e... /usr/bin/grep
checking for egrep... /usr/bin/grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking whether byte ordering is bigendian... no
checking for a BSD-compatible install... /usr/bin/install -c
checking for ANSI C header files... (cached) yes
checking for __int128_t... yes
checking whether the linker accepts -Wl,--export-dynamic... yes
configure: configuring default subproject : fesvr
checking for pthread_create in -lpthread... yes
configure: configuring default subproject : riscv
checking for library containing dlopen... -ldl
checking for pthread_create in -lpthread... (cached) yes
configure: configuring default subproject : dummy_rocc
configure: configuring default subproject : softfloat
configure: configuring default subproject : spike_main
configure: creating ./config.status
config.status: creating fesvr.mk
config.status: creating riscv.mk
config.status: creating dummy_rocc.mk
config.status: creating softfloat.mk
config.status: creating spike_main.mk
config.status: creating Makefile
config.status: creating riscv-spike.pc
config.status: creating riscv-riscv.pc
config.status: creating riscv-fesvr.pc
config.status: creating riscv-softfloat.pc
config.status: creating riscv-dummy_rocc.pc
config.status: creating riscv-spike_main.pc
config.status: creating config.h
+ make -j 8
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/elfloader.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/htif.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/memif.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/dtm.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/syscall.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/device.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/rfb.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/context.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/htif_pthread.cc
g++ -MMD -MP -DPREFIX=\"/home/tester/rtems-cron-5/tools/5\" -Wall -Wno-unused -g -O2 -std=c++11 -g -O2 -I. -I. -I./fesvr -I./riscv -I./dummy_rocc -I./softfloat -I./spike_main -fPIC -c ./fesvr/htif_hexwriter.cc
./fesvr/dtm.cc: In member function 'uint32_t dtm_t::get_xlen()':
./fesvr/dtm.cc:488:16: error: 'runtime_error' is not a member of 'std'
488 | throw std::runtime_error("FESVR DTM Does not support 128-bit");
| ^~~~~~~~~~~~~
./fesvr/dtm.cc:505:14: error: 'runtime_error' is not a member of 'std'
505 | throw std::runtime_error("FESVR DTM can't determine XLEN. Aborting");
| ^~~~~~~~~~~~~
./fesvr/dtm.cc:506:1: warning: control reaches end of non-void function [-Wreturn-type]
506 | }
| ^
make: *** [Makefile:347: dtm.o] Error 1
make: *** Waiting for unfinished jobs....
shell cmd failed: /bin/sh -ex /home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1/do-build
error: building spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
See error report: rsb-report-spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1.txt
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Output
======
Build Set: devel/spike
Build Set: devel/dtc.bset
config: devel/dtc-1.6.1-1.cfg
package: dtc-1.6.1-x86_64-linux-gnu-1
building: dtc-1.6.1-x86_64-linux-gnu-1
sizes: dtc-1.6.1-x86_64-linux-gnu-1: 5.174MB (installed: 1.428MB)
cleaning: dtc-1.6.1-x86_64-linux-gnu-1
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-linux-gnu-1.txt
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-linux-gnu-1.xml
staging: dtc-1.6.1-x86_64-linux-gnu-1 -> /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/sb-1002-staging
cleaning: dtc-1.6.1-x86_64-linux-gnu-1
Build Set: Time 0:00:04.008839
config: devel/spike-1.1.0.cfg
package: spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
building: spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
error: building spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
Build FAILED
See error report: rsb-report-spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1.txt
error: building spike-66b44bfbedda562a32e4a2cd0716afbf731b69cd-x86_64-linux-gnu-1
Mailing report: build at rtems.org
Report
======
==============================================================================
RTEMS Tools Project <users at rtems.org> Sat Feb 19 04:58:10 2022
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
Remotes:
[ remotes removed, contact sender for details ]
Status:
Clean
Head:
Commit: 52ca7d38aae2dacc45c56f2819befe21124b1476
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.6.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.6.1-x86_64-linux-gnu-1
Config: devel/dtc-1.6.1-1.cfg
Summary:
Device Tree Compiler v1.6.1 for target on host x86_64-linux-gnu
URL:
https://www.devicetree.org/
Version:
1.6.1
Release:
1
Sources: 1
1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
Patches: 0
Preparation:
build_top=$(pwd)
%setup source dtc -q -n dtc-1.6.1
%setup patch dtc -p1
cd ${build_top}
Build:
build_top=$(pwd)
cd dtc-1.6.1
# Build and build flags means force build == host
# gcc is not ready to be compiled with -std=gnu99
LDFLAGS="${SB_HOST_LDFLAGS}"
LIBS="${SB_HOST_LIBS}"
CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
CC_FOR_BUILD=${CC}
CXX_FOR_BUILD=${CXX}
export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
make PREFIX=/home/tester/rtems-cron-5/tools/5
cd ${build_top}
Install:
build_top=$(pwd)
rm -rf $SB_BUILD_ROOT
cd dtc-1.6.1
make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/tester/rtems-cron-5/tools/5 install
cd ${build_top}
==============================================================================
RTEMS Tools Project <users at rtems.org> Sat Feb 19 04:58:10 2022
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
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RTEMS Source Builder Repository Status
Remotes:
[ remotes removed, contact sender for details ]
Status:
Clean
Head:
Commit: 52ca7d38aae2dacc45c56f2819befe21124b1476
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Build Set: (1) devel/dtc-1.6.1-1.cfg
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Build Set: (2) devel/dtc-1.6.1-1.cfg
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Package: dtc-1.6.1-x86_64-linux-gnu-1
Config: devel/dtc-1.6.1-1.cfg
Summary:
Device Tree Compiler v1.6.1 for target on host x86_64-linux-gnu
URL:
https://www.devicetree.org/
Version:
1.6.1
Release:
1
Sources: 1
1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
Patches: 0
Preparation:
build_top=$(pwd)
%setup source dtc -q -n dtc-1.6.1
%setup patch dtc -p1
cd ${build_top}
Build:
build_top=$(pwd)
cd dtc-1.6.1
# Build and build flags means force build == host
# gcc is not ready to be compiled with -std=gnu99
LDFLAGS="${SB_HOST_LDFLAGS}"
LIBS="${SB_HOST_LIBS}"
CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
CC_FOR_BUILD=${CC}
CXX_FOR_BUILD=${CXX}
export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
make PREFIX=/home/tester/rtems-cron-5/tools/5
cd ${build_top}
Install:
build_top=$(pwd)
rm -rf $SB_BUILD_ROOT
cd dtc-1.6.1
make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/tester/rtems-cron-5/tools/5 install
cd ${build_top}
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