[rtems-test] i386/pc686: RTEMS_POSIX_API: Passed:576 Failed:6 Timeout:2 Test-Too-long:1 Invalid:5 Wrong:0
Joel Sherrill
joel at rtems.org
Fri Jan 14 00:55:51 UTC 2022
Testing time : 0:05:53.780985
Average test time: 0:00:00.589634
Host
====
Linux-3.10.0-1160.49.1.el7.x86_64-x86_64-with-centos-7.9.2009-Core (Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64 x86_64)
Configuration
=============
Version: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
Build : RTEMS_POSIX_API
Tools : 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
Summary
=======
Passed: 576
Failed: 6
User Input: 6
Expected Fail: 1
Indeterminate: 0
Benchmark: 3
Timeout: 2
Test too long: 1
Invalid: 5
Wrong Version: 0
Wrong Build: 0
Wrong Tools: 0
Wrong Header: 0
------------------
Total: 600
Failures:
dl06.exe
psx12.exe
sp69.exe
spfatal30.exe
tmcontext01.exe
minimum.exe
User Input:
dl10.exe
fileio.exe
top.exe
monitor.exe
capture.exe
termios.exe
Expected Fail:
psxfenv01.exe
Benchmark:
whetstone.exe
linpack.exe
dhrystone.exe
Timeouts:
ts-validation-0.exe
spfatal26.exe
Test too long:
sp20.exe
Invalid:
sptimecounter01.exe
spinternalerror01.exe
spfatal12.exe
spfatal33.exe
spfatal09.exe
Log
===
RTEMS Testing - Tester, 6.0.not_released
Command Line: /home/joel/rtems-cron-7/tools/7/bin/rtems-test --rtems-tools=/home/joel/rtems-cron-7/tools/7 --rtems-bsp=pc-qemu --log=run-pc-qemu.log --use-gitconfig --mail .
Host: Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64
Python: 2.7.5 (default, Nov 16 2020, 22:23:17) [GCC 4.8.5 20150623 (Red Hat 4.8.5-44)]
Host: Linux-3.10.0-1160.49.1.el7.x86_64-x86_64-with-centos-7.9.2009-Core (Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64 x86_64)
[ 1/600] p:0 f:0 u:0 e:0 I:0 B:0 t:0 L:0 i:0 W:0 | i386/pc686: dhrystone.exe
<<skipping passes>>
[ 94/600] p:83 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: dl06.exe
Result: failed
Time: 0:00:01.252405 dl06.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/dl06.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: libdl (RTL) 6
] *** BEGIN OF TEST libdl (RTL) 6 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
]
] load: /dl06.rap
] dlopen failed: offset past end of file: offset=8883 size=8883
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08a010001
] executing thread name: UI1
[ 95/600] p:85 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: dl07.exe
<<skipping passes>>
[169/600] p:153 f:1 u:4 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: psx12.exe
Result: failed
Time: 0:00:03.003869 psx12.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psx12.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: PSX 12
] *** BEGIN OF TEST PSX 12 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] Init's ID is 0x0b010001
] Init: pthread_attr_init - SUCCESSFUL
] Init: pthread_create - EINVAL (invalid scheduling policy)
] Init: pthread_attr_init - SUCCESSFUL
] Init: set scheduling parameter attributes for sporadic server
] Init: pthread_create - EINVAL (replenish < budget)
] Init: pthread_create - EINVAL (invalid sched_ss_low_priority)
] Init: pthread_create - SUCCESSFUL
] Sporadic Server: exitting
] [0] H 99ms
] [0] L 199ms
] ../../../testsuites/psxtests/psx12/init.c: 224 ctx->samples[ i ].low / SS_REPL_PERIOD_MS == i + 1
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08b010001
] executing thread name:
[170/600] p:154 f:1 u:4 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: psx13.exe
<<skipping passes>>
[357/600] p:336 f:3 u:6 e:1 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: sp20.exe
Result: test-too-long
Time: 0:01:15.097520 sp20.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp20.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SP 20
] *** BEGIN OF TEST SP 20 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] TA1 - rtems_rate_monotonic_create id = 0x42010001
] TA1 - rtems_rate_monotonic_ident id = 0x42010001
] TA1 - (0x42010001) period 2
] TA2 - rtems_rate_monotonic_create id = 0x42010002
] TA2 - rtems_rate_monotonic_ident id = 0x42010002
] TA2 - (0x42010002) period 2
] TA3 - rtems_rate_monotonic_create id = 0x42010003
] TA3 - rtems_rate_monotonic_ident id = 0x42010003
] TA3 - (0x42010003) period 2
] TA4 - rtems_rate_monotonic_create id = 0x42010004
] TA4 - rtems_rate_monotonic_ident id = 0x42010004
] TA4 - (0x42010004) period 2
] TA5 - rtems_rate_monotonic_create id = 0x42010005
] TA5 - rtems_rate_monotonic_ident id = 0x42010005
] TA5 - (0x42010005) period 100
] TA6 - rtems_rate_monotonic_create id = 0x42010006
] TA6 - rtems_rate_monotonic_ident id = 0x42010006
] TA6 - (0x42010006) period 0
] TA5 - PERIODS CHECK OK (1)
] TA5 - PERIODS CHECK OK (2)
] TA5 - PERIODS CHECK OK (3)
] TA5 - PERIODS CHECK OK (4)
] TA5 - PERIODS CHECK OK (5)
] TA6 - Actual: 10 Expected: 10 - OK
] TA6 - Actual: 20 Expected: 20 - OK
] TA6 - Actual: 30 Expected: 30 - OK
] TA6 - Actual: 40 Expected: 40 - OK
] TA6 - Actual: 50 Expected: 50 - OK
] TA6 - Actual: 60 Expected: 60 - OK
] TA6 - Actual: 70 Expected: 70 - OK
] TA6 - Actual: 80 Expected: 80 - OK
] TA6 - Actual: 90 Expected: 90 - OK
] TA6 - Actual: 100 Expected: 100 - OK
] TA5 - PERIODS CHECK OK (6)
] TA5 - PERIODS CHECK OK (7)
] *** TEST TOO LONG
[358/600] p:337 f:3 u:6 e:1 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: sp2038.exe
<<skipping passes>>
[404/600] p:383 f:3 u:6 e:1 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: sp69.exe
Result: failed
Time: 0:00:02.007141 sp69.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp69.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SP 69
] *** BEGIN OF TEST SP 69 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] rtems_rate_monotonic_get_status - verify values of an inactive period
] rtems_rate_monotonic_get_status - verify values of an active period
] wall time should be ~600000000 is 600261980
] cpu time should be ~100000000 is 99995276
] ../../../testsuites/sptests/sp69/init.c: 99 period_status.executed_since_last_period.tv_nsec >= 100000000
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08a010001
] executing thread name: UI1
[405/600] p:384 f:3 u:6 e:1 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: sp70.exe
<<skipping passes>>
[445/600] p:423 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:0 W:0 | i386/pc686: spfatal09.exe
Result: invalid
Time: 0:00:00.252678 spfatal09.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal09.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[446/600] p:423 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:0 W:0 | i386/pc686: spfatal10.exe
<<skipping passes>>
[448/600] p:424 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:1 W:0 | i386/pc686: spfatal12.exe
Result: invalid
Time: 0:00:00.250958 spfatal12.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal12.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[449/600] p:425 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal14.exe
<<skipping passes>>
[453/600] p:428 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal26.exe
Result: timeout
Time: 0:00:46.559474 spfatal26.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal26.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SPFATAL 26
] *** BEGIN OF TEST SPFATAL 26 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] ../../../testsuites/sptests/spfatal26/init.c: 30 0
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] *** TIMEOUT TIMEOUT
[454/600] p:431 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal28.exe
<<skipping passes>>
[456/600] p:431 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal30.exe
Result: failed
Time: 0:00:01.253110 spfatal30.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal30.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SPFATAL 30
] *** BEGIN OF TEST SPFATAL 30 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] ../../../testsuites/sptests/spfatal30/init.c: 58 0
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08a010001
] executing thread name: UI1
[457/600] p:432 f:4 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal31.exe
<<skipping passes>>
[459/600] p:434 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal33.exe
Result: invalid
Time: 0:00:00.255059 spfatal33.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal33.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[460/600] p:434 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:2 W:0 | i386/pc686: spfatal34.exe
<<skipping passes>>
[470/600] p:444 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:3 W:0 | i386/pc686: spinternalerror01.exe
Result: invalid
Time: 0:00:00.251027 spinternalerror01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spinternalerror01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[471/600] p:444 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:3 W:0 | i386/pc686: spinternalerror02.exe
<<skipping passes>>
[542/600] p:514 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:4 W:0 | i386/pc686: sptimecounter01.exe
Result: invalid
Time: 0:00:00.251010 sptimecounter01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sptimecounter01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[543/600] p:515 f:5 u:6 e:1 I:0 B:3 t:0 L:1 i:5 W:0 | i386/pc686: sptimecounter02.exe
<<skipping passes>>
[599/600] p:569 f:5 u:6 e:1 I:0 B:3 t:1 L:1 i:5 W:0 | i386/pc686: ts-validation-0.exe
Result: timeout
Time: 0:00:46.807434 ts-validation-0.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/validation/ts-validation-0.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: Validation0
] *** BEGIN OF TEST Validation0 ***
] *** TEST VERSION: 7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] A:Validation0
] S:Platform:RTEMS
] S:Compiler:11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] S:Version:7.0.0.671f126a3a8e6ce5da87aa75c7205fb764e95c78
] S:BSP:pc686
] S:BuildLabel:DEFAULT
] S:TargetHash:SHA256:88YxI_BcN0LiTylhghE9z0TpoFSPW688YjCWrEQn2Is=
] S:RTEMS_DEBUG:0
] S:RTEMS_MULTIPROCESSING:0
] S:RTEMS_POSIX_API:1
] S:RTEMS_PROFILING:0
] S:RTEMS_SMP:0
] B:RtemsTaskReqCreateErrors
] E:RtemsTaskReqCreateErrors:N:1460:F:0:D:0.026026
] B:RtemsTaskReqConstructErrors
] E:RtemsTaskReqConstructErrors:N:4625:F:0:D:0.062898
] B:RtemsSignalReqSend
] E:RtemsSignalReqSend:N:659:F:0:D:0.003127
] B:RtemsSignalReqCatch
] E:RtemsSignalReqCatch:N:577:F:0:D:0.000999
] B:RtemsObjectValObject
] E:RtemsObjectValObject:N:1:F:0:D:0.000289
] B:RtemsMessageReqConstructErrors
] E:RtemsMessageReqConstructErrors:N:1731:F:0:D:0.003758
] B:RtemsIntrReqVectorIsEnabled
] F:1:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:221:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:222
] F:4:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:10:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:14:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:20:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:24:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:30:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:34:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:35:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:413:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:40:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:44:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:50:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:54:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:60:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:64:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:69:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:413:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorIsEnabled:N:82:F:36:D:0.013156
] B:RtemsIntrReqVectorEnable
] F:1:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:3:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:8:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:13:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:17:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:18:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:23:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:27:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:28:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:33:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:38:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:43:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:47:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:48:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:53:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:57:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:58:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:63:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:67:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:68:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:72:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:73:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:78:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:82:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:83:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:87:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:88:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:93:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:97:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:98:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:102:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:103:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:107:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:108:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:112:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:113:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:117:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:118:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:122:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:123:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:127:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:128:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:132:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:133:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:137:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:138:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:142:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:143:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:147:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:148:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:152:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:153:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:157:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:158:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:162:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:163:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:167:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:168:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:171:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:172:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:173:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:176:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:177:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:178:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:181:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:182:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:183:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:186:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:187:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:188:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:191:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:192:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:193:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:196:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:197:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:198:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:201:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:202:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:203:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:206:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:207:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:208:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:211:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:212:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:213:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:216:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:217:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:218:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:221:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:222:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:223:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:226:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:227:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:228:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:231:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:232:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:233:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:236:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:237:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:238:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:241:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:242:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:243:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:246:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:247:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:248:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:251:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:252:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:253:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:256:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:257:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:258:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:261:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:262:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:263:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:266:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:267:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:268:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:271:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:272:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:273:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:276:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:277:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:278:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:281:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:282:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:283:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:286:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:287:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:288:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:291:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:292:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:293:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:296:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:297:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:298:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:301:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:302:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:303:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:306:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:307:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:308:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:311:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:312:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:313:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:316:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:317:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:318:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:321:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:322:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:323:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:326:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:327:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:328:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:331:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:332:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:333:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:336:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:337:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:338:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:341:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:342:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:343:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:346:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:347:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:348:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:351:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:352:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:353:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:356:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:357:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:358:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:361:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:362:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:363:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:366:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:367:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:368:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:371:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:372:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:373:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:376:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:377:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:378:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:381:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:382:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:383:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:386:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:387:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:388:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:391:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:392:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:393:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:396:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:397:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:398:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:401:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:402:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:403:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:406:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:407:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:408:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:411:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:412:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:413:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:416:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:417:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:418:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:421:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:422:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:423:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:426:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:427:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:428:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:431:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:432:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:433:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:436:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:437:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:438:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:441:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:442:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:443:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:446:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:447:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:448:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:451:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:452:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:453:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:456:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:457:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:458:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:461:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:462:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:463:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:466:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:467:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:468:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:471:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:472:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:473:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:476:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:477:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:478:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:481:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:482:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:483:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:486:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:487:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:488:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:491:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:492:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:493:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:496:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:497:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:498:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:501:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:502:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:503:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:506:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:507:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:508:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorEnable:N:516:F:306:D:0.110055
] B:RtemsIntrReqVectorDisable
] F:1:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:3:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:8:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:13:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:17:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:18:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:23:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:27:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:28:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:33:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:38:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:43:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:47:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:48:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:53:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:57:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:58:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:63:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:67:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:68:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:72:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:73:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:78:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:82:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:83:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:87:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:88:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:93:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:97:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:98:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:102:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:103:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:107:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:108:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:112:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:113:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:117:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:118:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:122:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:123:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:127:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:128:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:132:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:133:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:137:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:138:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:142:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:143:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:147:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:148:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:152:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:153:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:157:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:158:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:162:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:163:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:167:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:168:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:171:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:172:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:173:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:176:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:177:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:178:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:181:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:182:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:183:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:186:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:187:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:188:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:191:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:192:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:193:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:196:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:197:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:198:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:201:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:202:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:203:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:206:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:207:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:208:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:211:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:212:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:213:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:216:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:217:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:218:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:221:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:222:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:223:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:226:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:227:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:228:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:231:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:232:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:233:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:236:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:237:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:238:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:241:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:242:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:243:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:246:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:247:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:248:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:251:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:252:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:253:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:256:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:257:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:258:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:261:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:262:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:263:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:266:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:267:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:268:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:271:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:272:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:273:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:276:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:277:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:278:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:281:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:282:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:283:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:286:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:287:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:288:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:291:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:292:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:293:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:296:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:297:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:298:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:301:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:302:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:303:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:306:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:307:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:308:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:311:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:312:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:313:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:316:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:317:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:318:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:321:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:322:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:323:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:326:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:327:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:328:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:331:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:332:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:333:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:336:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:337:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:338:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:341:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:342:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:343:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:346:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:347:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:348:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:351:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:352:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:353:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:356:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:357:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:358:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:361:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:362:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:363:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:366:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:367:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:368:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:371:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:372:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:373:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:376:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:377:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:378:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:381:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:382:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:383:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:386:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:387:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:388:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:391:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:392:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:393:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:396:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:397:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:398:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:401:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:402:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:403:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:406:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:407:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:408:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:411:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:412:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:413:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:416:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:417:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:418:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:421:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:422:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:423:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:426:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:427:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:428:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:431:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:432:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:433:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:436:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:437:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:438:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:441:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:442:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:443:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:446:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:447:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:448:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:451:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:452:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:453:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:456:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:457:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:458:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:461:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:462:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:463:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:466:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:467:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:468:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:471:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:472:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:473:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:476:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:477:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:478:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:481:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:482:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:483:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:486:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:487:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:488:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:491:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:492:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:493:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:496:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:497:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:498:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:501:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:502:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:503:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:506:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:507:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:508:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorDisable:N:516:F:306:D:0.106480
] B:RtemsIntrReqSetAffinity
] E:RtemsIntrReqSetAffinity:N:222:F:0:D:0.000761
] B:RtemsIntrReqRaiseOn
] F:1:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:3:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:23:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:33:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:63:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:73:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:78:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:88:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:93:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:103:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:108:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:113:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:118:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:123:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:128:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:133:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:138:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:143:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:148:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:153:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:158:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:163:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:168:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqRaiseOn:N:176:F:68:D:0.025634
] B:RtemsIntrReqRaise
] F:1:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:3:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:23:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:33:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:63:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:73:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:78:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:88:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:93:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:103:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:108:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:113:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:118:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:123:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:128:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:133:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:138:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:143:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:148:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:153:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:158:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:163:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:168:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqRaise:N:172:F:68:D:0.022595
] B:RtemsIntrReqIsPending
] F:1:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:4:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:10:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:19:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:25:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:34:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:40:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:49:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:59:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:65:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:74:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:80:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:89:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:95:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqIsPending:N:116:F:34:D:0.012984
] B:RtemsIntrReqHandlerIterate
] F:0:0:UI1:tc-intr-handler-iterate.c:520:RTEMS_INVALID_ID == RTEMS_SUCCESSFUL
] raw_idt_notify has been called
] *** TIMEOUT TIMEOUT
[600/600] p:570 f:6 u:6 e:1 I:0 B:3 t:1 L:1 i:5 W:0 | i386/pc686: ts-validation-1.exe
Passed: 576
Failed: 6
User Input: 6
Expected Fail: 1
Indeterminate: 0
Benchmark: 3
Timeout: 2
Test too long: 1
Invalid: 5
Wrong Version: 0
Wrong Build: 0
Wrong Tools: 0
Wrong Header: 0
------------------
Total: 600
Failures:
dl06.exe
psx12.exe
sp69.exe
spfatal30.exe
tmcontext01.exe
minimum.exe
User Input:
dl10.exe
fileio.exe
top.exe
monitor.exe
capture.exe
termios.exe
Expected Fail:
psxfenv01.exe
Benchmark:
whetstone.exe
linpack.exe
dhrystone.exe
Timeouts:
ts-validation-0.exe
spfatal26.exe
Test too long:
sp20.exe
Invalid:
sptimecounter01.exe
spinternalerror01.exe
spfatal12.exe
spfatal33.exe
spfatal09.exe
Average test time: 0:00:00.589634
Testing time : 0:05:53.780985
More information about the build
mailing list