[rtems-test] i386/pc686: RTEMS_POSIX_API: Passed:537 Failed:5 Timeout:7 Test-Too-long:0 Invalid:42 Wrong:0
Joel Sherrill
joel at rtems.org
Wed Jan 19 00:14:00 UTC 2022
Testing time : 0:06:28.230254
Average test time: 0:00:00.647050
Host
====
Linux-3.10.0-1160.49.1.el7.x86_64-x86_64-with-centos-7.9.2009-Core (Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64 x86_64)
Configuration
=============
Version: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
Build : RTEMS_POSIX_API
Tools : 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
Summary
=======
Passed: 537
Failed: 5
User Input: 5
Expected Fail: 1
Indeterminate: 0
Benchmark: 3
Timeout: 7
Test too long: 0
Invalid: 42
Wrong Version: 0
Wrong Build: 0
Wrong Tools: 0
Wrong Header: 0
------------------
Total: 600
Failures:
sptimecounter02.exe
psx12.exe
tm26.exe
tmcontext01.exe
minimum.exe
User Input:
dl10.exe
fileio.exe
monitor.exe
capture.exe
termios.exe
Expected Fail:
psxfenv01.exe
Benchmark:
whetstone.exe
linpack.exe
dhrystone.exe
Timeouts:
psxconfstr.exe
psxtmthread04.exe
spscheduler01.exe
sp49.exe
psx01.exe
ts-validation-0.exe
spfatal26.exe
Invalid:
block17.exe
sp2038.exe
fsimfsconfig02.exe
psxtmmutexattr01.exe
psxtmcleanup01.exe
mimfs_fsscandir01.exe
psxtmrwlock07.exe
bspcmdline01.exe
psxtmsleep02.exe
sparsedisk01.exe
nsecs.exe
sptimecounter01.exe
psxfile01.exe
dl06.exe
spinternalerror01.exe
top.exe
psxsignal02.exe
tm07.exe
psxsem01.exe
devnullfatal01.exe
spfatal12.exe
sp56.exe
tm09.exe
psxtmmqrcvblock02.exe
spfatal33.exe
spinternalerror02.exe
psxtmcond06.exe
psxtmrwlock06.exe
psxtmclocknanosleep03.exe
spfatal25.exe
spedfsched02.exe
tmck.exe
spintrcritical21.exe
spfatal30.exe
psxfatal02.exe
psxsignal01.exe
spfatal09.exe
sp20.exe
tmtimer01.exe
spintrcritical20.exe
tm15.exe
spedfsched03.exe
Log
===
RTEMS Testing - Tester, 6.0.not_released
Command Line: /home/joel/rtems-cron-7/tools/7/bin/rtems-test --rtems-tools=/home/joel/rtems-cron-7/tools/7 --rtems-bsp=pc-qemu --log=run-pc-qemu.log --use-gitconfig --mail .
Host: Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64
Python: 2.7.5 (default, Nov 16 2020, 22:23:17) [GCC 4.8.5 20150623 (Red Hat 4.8.5-44)]
Host: Linux-3.10.0-1160.49.1.el7.x86_64-x86_64-with-centos-7.9.2009-Core (Linux devel.oarcorp.com 3.10.0-1160.49.1.el7.x86_64 #1 SMP Tue Nov 30 15:51:32 UTC 2021 x86_64 x86_64)
[ 1/600] p:0 f:0 u:0 e:0 I:0 B:0 t:0 L:0 i:0 W:0 | i386/pc686: dhrystone.exe
<<skipping passes>>
[ 13/600] p:3 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: fsimfsconfig02.exe
Result: invalid
Time: 0:00:00.770455 fsimfsconfig02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/fstests/fsimfsconfig02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 14/600] p:3 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:0 W:0 | i386/pc686: fsimfsconfig03.exe
<<skipping passes>>
[ 48/600] p:36 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:1 W:0 | i386/pc686: mimfs_fsscandir01.exe
Result: invalid
Time: 0:00:00.760489 mimfs_fsscandir01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/fstests/mimfs_fsscandir01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 49/600] p:38 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:2 W:0 | i386/pc686: mimfs_fssymlink.exe
<<skipping passes>>
[ 77/600] p:64 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:2 W:0 | i386/pc686: block17.exe
Result: invalid
Time: 0:00:00.502028 block17.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/block17.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 78/600] p:65 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:3 W:0 | i386/pc686: bspcmdline01.exe
Result: invalid
Time: 0:00:00.524574 bspcmdline01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/bspcmdline01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 79/600] p:65 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:3 W:0 | i386/pc686: capture01.exe
<<skipping passes>>
[ 88/600] p:73 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:4 W:0 | i386/pc686: devnullfatal01.exe
Result: invalid
Time: 0:00:00.769531 devnullfatal01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/devnullfatal01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 89/600] p:73 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:5 W:0 | i386/pc686: dl01.exe
<<skipping passes>>
[ 94/600] p:78 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:5 W:0 | i386/pc686: dl06.exe
Result: invalid
Time: 0:00:00.761246 dl06.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/dl06.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[ 95/600] p:80 f:0 u:0 e:0 I:0 B:3 t:0 L:0 i:5 W:0 | i386/pc686: dl07.exe
<<skipping passes>>
[132/600] p:113 f:0 u:2 e:0 I:0 B:3 t:0 L:0 i:6 W:0 | i386/pc686: sparsedisk01.exe
Result: invalid
Time: 0:00:00.501810 sparsedisk01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/sparsedisk01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[133/600] p:114 f:0 u:2 e:0 I:0 B:3 t:0 L:0 i:6 W:0 | i386/pc686: spi01.exe
<<skipping passes>>
[152/600] p:131 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:7 W:0 | i386/pc686: top.exe
Result: invalid
Time: 0:00:00.503009 top.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/libtests/top.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[153/600] p:131 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: ttest01.exe
<<skipping passes>>
[158/600] p:136 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psx01.exe
Result: timeout
Time: 0:00:45.615328 psx01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psx01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] *** TIMEOUT TIMEOUT
[159/600] p:137 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psx02.exe
<<skipping passes>>
[169/600] p:148 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psx12.exe
Result: failed
Time: 0:00:03.519636 psx12.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psx12.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: PSX 12
] *** BEGIN OF TEST PSX 12 ***
] *** TEST VERSION: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] Init's ID is 0x0b010001
] Init: pthread_attr_init - SUCCESSFUL
] Init: pthread_create - EINVAL (invalid scheduling policy)
] Init: pthread_attr_init - SUCCESSFUL
] Init: set scheduling parameter attributes for sporadic server
] Init: pthread_create - EINVAL (replenish < budget)
] Init: pthread_create - EINVAL (invalid sched_ss_low_priority)
] Init: pthread_create - SUCCESSFUL
] Sporadic Server: exitting
] [0] H 99ms
] [0] L 205ms
] [1] H 287ms
] [1] L 399ms
] ../../../testsuites/psxtests/psx12/init.c: 224 ctx->samples[ i ].low / SS_REPL_PERIOD_MS == i + 1
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08b010001
] executing thread name:
[170/600] p:148 f:0 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psx13.exe
<<skipping passes>>
[195/600] p:172 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psxconfstr.exe
Result: timeout
Time: 0:00:45.329666 psxconfstr.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxconfstr.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] *** TIMEOUT TIMEOUT
[196/600] p:174 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psxdevctl01.exe
<<skipping passes>>
[200/600] p:179 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psxfatal02.exe
Result: invalid
Time: 0:00:00.514768 psxfatal02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxfatal02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[201/600] p:179 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:8 W:0 | i386/pc686: psxfchx01.exe
<<skipping passes>>
[203/600] p:180 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:9 W:0 | i386/pc686: psxfile01.exe
Result: invalid
Time: 0:00:00.765530 psxfile01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxfile01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[204/600] p:181 f:1 u:3 e:0 I:0 B:3 t:0 L:0 i:9 W:0 | i386/pc686: psxfile02.exe
<<skipping passes>>
[243/600] p:216 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:10 W:0 | i386/pc686: psxsem01.exe
Result: invalid
Time: 0:00:00.780698 psxsem01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxsem01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[244/600] p:218 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:10 W:0 | i386/pc686: psxshm01.exe
<<skipping passes>>
[246/600] p:220 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:11 W:0 | i386/pc686: psxsignal01.exe
Result: invalid
Time: 0:00:00.766026 psxsignal01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxsignal01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[247/600] p:220 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:11 W:0 | i386/pc686: psxsignal02.exe
Result: invalid
Time: 0:00:00.775612 psxsignal02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtests/psxsignal02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[248/600] p:220 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:11 W:0 | i386/pc686: psxsignal03.exe
<<skipping passes>>
[272/600] p:243 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:13 W:0 | i386/pc686: psxtmcleanup01.exe
Result: invalid
Time: 0:00:00.511314 psxtmcleanup01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmcleanup01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[273/600] p:243 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:13 W:0 | i386/pc686: psxtmclocknanosleep01.exe
<<skipping passes>>
[275/600] p:244 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:14 W:0 | i386/pc686: psxtmclocknanosleep03.exe
Result: invalid
Time: 0:00:00.509893 psxtmclocknanosleep03.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmclocknanosleep03.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[276/600] p:245 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:14 W:0 | i386/pc686: psxtmcond01.exe
<<skipping passes>>
[281/600] p:249 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:15 W:0 | i386/pc686: psxtmcond06.exe
Result: invalid
Time: 0:00:00.511376 psxtmcond06.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmcond06.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[282/600] p:251 f:1 u:3 e:1 I:0 B:3 t:1 L:0 i:16 W:0 | i386/pc686: psxtmcond07.exe
<<skipping passes>>
[290/600] p:258 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:16 W:0 | i386/pc686: psxtmmqrcvblock02.exe
Result: invalid
Time: 0:00:00.506249 psxtmmqrcvblock02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmmqrcvblock02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[291/600] p:258 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:16 W:0 | i386/pc686: psxtmmutex01.exe
<<skipping passes>>
[298/600] p:263 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:17 W:0 | i386/pc686: psxtmmutexattr01.exe
Result: invalid
Time: 0:00:00.516711 psxtmmutexattr01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmmutexattr01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[299/600] p:265 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:18 W:0 | i386/pc686: psxtmnanosleep01.exe
<<skipping passes>>
[307/600] p:271 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:18 W:0 | i386/pc686: psxtmrwlock06.exe
Result: invalid
Time: 0:00:00.517340 psxtmrwlock06.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmrwlock06.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[308/600] p:272 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:18 W:0 | i386/pc686: psxtmrwlock07.exe
Result: invalid
Time: 0:00:00.515065 psxtmrwlock07.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmrwlock07.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[309/600] p:272 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:19 W:0 | i386/pc686: psxtmsem01.exe
<<skipping passes>>
[315/600] p:279 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:20 W:0 | i386/pc686: psxtmsleep02.exe
Result: invalid
Time: 0:00:00.537524 psxtmsleep02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmsleep02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[316/600] p:279 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:20 W:0 | i386/pc686: psxtmthread01.exe
<<skipping passes>>
[319/600] p:280 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:21 W:0 | i386/pc686: psxtmthread04.exe
Result: timeout
Time: 0:00:45.586941 psxtmthread04.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/psxtmtests/psxtmthread04.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] *** TIMEOUT TIMEOUT
[320/600] p:281 f:1 u:3 e:1 I:0 B:3 t:2 L:0 i:21 W:0 | i386/pc686: psxtmthread05.exe
<<skipping passes>>
[336/600] p:296 f:1 u:4 e:1 I:0 B:3 t:2 L:0 i:21 W:0 | i386/pc686: nsecs.exe
Result: invalid
Time: 0:00:00.511395 nsecs.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/samples/nsecs.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[337/600] p:297 f:1 u:4 e:1 I:0 B:3 t:2 L:0 i:21 W:0 | i386/pc686: paranoia.exe
<<skipping passes>>
[357/600] p:314 f:2 u:5 e:1 I:0 B:3 t:2 L:0 i:22 W:0 | i386/pc686: sp20.exe
Result: invalid
Time: 0:00:00.501360 sp20.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp20.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[358/600] p:314 f:2 u:5 e:1 I:0 B:3 t:2 L:0 i:23 W:0 | i386/pc686: sp2038.exe
Result: invalid
Time: 0:00:00.762701 sp2038.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp2038.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[359/600] p:314 f:2 u:5 e:1 I:0 B:3 t:2 L:0 i:24 W:0 | i386/pc686: sp21.exe
<<skipping passes>>
[385/600] p:339 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:24 W:0 | i386/pc686: sp49.exe
Result: timeout
Time: 0:00:45.347469 sp49.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp49.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] *** TIMEOUT TIMEOUT
[386/600] p:340 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:24 W:0 | i386/pc686: sp50.exe
<<skipping passes>>
[392/600] p:346 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:24 W:0 | i386/pc686: sp56.exe
Result: invalid
Time: 0:00:00.506899 sp56.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sp56.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[393/600] p:346 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:25 W:0 | i386/pc686: sp57.exe
<<skipping passes>>
[431/600] p:385 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:25 W:0 | i386/pc686: spedfsched02.exe
Result: invalid
Time: 0:00:00.511879 spedfsched02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spedfsched02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[432/600] p:385 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:25 W:0 | i386/pc686: spedfsched03.exe
Result: invalid
Time: 0:00:00.513179 spedfsched03.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spedfsched03.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[433/600] p:385 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:27 W:0 | i386/pc686: spedfsched04.exe
<<skipping passes>>
[445/600] p:397 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:27 W:0 | i386/pc686: spfatal09.exe
Result: invalid
Time: 0:00:00.765231 spfatal09.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal09.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[446/600] p:397 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:27 W:0 | i386/pc686: spfatal10.exe
<<skipping passes>>
[448/600] p:399 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:28 W:0 | i386/pc686: spfatal12.exe
Result: invalid
Time: 0:00:00.513306 spfatal12.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal12.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[449/600] p:399 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:28 W:0 | i386/pc686: spfatal14.exe
<<skipping passes>>
[452/600] p:402 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:29 W:0 | i386/pc686: spfatal25.exe
Result: invalid
Time: 0:00:00.533918 spfatal25.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal25.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[453/600] p:402 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:29 W:0 | i386/pc686: spfatal26.exe
Result: timeout
Time: 0:00:47.130780 spfatal26.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal26.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SPFATAL 26
] *** BEGIN OF TEST SPFATAL 26 ***
] *** TEST VERSION: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] ../../../testsuites/sptests/spfatal26/init.c: 30 0
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/s../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] ../../../testsuites/sptests/spfatal26/init.c: 39 source == RTEMS_FATAL_SOURCE_EXCEPTION
] *** TIMEOUT TIMEOUT
[454/600] p:403 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:30 W:0 | i386/pc686: spfatal28.exe
<<skipping passes>>
[456/600] p:404 f:2 u:5 e:1 I:0 B:3 t:3 L:0 i:30 W:0 | i386/pc686: spfatal30.exe
Result: invalid
Time: 0:00:00.523971 spfatal30.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal30.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[457/600] p:404 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:31 W:0 | i386/pc686: spfatal31.exe
<<skipping passes>>
[459/600] p:406 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:31 W:0 | i386/pc686: spfatal33.exe
Result: invalid
Time: 0:00:00.506123 spfatal33.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spfatal33.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[460/600] p:406 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:31 W:0 | i386/pc686: spfatal34.exe
<<skipping passes>>
[470/600] p:415 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:32 W:0 | i386/pc686: spinternalerror01.exe
Result: invalid
Time: 0:00:00.516285 spinternalerror01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spinternalerror01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[471/600] p:416 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:33 W:0 | i386/pc686: spinternalerror02.exe
Result: invalid
Time: 0:00:00.517915 spinternalerror02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spinternalerror02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[472/600] p:416 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:33 W:0 | i386/pc686: spintr_err01.exe
<<skipping passes>>
[488/600] p:431 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:34 W:0 | i386/pc686: spintrcritical20.exe
Result: invalid
Time: 0:00:00.757323 spintrcritical20.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spintrcritical20.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[489/600] p:433 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:35 W:0 | i386/pc686: spintrcritical21.exe
Result: invalid
Time: 0:00:00.784584 spintrcritical21.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spintrcritical21.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[490/600] p:433 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:35 W:0 | i386/pc686: spintrcritical22.exe
<<skipping passes>>
[516/600] p:458 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:36 W:0 | i386/pc686: spscheduler01.exe
Result: timeout
Time: 0:00:45.325380 spscheduler01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/spscheduler01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] *** TIMEOUT TIMEOUT
[517/600] p:458 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:36 W:0 | i386/pc686: spsem01.exe
<<skipping passes>>
[542/600] p:483 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:36 W:0 | i386/pc686: sptimecounter01.exe
Result: invalid
Time: 0:00:00.774916 sptimecounter01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sptimecounter01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[543/600] p:484 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:36 W:0 | i386/pc686: sptimecounter02.exe
Result: failed
Time: 0:00:03.265196 sptimecounter02.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/sptests/sptimecounter02.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: SPTIMECOUNTER 2
] *** BEGIN OF TEST SPTIMECOUNTER 2 ***
] *** TEST VERSION: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] <SPTimecounter01>
] <BinuptimeTest activeWorker="1">
] <Counter worker="1">4854216</Counter>
] <Duration worker="1" unit="sbintime">6588842241</Duration>
] ../../../testsuites/sptests/sptimecounter02/init.c: 138 error * error < SBT_1MS * SBT_1MS
]
] [ RTEMS shutdown ]
] RTEMS version: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] RTEMS tools: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] executing thread ID: 0x08a010001
] executing thread name: UI1
[544/600] p:485 f:2 u:5 e:1 I:0 B:3 t:4 L:0 i:37 W:0 | i386/pc686: sptimecounter03.exe
<<skipping passes>>
[563/600] p:501 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:37 W:0 | i386/pc686: tm07.exe
Result: invalid
Time: 0:00:00.771034 tm07.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/tmtests/tm07.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[564/600] p:503 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:38 W:0 | i386/pc686: tm08.exe
[565/600] p:503 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:38 W:0 | i386/pc686: tm09.exe
Result: invalid
Time: 0:00:00.764151 tm09.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/tmtests/tm09.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[566/600] p:503 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:38 W:0 | i386/pc686: tm10.exe
<<skipping passes>>
[571/600] p:507 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:39 W:0 | i386/pc686: tm15.exe
Result: invalid
Time: 0:00:00.512222 tm15.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/tmtests/tm15.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[572/600] p:508 f:3 u:5 e:1 I:0 B:3 t:5 L:0 i:39 W:0 | i386/pc686: tm16.exe
<<skipping passes>>
[593/600] p:528 f:4 u:5 e:1 I:0 B:3 t:5 L:0 i:40 W:0 | i386/pc686: tmck.exe
Result: invalid
Time: 0:00:00.751899 tmck.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/tmtests/tmck.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[594/600] p:528 f:4 u:5 e:1 I:0 B:3 t:5 L:0 i:40 W:0 | i386/pc686: tmcontext01.exe
<<skipping passes>>
[597/600] p:530 f:4 u:5 e:1 I:0 B:3 t:5 L:0 i:41 W:0 | i386/pc686: tmtimer01.exe
Result: invalid
Time: 0:00:00.525521 tmtimer01.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/tmtests/tmtimer01.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..
] Booting from ROM..
[598/600] p:532 f:4 u:5 e:1 I:0 B:3 t:5 L:0 i:41 W:0 | i386/pc686: ts-performance-0.exe
[599/600] p:532 f:4 u:5 e:1 I:0 B:3 t:5 L:0 i:41 W:0 | i386/pc686: ts-validation-0.exe
Result: timeout
Time: 0:00:48.577578 ts-validation-0.exe
=> exe: qemu-system-i386 -no-reboot -nographic -monitor none -serial stdio -append --console=/dev/com1 -kernel ./b-pc686/i386/pc686/testsuites/validation/ts-validation-0.exe
] c[?7l[2J[0mSeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
]
]
] iPXE (http://ipxe.org) 00:03.0 CA00 PCI2.10 PnP PMM+07F8F130+07EEF130 CA00
] Press Ctrl-B to configure iPXE (PCI 00:03.0)...
]
]
] Booting from ROM..i386: isr=0 irr=1
] i386: isr=0 irr=1
]
]
=> test start: Validation0
] *** BEGIN OF TEST Validation0 ***
] *** TEST VERSION: 7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] *** TEST STATE: EXPECTED_PASS
] *** TEST BUILD: RTEMS_POSIX_API
] *** TEST TOOLS: 11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] A:Validation0
] S:Platform:RTEMS
] S:Compiler:11.0.1 20210409 (RTEMS 7, RSB a553ce1fe632e46356d79891ecd831dc98968a90, Newlib ebe756e)
] S:Version:7.0.0.aa95122c17707d6eaadcbdae71aad33446fcf66c
] S:BSP:pc686
] S:BuildLabel:DEFAULT
] S:TargetHash:SHA256:88YxI_BcN0LiTylhghE9z0TpoFSPW688YjCWrEQn2Is=
] S:RTEMS_DEBUG:0
] S:RTEMS_MULTIPROCESSING:0
] S:RTEMS_POSIX_API:1
] S:RTEMS_PROFILING:0
] S:RTEMS_SMP:0
] B:RtemsTaskReqCreateErrors
] E:RtemsTaskReqCreateErrors:N:1460:F:0:D:0.100819
] B:RtemsTaskReqConstructErrors
] E:RtemsTaskReqConstructErrors:N:4625:F:0:D:0.245482
] B:RtemsSignalReqSend
] E:RtemsSignalReqSend:N:659:F:0:D:0.005555
] B:RtemsSignalReqCatch
] E:RtemsSignalReqCatch:N:577:F:0:D:0.001823
] B:RtemsObjectValObject
] E:RtemsObjectValObject:N:1:F:0:D:0.000486
] B:RtemsMessageReqConstructErrors
] E:RtemsMessageReqConstructErrors:N:1731:F:0:D:0.007064
] B:RtemsIntrReqVectorIsEnabled
] F:1:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:221:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:222
] F:4:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:10:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:14:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:20:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:24:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:30:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:34:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:286:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:35:0:UI1/Valid/Obj/Yes:tc-intr-vector-is-enabled.c:413:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:40:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:44:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:50:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:54:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:60:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:64:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:308:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:69:0:UI1/Valid/Obj/No:tc-intr-vector-is-enabled.c:413:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorIsEnabled:N:82:F:36:D:0.082192
] B:RtemsIntrReqVectorEnable
] F:1:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:3:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:8:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:13:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:17:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:18:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:23:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:27:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:28:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:33:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:38:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:43:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:47:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:48:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:53:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:57:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:58:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:63:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:67:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:68:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:72:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:73:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:78:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:82:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:83:0:UI1/Valid/Yes/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:87:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:88:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:93:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:97:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:98:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:102:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:103:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:107:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:108:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:112:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:113:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:117:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:118:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:122:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:123:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:127:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:128:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:132:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:133:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:137:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:138:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:142:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:143:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:147:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:148:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:152:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:153:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:157:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:158:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:162:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:163:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:167:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:168:0:UI1/Valid/Yes/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:171:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:172:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:173:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:176:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:177:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:178:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:181:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:182:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:183:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:186:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:187:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:188:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:191:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:192:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:193:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:196:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:197:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:198:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:201:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:202:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:203:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:206:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:207:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:208:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:211:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:212:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:213:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:216:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:217:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:218:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:221:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:222:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:223:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:226:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:227:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:228:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:231:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:232:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:233:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:236:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:237:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:238:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:241:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:242:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:243:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:246:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:247:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:248:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:251:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:252:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:253:0:UI1/Valid/Yes/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:256:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:257:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:258:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:261:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:262:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:263:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:266:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:267:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:268:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:271:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:272:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:273:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:276:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:277:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:278:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:281:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:282:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:283:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:286:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:287:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:288:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:291:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:292:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:293:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:296:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:297:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:298:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:301:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:302:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:303:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:306:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:307:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:308:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:311:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:312:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:313:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:316:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:317:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:318:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:321:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:322:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:323:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:326:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:327:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:328:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:331:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:332:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:333:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:336:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:337:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:338:0:UI1/Valid/No/Yes:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:341:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:342:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:343:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:346:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:347:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:348:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:351:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:352:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:353:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:356:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:357:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:358:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:361:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:362:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:363:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:366:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:367:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:368:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:371:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:372:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:373:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:376:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:377:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:378:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:381:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:382:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:383:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:386:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:387:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:388:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:391:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:392:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:393:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:396:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:397:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:398:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:401:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:402:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:403:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:406:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:407:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:408:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:411:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:412:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:413:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:416:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:417:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:418:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:421:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:422:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:423:0:UI1/Valid/No/Maybe:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:426:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:427:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:428:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:431:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:432:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:433:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:436:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:437:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:438:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:441:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:442:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:443:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:446:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:447:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:448:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:451:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:452:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:453:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:456:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:457:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:458:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:461:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:462:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:463:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:466:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:467:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:468:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:471:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:472:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:473:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:476:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:477:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:478:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:481:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:482:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:483:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:486:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:487:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:488:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:491:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:492:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:493:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:496:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:497:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:498:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:501:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:502:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:503:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:506:0:UI1/Valid/No/No:tc-intr-vector-enable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:507:0:UI1/Valid/No/No:tc-intr-vector-enable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:508:0:UI1/Valid/No/No:tc-intr-vector-enable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorEnable:N:516:F:306:D:0.553486
] B:RtemsIntrReqVectorDisable
] F:1:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:2:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:3:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:8:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:12:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:13:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:17:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:18:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:23:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:27:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:28:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:32:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:33:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:38:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:42:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:43:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:47:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:48:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:52:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:53:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:57:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:58:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:63:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:67:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:68:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:72:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:73:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:78:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:82:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:83:0:UI1/Valid/Yes/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:87:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:88:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:93:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:97:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:98:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:102:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:103:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:107:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:108:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:112:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:113:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:117:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:118:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:122:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:123:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:127:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:128:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:132:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:133:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:137:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:138:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:142:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:143:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:147:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:148:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:152:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:153:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:157:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:158:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:162:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:163:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:167:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:168:0:UI1/Valid/Yes/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:171:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:172:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:173:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:176:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:177:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:178:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:181:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:182:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:183:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:186:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:187:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:188:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:191:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:192:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:193:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:196:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:197:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:198:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:201:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:202:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:203:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:206:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:207:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:208:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:211:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:212:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:213:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:216:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:217:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:218:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:221:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:222:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:223:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:226:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:227:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:228:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:231:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:232:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:233:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:236:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:237:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:238:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:241:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:242:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:243:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:246:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:247:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:248:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:251:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:252:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:253:0:UI1/Valid/Yes/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:256:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:257:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:258:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:261:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:262:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:263:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:266:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:267:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:268:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:271:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:272:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:273:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:276:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:277:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:278:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:281:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:282:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:283:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:286:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:287:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:288:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:291:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:292:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:293:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:296:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:297:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:298:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:301:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:302:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:303:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:306:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:307:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:308:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:311:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:312:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:313:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:316:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:317:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:318:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:321:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:322:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:323:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:326:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:327:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:328:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:331:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:332:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:333:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:336:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:337:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:338:0:UI1/Valid/No/Yes:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:341:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:342:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:343:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:346:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:347:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:348:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:351:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:352:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:353:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:356:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:357:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:358:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:361:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:362:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:363:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:366:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:367:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:368:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:371:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:372:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:373:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:376:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:377:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:378:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:381:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:382:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:383:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:386:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:387:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:388:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:391:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:392:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:393:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:396:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:397:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:398:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:401:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:402:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:403:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:406:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:407:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:408:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:411:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:412:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:413:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:416:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:417:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:418:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:421:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:422:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:423:0:UI1/Valid/No/Maybe:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:426:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:427:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:428:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:431:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:432:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:433:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:436:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:437:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:438:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:441:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:442:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:443:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:446:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:447:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:448:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:451:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:452:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:453:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:456:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:457:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:458:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:461:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:462:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:463:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:466:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:467:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:468:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:471:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:472:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:473:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:476:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:477:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:478:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:481:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:482:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:483:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:486:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:487:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:488:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:491:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:492:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:493:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:496:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:497:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:498:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:501:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:502:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:503:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:506:0:UI1/Valid/No/No:tc-intr-vector-disable.c:251:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:507:0:UI1/Valid/No/No:tc-intr-vector-disable.c:254:RTEMS_SUCCESSFUL == RTEMS_UNSATISFIED
] F:508:0:UI1/Valid/No/No:tc-intr-vector-disable.c:258:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqVectorDisable:N:516:F:306:D:0.416567
] B:RtemsIntrReqSetAffinity
] E:RtemsIntrReqSetAffinity:N:222:F:0:D:0.002256
] B:RtemsIntrReqRaiseOn
] F:1:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:3:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:23:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:33:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:63:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:73:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:78:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Online/Yes:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:88:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:93:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:103:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:108:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:113:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:118:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:123:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:128:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:133:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:138:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:143:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:148:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:153:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:158:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:163:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/Online/No:tc-intr-raise-on.c:287:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:168:0:UI1/Valid/Online/No:tc-intr-raise-on.c:294:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqRaiseOn:N:176:F:68:D:0.126429
] B:RtemsIntrReqRaise
] F:1:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:3:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:6:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:8:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:11:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:18:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:21:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:23:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:26:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:33:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:36:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:38:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:41:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:48:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:51:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:58:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:61:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:63:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:66:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:73:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:76:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:78:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:81:0:UI1/Valid/Yes:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Yes:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:88:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:91:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:93:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:96:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:103:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:106:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:108:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:111:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:113:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:116:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:118:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:121:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:123:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:126:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:128:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:131:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:133:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:136:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:138:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:141:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:143:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:146:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:148:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:151:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:153:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:156:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:158:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:161:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:163:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:166:0:UI1/Valid/No:tc-intr-raise.c:259:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:168:0:UI1/Valid/No:tc-intr-raise.c:266:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqRaise:N:172:F:68:D:0.063978
] B:RtemsIntrReqIsPending
] F:1:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:4:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:7:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:10:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:13:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:16:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:19:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:22:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:25:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:28:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:31:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:34:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:37:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:40:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:43:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:46:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:49:0:UI1/Valid/Obj/Yes:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:53:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:56:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:59:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:62:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:65:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:68:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:71:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:74:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:77:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:80:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:83:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:86:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:89:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:92:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:95:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:98:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] F:101:0:UI1/Valid/Obj/No:tc-intr-is-pending.c:231:RTEMS_UNSATISFIED == RTEMS_SUCCESSFUL
] E:RtemsIntrReqIsPending:N:116:F:34:D:0.021744
] B:RtemsIntrReqHandlerIterate
] F:0:0:UI1:tc-intr-handler-iterate.c:520:RTEMS_INVALID_ID == RTEMS_SUCCESSFUL
] raw_idt_notify has been called
] *** TIMEOUT TIMEOUT
[600/600] p:532 f:5 u:5 e:1 I:0 B:3 t:5 L:0 i:42 W:0 | i386/pc686: ts-validation-1.exe
Passed: 537
Failed: 5
User Input: 5
Expected Fail: 1
Indeterminate: 0
Benchmark: 3
Timeout: 7
Test too long: 0
Invalid: 42
Wrong Version: 0
Wrong Build: 0
Wrong Tools: 0
Wrong Header: 0
------------------
Total: 600
Failures:
sptimecounter02.exe
psx12.exe
tm26.exe
tmcontext01.exe
minimum.exe
User Input:
dl10.exe
fileio.exe
monitor.exe
capture.exe
termios.exe
Expected Fail:
psxfenv01.exe
Benchmark:
whetstone.exe
linpack.exe
dhrystone.exe
Timeouts:
psxconfstr.exe
psxtmthread04.exe
spscheduler01.exe
sp49.exe
psx01.exe
ts-validation-0.exe
spfatal26.exe
Invalid:
block17.exe
sp2038.exe
fsimfsconfig02.exe
psxtmmutexattr01.exe
psxtmcleanup01.exe
mimfs_fsscandir01.exe
psxtmrwlock07.exe
bspcmdline01.exe
psxtmsleep02.exe
sparsedisk01.exe
nsecs.exe
sptimecounter01.exe
psxfile01.exe
dl06.exe
spinternalerror01.exe
top.exe
psxsignal02.exe
tm07.exe
psxsem01.exe
devnullfatal01.exe
spfatal12.exe
sp56.exe
tm09.exe
psxtmmqrcvblock02.exe
spfatal33.exe
spinternalerror02.exe
psxtmcond06.exe
psxtmrwlock06.exe
psxtmclocknanosleep03.exe
spfatal25.exe
spedfsched02.exe
tmck.exe
spintrcritical21.exe
spfatal30.exe
psxfatal02.exe
psxsignal01.exe
spfatal09.exe
sp20.exe
tmtimer01.exe
spintrcritical20.exe
tm15.exe
spedfsched03.exe
Average test time: 0:00:00.647050
Testing time : 0:06:28.230254
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