Build CYGWIN_NT-10.0-19045: FAILED devel/spike on x86_64-pc-cygwin (spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1)

[OAR Tester for Windows10 Cygwin]

RTEMS Source Builder - Set Builder, 6 (108b765c96bf)

Host: CYGWIN_NT-10.0-19045-3.4.7-1.x86_64-x86_64-64bit-WindowsPE
       CYGWIN_NT-10.0-19045 VM-Windows10 3.4.7-1.x86_64 2023-06-16 14:04 UTC
       x86_64

Build Time: 0:00:47.453223

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
Build FAILED: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
-rw-rw-r-- root/root       479 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsadd_vx.h
-rw-rw-r-- root/root       187 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsaddu_vi.h
-rw-rw-r-- root/root       137 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsaddu_vv.h
-rw-rw-r-- root/root       138 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsaddu_vx.h
-rw-rw-r-- root/root       120 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsbc_vvm.h
-rw-rw-r-- root/root       120 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsbc_vxm.h
-rw-rw-r-- root/root        71 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vse16_v.h
-rw-rw-r-- root/root        71 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vse32_v.h
-rw-rw-r-- root/root        71 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vse64_v.h
-rw-rw-r-- root/root        68 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vse8_v.h
-rw-rw-r-- root/root       105 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsetivli.h
-rw-rw-r-- root/root        94 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsetvl.h
-rw-rw-r-- root/root       106 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsetvli.h
-rw-rw-r-- root/root        19 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsext_vf2.h
-rw-rw-r-- root/root        19 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsext_vf4.h
-rw-rw-r-- root/root        19 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsext_vf8.h
-rw-rw-r-- root/root       753 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslide1down_vx.h
-rw-rw-r-- root/root       681 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslide1up_vx.h
-rw-rw-r-- root/root       567 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslidedown_vi.h
-rw-rw-r-- root/root       559 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslidedown_vx.h
-rw-rw-r-- root/root       468 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslideup_vi.h
-rw-rw-r-- root/root       456 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vslideup_vx.h
-rw-rw-r-- root/root        86 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsll_vi.h
-rw-rw-r-- root/root        58 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsll_vv.h
-rw-rw-r-- root/root        58 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsll_vx.h
-rw-rw-r-- root/root        48 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsm_v.h
-rw-rw-r-- root/root       704 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsmul_vv.h
-rw-rw-r-- root/root       709 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsmul_vx.h
-rw-rw-r-- root/root        59 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsoxei16_v.h
-rw-rw-r-- root/root        59 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsoxei32_v.h
-rw-rw-r-- root/root        59 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsoxei64_v.h
-rw-rw-r-- root/root        56 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsoxei8_v.h
-rw-rw-r-- root/root        85 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsra_vi.h
-rw-rw-r-- root/root        75 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsra_vv.h
-rw-rw-r-- root/root        74 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsra_vx.h
-rw-rw-r-- root/root        86 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsrl_vi.h
-rw-rw-r-- root/root        76 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsrl_vv.h
-rw-rw-r-- root/root        75 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsrl_vx.h
-rw-rw-r-- root/root        67 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsse16_v.h
-rw-rw-r-- root/root        68 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsse32_v.h
-rw-rw-r-- root/root        68 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsse64_v.h
-rw-rw-r-- root/root        65 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsse8_v.h
-rw-rw-r-- root/root       186 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssra_vi.h
-rw-rw-r-- root/root       175 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssra_vv.h
-rw-rw-r-- root/root       175 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssra_vx.h
-rw-rw-r-- root/root       188 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssrl_vi.h
-rw-rw-r-- root/root       177 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssrl_vv.h
-rw-rw-r-- root/root       177 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssrl_vx.h
-rw-rw-r-- root/root       480 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssub_vv.h
-rw-rw-r-- root/root       481 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssub_vx.h
-rw-rw-r-- root/root       459 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssubu_vv.h
-rw-rw-r-- root/root       459 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vssubu_vx.h
-rw-rw-r-- root/root        43 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsub_vv.h
-rw-rw-r-- root/root        78 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsub_vx.h
-rw-rw-r-- root/root        37 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsuxei16_v.h
-rw-rw-r-- root/root        37 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsuxei32_v.h
-rw-rw-r-- root/root        37 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsuxei64_v.h
-rw-rw-r-- root/root        35 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vsuxei8_v.h
-rw-rw-r-- root/root       117 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwadd_vv.h
-rw-rw-r-- root/root       118 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwadd_vx.h
-rw-rw-r-- root/root        99 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwadd_wv.h
-rw-rw-r-- root/root       101 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwadd_wx.h
-rw-rw-r-- root/root       119 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwaddu_vv.h
-rw-rw-r-- root/root       120 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwaddu_vx.h
-rw-rw-r-- root/root       101 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwaddu_wv.h
-rw-rw-r-- root/root       102 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwaddu_wx.h
-rw-rw-r-- root/root       121 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmacc_vv.h
-rw-rw-r-- root/root       122 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmacc_vx.h
-rw-rw-r-- root/root       138 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmaccsu_vv.h
-rw-rw-r-- root/root       139 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmaccsu_vx.h
-rw-rw-r-- root/root       123 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmaccu_vv.h
-rw-rw-r-- root/root       124 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmaccu_vx.h
-rw-rw-r-- root/root       139 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmaccus_vx.h
-rw-rw-r-- root/root       117 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmul_vv.h
-rw-rw-r-- root/root       118 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmul_vx.h
-rw-rw-r-- root/root       134 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmulsu_vv.h
-rw-rw-r-- root/root       135 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmulsu_vx.h
-rw-rw-r-- root/root       119 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmulu_vv.h
-rw-rw-r-- root/root       119 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwmulu_vx.h
-rw-rw-r-- root/root        79 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwredsum_vs.h
-rw-rw-r-- root/root        80 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwredsumu_vs.h
-rw-rw-r-- root/root       117 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsub_vv.h
-rw-rw-r-- root/root       118 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsub_vx.h
-rw-rw-r-- root/root        99 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsub_wv.h
-rw-rw-r-- root/root       100 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsub_wx.h
-rw-rw-r-- root/root       119 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsubu_vv.h
-rw-rw-r-- root/root       120 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsubu_vx.h
-rw-rw-r-- root/root       101 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsubu_wv.h
-rw-rw-r-- root/root       102 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vwsubu_wx.h
-rw-rw-r-- root/root        45 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vxor_vi.h
-rw-rw-r-- root/root        43 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vxor_vv.h
-rw-rw-r-- root/root        43 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vxor_vx.h
-rw-rw-r-- root/root        20 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vzext_vf2.h
-rw-rw-r-- root/root        20 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vzext_vf4.h
-rw-rw-r-- root/root        20 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/vzext_vf8.h
-rw-rw-r-- root/root       298 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/wfi.h
-rw-rw-r-- root/root        67 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xnor.h
-rw-rw-r-- root/root        21 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xor.h
-rw-rw-r-- root/root        30 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xori.h
-rw-rw-r-- root/root        81 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xperm16.h
-rw-rw-r-- root/root        84 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xperm32.h
-rw-rw-r-- root/root        98 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xperm4.h
-rw-rw-r-- root/root        98 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/xperm8.h
-rw-rw-r-- root/root        16 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/zunpkd810.h
-rw-rw-r-- root/root        16 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/zunpkd820.h
-rw-rw-r-- root/root        16 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/zunpkd830.h
-rw-rw-r-- root/root        16 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/zunpkd831.h
-rw-rw-r-- root/root        16 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/insns/zunpkd832.h
-rw-rw-r-- root/root     17487 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/interactive.cc
-rw-rw-r-- root/root      5238 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/jtag_dtm.cc
-rw-rw-r-- root/root      1331 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/jtag_dtm.h
-rw-rw-r-- root/root       863 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/log_file.h
-rw-rw-r-- root/root      1099 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/memtracer.h
-rw-rw-r-- root/root      2932 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/mmio_plugin.h
-rw-rw-r-- root/root     14353 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/mmu.cc
-rw-rw-r-- root/root     18078 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/mmu.h
-rw-rw-r-- root/root      7422 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/opcodes.h
-rw-rw-r-- root/root       287 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/platform.h
-rw-rw-r-- root/root     39299 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/processor.cc
-rw-rw-r-- root/root     14694 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/processor.h
-rw-rw-r-- root/root      4842 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/remote_bitbang.cc
-rw-rw-r-- root/root       648 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/remote_bitbang.h
-rw-rw-r-- root/root      2770 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/riscv.ac
-rw-rw-r-- root/root     15898 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/riscv.mk.in
-rw-rw-r-- root/root      1162 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/rocc.cc
-rw-rw-r-- root/root      1553 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/rocc.h
-rw-rw-r-- root/root       353 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/rom.cc
-rw-rw-r-- root/root     11331 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/sim.cc
-rw-rw-r-- root/root      6650 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/sim.h
-rw-rw-r-- root/root       652 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/simif.h
-rw-rw-r-- root/root       200 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/tracer.h
-rw-rw-r-- root/root       259 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/trap.cc
-rw-rw-r-- root/root      3714 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/riscv/trap.h
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/
-rw-rw-r-- root/root     49274 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/config.guess
-rw-rw-r-- root/root     34214 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/config.sub
-rwxrwxr-x root/root      4772 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/install.sh
-rwxrwxr-x root/root       736 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/mk-install-dirs.sh
-rwxrwxr-x root/root      4117 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/scripts/vcs-version.sh
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/
-rw-rw-r-- root/root      2892 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_add.c
-rwxrwxr-x root/root      1220 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_classify.c
-rw-rw-r-- root/root      7769 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_div.c
-rw-rw-r-- root/root      2690 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_eq.c
-rw-rw-r-- root/root      2527 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_eq_signaling.c
-rw-rw-r-- root/root      2071 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_isSignalingNaN.c
-rw-rw-r-- root/root      2748 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_le.c
-rw-rw-r-- root/root      2927 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_le_quiet.c
-rw-rw-r-- root/root      2744 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_lt.c
-rw-rw-r-- root/root      2923 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_lt_quiet.c
-rw-rw-r-- root/root      6117 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_mul.c
-rw-rw-r-- root/root      2395 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_mulAdd.c
-rw-rw-r-- root/root      7468 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_rem.c
-rw-rw-r-- root/root      6600 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_roundToInt.c
-rw-rw-r-- root/root      8649 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_sqrt.c
-rw-rw-r-- root/root      2892 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_sub.c
-rw-rw-r-- root/root      3837 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_f16.c
-rw-rw-r-- root/root      3845 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_f32.c
-rw-rw-r-- root/root      3977 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_f64.c
-rw-rw-r-- root/root      3479 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_i32.c
-rw-rw-r-- root/root      3980 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_i32_r_minMag.c
-rw-rw-r-- root/root      4072 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_i64.c
-rw-rw-r-- root/root      4781 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_i64_r_minMag.c
-rw-rw-r-- root/root      3463 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_ui32.c
-rw-rw-r-- root/root      3654 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_ui32_r_minMag.c
-rw-rw-r-- root/root      4079 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_ui64.c
-rw-rw-r-- root/root      4426 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f128_to_ui64_r_minMag.c
-rw-rw-r-- root/root      2607 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_add.c
-rwxrwxr-x root/root      1127 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_classify.c
-rw-rw-r-- root/root      6492 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_div.c
-rw-rw-r-- root/root      2462 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_eq.c
-rw-rw-r-- root/root      2332 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_eq_signaling.c
-rw-rw-r-- root/root      2059 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_isSignalingNaN.c
-rw-rw-r-- root/root      2477 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_le.c
-rw-rw-r-- root/root      2623 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_le_quiet.c
-rw-rw-r-- root/root      2482 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_lt.c
-rw-rw-r-- root/root      2628 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_lt_quiet.c
-rw-rw-r-- root/root      5097 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_mul.c
-rw-rw-r-- root/root      2258 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_mulAdd.c
-rw-rw-r-- root/root      6376 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_rem.c
-rw-rw-r-- root/root      4425 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_roundToInt.c
-rw-rw-r-- root/root      5216 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_sqrt.c
-rw-rw-r-- root/root      2607 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_sub.c
-rw-rw-r-- root/root      3688 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_f128.c
-rw-rw-r-- root/root      3590 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_f32.c
-rw-rw-r-- root/root      3592 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_f64.c
-rw-rw-r-- root/root      2418 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i16.c
-rw-rw-r-- root/root      3402 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i32.c
-rw-rw-r-- root/root      3585 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i32_r_minMag.c
-rw-rw-r-- root/root      3402 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i64.c
-rw-rw-r-- root/root      3585 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i64_r_minMag.c
-rw-rw-r-- root/root      2412 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_i8.c
-rw-rw-r-- root/root      2281 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui16.c
-rw-rw-r-- root/root      3347 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui32.c
-rw-rw-r-- root/root      3562 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui32_r_minMag.c
-rw-rw-r-- root/root      3347 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui64.c
-rw-rw-r-- root/root      3562 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui64_r_minMag.c
-rw-rw-r-- root/root      2277 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f16_to_ui8.c
-rw-rw-r-- root/root      2607 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_add.c
-rwxrwxr-x root/root      1127 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_classify.c
-rw-rw-r-- root/root      6323 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_div.c
-rw-rw-r-- root/root      2455 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_eq.c
-rw-rw-r-- root/root      2325 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_eq_signaling.c
-rw-rw-r-- root/root      2052 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_isSignalingNaN.c
-rw-rw-r-- root/root      2470 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_le.c
-rw-rw-r-- root/root      2616 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_le_quiet.c
-rw-rw-r-- root/root      2475 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_lt.c
-rw-rw-r-- root/root      2621 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_lt_quiet.c
-rw-rw-r-- root/root      5063 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_mul.c
-rw-rw-r-- root/root      2251 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_mulAdd.c
-rw-rw-r-- root/root      6317 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_rem.c
-rw-rw-r-- root/root      4425 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_roundToInt.c
-rw-rw-r-- root/root      4623 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_sqrt.c
-rw-rw-r-- root/root      2607 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_sub.c
-rw-rw-r-- root/root      3690 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_f128.c
-rw-rw-r-- root/root      3460 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_f16.c
-rw-rw-r-- root/root      3594 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_f64.c
-rw-rw-r-- root/root      2418 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_i16.c
-rw-rw-r-- root/root      3394 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_i32.c
-rw-rw-r-- root/root      3638 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_i32_r_minMag.c
-rw-rw-r-- root/root      3787 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_i64.c
-rw-rw-r-- root/root      3780 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_i64_r_minMag.c
-rw-rw-r-- root/root      2280 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_ui16.c
-rw-rw-r-- root/root      3406 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_ui32.c
-rw-rw-r-- root/root      3538 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_ui32_r_minMag.c
-rw-rw-r-- root/root      3794 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_ui64.c
-rw-rw-r-- root/root      3638 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f32_to_ui64_r_minMag.c
-rw-rw-r-- root/root      2699 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_add.c
-rwxrwxr-x root/root      1128 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_classify.c
-rw-rw-r-- root/root      6427 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_div.c
-rw-rw-r-- root/root      2474 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_eq.c
-rw-rw-r-- root/root      2344 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_eq_signaling.c
-rw-rw-r-- root/root      2052 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_isSignalingNaN.c
-rw-rw-r-- root/root      2501 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_le.c
-rw-rw-r-- root/root      2647 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_le_quiet.c
-rw-rw-r-- root/root      2499 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_lt.c
-rw-rw-r-- root/root      2645 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_lt_quiet.c
-rw-rw-r-- root/root      5494 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_mul.c
-rw-rw-r-- root/root      2251 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_mulAdd.c
-rw-rw-r-- root/root      7059 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_rem.c
-rw-rw-r-- root/root      4452 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_roundToInt.c
-rw-rw-r-- root/root      5184 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_sqrt.c
-rw-rw-r-- root/root      2699 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_sub.c
-rw-rw-r-- root/root      3773 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_f128.c
-rw-rw-r-- root/root      3473 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_f16.c
-rw-rw-r-- root/root      3477 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_f32.c
-rw-rw-r-- root/root      3348 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_i32.c
-rw-rw-r-- root/root      3858 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_i32_r_minMag.c
-rw-rw-r-- root/root      3996 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_i64.c
-rw-rw-r-- root/root      4205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_i64_r_minMag.c
-rw-rw-r-- root/root      3360 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_ui32.c
-rw-rw-r-- root/root      3567 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_ui32_r_minMag.c
-rw-rw-r-- root/root      4003 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_ui64.c
-rw-rw-r-- root/root      3721 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/f64_to_ui64_r_minMag.c
-rw-rw-r-- root/root      4517 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/fall_maxmin.c
-rw-rw-r-- root/root     11461 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/fall_reciprocal.c
-rw-rw-r-- root/root      2437 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i32_to_f128.c
-rw-rw-r-- root/root      2726 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i32_to_f16.c
-rw-rw-r-- root/root      2275 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i32_to_f32.c
-rw-rw-r-- root/root      2438 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i32_to_f64.c
-rw-rw-r-- root/root      2686 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i64_to_f128.c
-rw-rw-r-- root/root      2691 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i64_to_f16.c
-rw-rw-r-- root/root      2691 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i64_to_f32.c
-rw-rw-r-- root/root      2297 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/i64_to_f64.c
-rw-rw-r-- root/root     10751 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/internals.h
-rw-rw-r-- root/root      2347 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/platform.h
-rw-rw-r-- root/root      3419 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/primitiveTypes.h
-rw-rw-r-- root/root     51745 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/primitives.h
-rw-rw-r-- root/root      2111 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_add128.c
-rw-rw-r-- root/root      2401 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_add256M.c
-rw-rw-r-- root/root      2514 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addCarryM.c
-rw-rw-r-- root/root      2525 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addComplCarryM.c
-rw-rw-r-- root/root      2492 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addM.c
-rw-rw-r-- root/root      5037 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addMagsF128.c
-rw-rw-r-- root/root      6761 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addMagsF16.c
-rw-rw-r-- root/root      4705 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addMagsF32.c
-rw-rw-r-- root/root      4762 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_addMagsF64.c
-rw-rw-r-- root/root      2614 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_approxRecip32_1.c
-rw-rw-r-- root/root      2921 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_approxRecipSqrt32_1.c
-rw-rw-r-- root/root      2275 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_approxRecipSqrt_1Ks.c
-rw-rw-r-- root/root      2267 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_approxRecip_1Ks.c
-rw-rw-r-- root/root      2455 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_commonNaNToF128UI.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_commonNaNToF16UI.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_commonNaNToF32UI.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_commonNaNToF64UI.c
-rw-rw-r-- root/root      2364 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_compare128M.c
-rw-rw-r-- root/root      2362 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_compare96M.c
-rw-rw-r-- root/root      2233 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_countLeadingZeros16.c
-rw-rw-r-- root/root      2310 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_countLeadingZeros32.c
-rw-rw-r-- root/root      2650 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_countLeadingZeros64.c
-rw-rw-r-- root/root      2770 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_countLeadingZeros8.c
-rw-rw-r-- root/root      2037 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_eq128.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_f128UIToCommonNaN.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_f16UIToCommonNaN.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_f32UIToCommonNaN.c
-rw-rw-r-- root/root       205 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_f64UIToCommonNaN.c
-rw-rw-r-- root/root      2054 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_le128.c
-rw-rw-r-- root/root      2053 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_lt128.c
-rw-rw-r-- root/root      2298 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128By32.c
-rw-rw-r-- root/root      4118 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128MTo256M.c
-rw-rw-r-- root/root      2692 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128To256M.c
-rw-rw-r-- root/root      2204 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64ByShifted32To128.c
-rw-rw-r-- root/root      2416 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64To128.c
-rw-rw-r-- root/root      2506 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64To128M.c
-rw-rw-r-- root/root     13492 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF128.c
-rw-rw-r-- root/root      8247 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF16.c
-rw-rw-r-- root/root      8272 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF32.c
-rw-rw-r-- root/root     18253 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF64.c
-rw-rw-r-- root/root      2352 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_negXM.c
-rw-rw-r-- root/root      3063 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF128.c
-rw-rw-r-- root/root      2382 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF16.c
-rw-rw-r-- root/root      2382 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF32.c
-rw-rw-r-- root/root      2385 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF64.c
-rw-rw-r-- root/root      2579 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF128Sig.c
-rw-rw-r-- root/root      2144 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF16Sig.c
-rw-rw-r-- root/root      2146 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF32Sig.c
-rw-rw-r-- root/root      2147 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF64Sig.c
-rw-rw-r-- root/root      3012 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF128UI.c
-rw-rw-r-- root/root      2604 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF16UI.c
-rw-rw-r-- root/root      2598 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF32UI.c
-rw-rw-r-- root/root      2598 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF64UI.c
-rw-rw-r-- root/root      3169 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_remStepMBy32.c
-rw-rw-r-- root/root      3514 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundMToI64.c
-rw-rw-r-- root/root      3408 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundMToUI64.c
-rw-rw-r-- root/root      3513 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackMToI64.c
-rw-rw-r-- root/root      3407 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackMToUI64.c
-rw-rw-r-- root/root      6709 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF128.c
-rw-rw-r-- root/root      4763 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF16.c
-rw-rw-r-- root/root      4778 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF32.c
-rw-rw-r-- root/root      4880 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF64.c
-rw-rw-r-- root/root      3434 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToI32.c
-rw-rw-r-- root/root      3459 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToI64.c
-rw-rw-r-- root/root      3303 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToUI32.c
-rw-rw-r-- root/root      3348 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToUI64.c
-rw-rw-r-- root/root      3441 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToI32.c
-rw-rw-r-- root/root      3460 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToI64.c
-rw-rw-r-- root/root      3310 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToUI32.c
-rw-rw-r-- root/root      3349 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToUI64.c
-rw-rw-r-- root/root      2562 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam128.c
-rw-rw-r-- root/root      2758 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam128Extra.c
-rw-rw-r-- root/root      4022 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam256M.c
-rw-rw-r-- root/root      2076 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam32.c
-rw-rw-r-- root/root      2076 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam64.c
-rw-rw-r-- root/root      2290 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam64Extra.c
-rw-rw-r-- root/root      2137 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftLeft128.c
-rw-rw-r-- root/root      2183 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftLeft64To96M.c
-rw-rw-r-- root/root      2140 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRight128.c
-rw-rw-r-- root/root      2614 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightExtendM.c
-rw-rw-r-- root/root      2265 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam128.c
-rw-rw-r-- root/root      2295 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam128Extra.c
-rw-rw-r-- root/root      2061 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam64.c
-rw-rw-r-- root/root      2171 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam64Extra.c
-rw-rw-r-- root/root      2543 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightM.c
-rw-rw-r-- root/root      2109 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub128.c
-rw-rw-r-- root/root      2293 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub1XM.c
-rw-rw-r-- root/root      2405 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub256M.c
-rw-rw-r-- root/root      2496 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subM.c
-rw-rw-r-- root/root      4748 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF128.c
-rw-rw-r-- root/root      7061 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF16.c
-rw-rw-r-- root/root      5481 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF32.c
-rw-rw-r-- root/root      5533 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF64.c
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.ac
-rw-rw-r-- root/root     18490 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.h
-rw-rw-r-- root/root      4583 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.mk.in
-rw-rw-r-- root/root      2390 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_raiseFlags.c
-rw-rw-r-- root/root      2253 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_state.c
-rw-rw-r-- root/root      4046 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_types.h
-rw-rw-r-- root/root     21790 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/specialize.h
-rw-rw-r-- root/root      2305 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f128.c
-rw-rw-r-- root/root      2547 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f16.c
-rw-rw-r-- root/root      2202 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f32.c
-rw-rw-r-- root/root      2269 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f64.c
-rw-rw-r-- root/root      2551 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f128.c
-rw-rw-r-- root/root      2521 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f16.c
-rw-rw-r-- root/root      2521 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f32.c
-rw-rw-r-- root/root      2276 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f64.c
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/
-rw-rw-r-- root/root      1983 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike-dasm.cc
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm.ac
-rw-rw-r-- root/root       177 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm.mk.in
lrwxrwxrwx root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm_option_parser.cc -> ../fesvr/option_parser.cc
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/
-rw-rw-r-- root/root      1578 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike-log-parser.cc
-rw-rw-r-- root/root     18870 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike.cc
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike_main.ac
-rw-rw-r-- root/root       224 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike_main.mk.in
-rw-rw-r-- root/root       611 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/termios-xspike.cc
-rw-rw-r-- root/root      2064 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/xspike.cc
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/
-rwxrwxr-x root/root       715 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/ebreak.py
-rw-rw-r-- root/root        76 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/ebreak.s
-rw-rw-r-- root/root      3439 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/testlib.py
+ tar_exit=0
+ cd riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa
+ chmod -R a+rX,g-w,o-w .
shell cmd failed: sh -ex  /home/rtems-tester/rtems-cron-6/rtems-source-builder/bare/build/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1/do-build
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
  See error report: rsb-report-spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1.txt
  Note: In some cases the error appears only in
  the complete build log (see --log option)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 


Output
======

Build Set: devel/spike
Build Set: devel/dtc.bset
config: devel/dtc-1.6.1-1.cfg
package: dtc-1.6.1-x86_64-pc-cygwin-1
building: dtc-1.6.1-x86_64-pc-cygwin-1
sizes: dtc-1.6.1-x86_64-pc-cygwin-1: 4.668MB (installed: 1.470MB)
cleaning: dtc-1.6.1-x86_64-pc-cygwin-1
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-pc-cygwin-1.txt
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-pc-cygwin-1.xml
staging: dtc-1.6.1-x86_64-pc-cygwin-1 -> /home/rtems-tester/rtems-cron-6/rtems-source-builder/bare/build/tmp/sb-197609-staging
cleaning: dtc-1.6.1-x86_64-pc-cygwin-1
Build Set: Time 0:00:43.083251
config: devel/spike-1.1.0.cfg
package: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
download: https://github.com/riscv/riscv-isa-sim/archive/530af85d83781a3dae31a4ace84a573ec255fefa.tar.gz -> sources/spike-530af85d83781a3dae31a4ace84a573ec255fefa.tar.gz
 redirect: https://codeload.github.com/riscv-software-src/riscv-isa-sim/tar.gz/530af85d83781a3dae...<see log>
building: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
Build FAILED
  See error report: rsb-report-spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1.txt
  Note: In some cases the error appears only in
  the complete build log (see --log option)
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-pc-cygwin-1
Mailing report: build at rtems.org

Report
======

==============================================================================
RTEMS Tools Project <users at rtems.org> Thu Jun 13 18:15:31 2024
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
[ remotes removed, contact sender for details ]
 Status:
  Clean
 Head:
  Commit: 108b765c96bfa494824eae0101630aa1bbfbf435
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.6.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.6.1-x86_64-pc-cygwin-1
 Config: devel/dtc-1.6.1-1.cfg
 Summary:
  Device Tree Compiler v1.6.1 for target  on host x86_64-pc-cygwin
 URL:
  https://www.devicetree.org/
 Version:
  1.6.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
       sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
  Patches: 1
    1: https://devel.rtems.org/raw-attachment/ticket/4783/0001-checks.c-Ensure-argument-is-an-integer-v2.patch
       sha256: dd83c10326188732ac26c1fd8dce70b796a7dde204b31c67cf4d04f29ed4dfef
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.6.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.6.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  make PREFIX=/home/rtems-tester/rtems-cron-6/tools/6 WARNINGS=
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.6.1
  make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/rtems-tester/rtems-cron-6/tools/6 WARNINGS= install
  cd ${build_top}
==============================================================================
RTEMS Tools Project <users at rtems.org> Thu Jun 13 18:15:31 2024
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
[ remotes removed, contact sender for details ]
 Status:
  Clean
 Head:
  Commit: 108b765c96bfa494824eae0101630aa1bbfbf435
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.6.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.6.1-x86_64-pc-cygwin-1
 Config: devel/dtc-1.6.1-1.cfg
 Summary:
  Device Tree Compiler v1.6.1 for target  on host x86_64-pc-cygwin
 URL:
  https://www.devicetree.org/
 Version:
  1.6.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
       sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
  Patches: 1
    1: https://devel.rtems.org/raw-attachment/ticket/4783/0001-checks.c-Ensure-argument-is-an-integer-v2.patch
       sha256: dd83c10326188732ac26c1fd8dce70b796a7dde204b31c67cf4d04f29ed4dfef
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.6.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.6.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  make PREFIX=/home/rtems-tester/rtems-cron-6/tools/6 WARNINGS=
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.6.1
  make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/rtems-tester/rtems-cron-6/tools/6 WARNINGS= install
  cd ${build_top}