Build Linux: FAILED devel/spike on x86_64-linux-gnu (spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1)

[OAR Tester for Ubuntu 22.04]

RTEMS Source Builder - Set Builder, 5.not_released

Host: Linux-6.8.0-58-generic-x86_64-with-glibc2.39
       Linux VM-Ubuntu22.rtems.com 6.8.0-58-generic #60-Ubuntu SMP
       PREEMPT_DYNAMIC Fri Mar 14 18:29:48 UTC 2025 x86_64 x86_64

Build Time: 0:00:12.358229

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Build FAILED: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
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-rw-rw-r-- root/root      2053 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_lt128.c
-rw-rw-r-- root/root      2298 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128By32.c
-rw-rw-r-- root/root      4118 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128MTo256M.c
-rw-rw-r-- root/root      2692 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul128To256M.c
-rw-rw-r-- root/root      2204 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64ByShifted32To128.c
-rw-rw-r-- root/root      2416 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64To128.c
-rw-rw-r-- root/root      2506 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mul64To128M.c
-rw-rw-r-- root/root     13492 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF128.c
-rw-rw-r-- root/root      8247 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF16.c
-rw-rw-r-- root/root      8272 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF32.c
-rw-rw-r-- root/root     18253 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_mulAddF64.c
-rw-rw-r-- root/root      2352 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_negXM.c
-rw-rw-r-- root/root      3063 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF128.c
-rw-rw-r-- root/root      2382 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF16.c
-rw-rw-r-- root/root      2382 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF32.c
-rw-rw-r-- root/root      2385 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normRoundPackToF64.c
-rw-rw-r-- root/root      2579 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF128Sig.c
-rw-rw-r-- root/root      2144 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF16Sig.c
-rw-rw-r-- root/root      2146 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF32Sig.c
-rw-rw-r-- root/root      2147 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_normSubnormalF64Sig.c
-rw-rw-r-- root/root      3012 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF128UI.c
-rw-rw-r-- root/root      2604 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF16UI.c
-rw-rw-r-- root/root      2598 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF32UI.c
-rw-rw-r-- root/root      2598 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_propagateNaNF64UI.c
-rw-rw-r-- root/root      3169 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_remStepMBy32.c
-rw-rw-r-- root/root      3514 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundMToI64.c
-rw-rw-r-- root/root      3408 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundMToUI64.c
-rw-rw-r-- root/root      3513 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackMToI64.c
-rw-rw-r-- root/root      3407 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackMToUI64.c
-rw-rw-r-- root/root      6709 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF128.c
-rw-rw-r-- root/root      4763 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF16.c
-rw-rw-r-- root/root      4778 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF32.c
-rw-rw-r-- root/root      4880 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToF64.c
-rw-rw-r-- root/root      3434 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToI32.c
-rw-rw-r-- root/root      3459 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToI64.c
-rw-rw-r-- root/root      3303 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToUI32.c
-rw-rw-r-- root/root      3348 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundPackToUI64.c
-rw-rw-r-- root/root      3441 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToI32.c
-rw-rw-r-- root/root      3460 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToI64.c
-rw-rw-r-- root/root      3310 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToUI32.c
-rw-rw-r-- root/root      3349 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_roundToUI64.c
-rw-rw-r-- root/root      2562 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam128.c
-rw-rw-r-- root/root      2758 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam128Extra.c
-rw-rw-r-- root/root      4022 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam256M.c
-rw-rw-r-- root/root      2076 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam32.c
-rw-rw-r-- root/root      2076 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam64.c
-rw-rw-r-- root/root      2290 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shiftRightJam64Extra.c
-rw-rw-r-- root/root      2137 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftLeft128.c
-rw-rw-r-- root/root      2183 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftLeft64To96M.c
-rw-rw-r-- root/root      2140 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRight128.c
-rw-rw-r-- root/root      2614 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightExtendM.c
-rw-rw-r-- root/root      2265 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam128.c
-rw-rw-r-- root/root      2295 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam128Extra.c
-rw-rw-r-- root/root      2061 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam64.c
-rw-rw-r-- root/root      2171 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightJam64Extra.c
-rw-rw-r-- root/root      2543 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_shortShiftRightM.c
-rw-rw-r-- root/root      2109 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub128.c
-rw-rw-r-- root/root      2293 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub1XM.c
-rw-rw-r-- root/root      2405 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_sub256M.c
-rw-rw-r-- root/root      2496 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subM.c
-rw-rw-r-- root/root      4748 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF128.c
-rw-rw-r-- root/root      7061 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF16.c
-rw-rw-r-- root/root      5481 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF32.c
-rw-rw-r-- root/root      5533 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/s_subMagsF64.c
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.ac
-rw-rw-r-- root/root     18490 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.h
-rw-rw-r-- root/root      4583 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat.mk.in
-rw-rw-r-- root/root      2390 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_raiseFlags.c
-rw-rw-r-- root/root      2253 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_state.c
-rw-rw-r-- root/root      4046 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/softfloat_types.h
-rw-rw-r-- root/root     21790 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/specialize.h
-rw-rw-r-- root/root      2305 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f128.c
-rw-rw-r-- root/root      2547 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f16.c
-rw-rw-r-- root/root      2202 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f32.c
-rw-rw-r-- root/root      2269 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui32_to_f64.c
-rw-rw-r-- root/root      2551 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f128.c
-rw-rw-r-- root/root      2521 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f16.c
-rw-rw-r-- root/root      2521 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f32.c
-rw-rw-r-- root/root      2276 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/softfloat/ui64_to_f64.c
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/
-rw-rw-r-- root/root      1983 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike-dasm.cc
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm.ac
-rw-rw-r-- root/root       177 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm.mk.in
lrwxrwxrwx root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_dasm/spike_dasm_option_parser.cc -> ../fesvr/option_parser.cc
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/
-rw-rw-r-- root/root      1578 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike-log-parser.cc
-rw-rw-r-- root/root     18870 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike.cc
-rw-rw-r-- root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike_main.ac
-rw-rw-r-- root/root       224 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/spike_main.mk.in
-rw-rw-r-- root/root       611 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/termios-xspike.cc
-rw-rw-r-- root/root      2064 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/spike_main/xspike.cc
drwxrwxr-x root/root         0 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/
-rwxrwxr-x root/root       715 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/ebreak.py
-rw-rw-r-- root/root        76 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/ebreak.s
-rw-rw-r-- root/root      3439 2021-12-17 03:11 riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa/tests/testlib.py
+ tar_exit=0
+ cd riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa
+ /bin/chmod -R a+rX,g-w,o-w .
+ cd /home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
+ SB_CXC=no
==> clean %{buildroot}: /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1-1002
+ echo ==> clean %{buildroot}: /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1-1002
+ /bin/rm -rf /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1-1002
+ /bin/mkdir -p /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1-1002
+ echo ==> %build:
==> %build:
+ pwd
+ build_top=/home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
+ cd riscv-isa-sim-530af85d83781a3dae31a4ace84a573ec255fefa
+ ./configure --prefix=/home/tester/rtems-cron-5/tools/5
checking build system type... x86_64-pc-linux-gnu
checking host system type... x86_64-pc-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables... 
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking for g++... g++
checking whether we are using the GNU C++ compiler... yes
checking whether g++ accepts -g... yes
checking for ar... ar
checking for ranlib... ranlib
checking for dtc... /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/sb-1002-staging/bin/dtc
checking how to run the C++ preprocessor... g++ -E
checking for grep that handles long lines and -e... /usr/bin/grep
checking for egrep... /usr/bin/grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking whether byte ordering is bigendian... no
checking for a BSD-compatible install... /usr/bin/install -c
checking for ANSI C header files... (cached) yes
checking for __int128_t... yes
checking whether the linker accepts -Wl,--export-dynamic... yes
checking whether C++ compiler accepts -relocatable-pch... no
configure: configuring default subproject : fesvr
checking for pthread_create in -lpthread... yes
checking for struct statx.stx_ino... yes
checking for struct statx.stx_mnt_id... yes
configure: configuring default subproject : riscv
checking for boostlib >= 1.53 (105300)... yes
checking whether the Boost::ASIO library is available... yes
configure: error: Could not find a version of the Boost::Asio library!
shell cmd failed: /bin/sh -ex  /home/tester/rtems-cron-5/rtems-source-builder/bare/build/spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1/do-build
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
  See error report: rsb-report-spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1.txt
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 


Output
======

Build Set: devel/spike
Build Set: devel/dtc.bset
config: devel/dtc-1.6.1-1.cfg
package: dtc-1.6.1-x86_64-linux-gnu-1
building: dtc-1.6.1-x86_64-linux-gnu-1
sizes: dtc-1.6.1-x86_64-linux-gnu-1: 4.576MB (installed: 1.212MB)
cleaning: dtc-1.6.1-x86_64-linux-gnu-1
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-linux-gnu-1.txt
reporting: devel/dtc-1.6.1-1.cfg -> dtc-1.6.1-x86_64-linux-gnu-1.xml
staging: dtc-1.6.1-x86_64-linux-gnu-1 -> /home/tester/rtems-cron-5/rtems-source-builder/bare/build/tmp/sb-1002-staging
cleaning: dtc-1.6.1-x86_64-linux-gnu-1
Build Set: Time 0:00:04.587101
config: devel/spike-1.1.0.cfg
package: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
download: https://github.com/riscv/riscv-isa-sim/archive/530af85d83781a3dae31a4ace84a573ec255fefa.tar.gz -> sources/spike-530af85d83781a3dae31a4ace84a573ec255fefa.tar.gz
 redirect: https://codeload.github.com/riscv-software-src/riscv-isa-sim/tar.gz/530af85d83781a3dae...<see log>
building: spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
Build FAILED
  See error report: rsb-report-spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1.txt
error: building spike-530af85d83781a3dae31a4ace84a573ec255fefa-x86_64-linux-gnu-1
Mailing report: build at rtems.org

Report
======

==============================================================================
RTEMS Tools Project <users at rtems.org> Sat Apr 19 03:09:31 2025
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
[ remotes removed, contact sender for details ]
 Status:
  Clean
 Head:
  Commit: a3bc31ef82e3e230cac07e3a7d781903d6c59d66
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.6.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.6.1-x86_64-linux-gnu-1
 Config: devel/dtc-1.6.1-1.cfg
 Summary:
  Device Tree Compiler v1.6.1 for target  on host x86_64-linux-gnu
 URL:
  https://www.devicetree.org/
 Version:
  1.6.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
       sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
  Patches: 0
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.6.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.6.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  make PREFIX=/home/tester/rtems-cron-5/tools/5
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.6.1
  make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/tester/rtems-cron-5/tools/5 install
  cd ${build_top}
==============================================================================
RTEMS Tools Project <users at rtems.org> Sat Apr 19 03:09:31 2025
==============================================================================
Report: devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
RTEMS Source Builder Repository Status
 Remotes:
[ remotes removed, contact sender for details ]
 Status:
  Clean
 Head:
  Commit: a3bc31ef82e3e230cac07e3a7d781903d6c59d66
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (1) devel/dtc-1.6.1-1.cfg
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Build Set: (2) devel/dtc-1.6.1-1.cfg
------------------------------------------------------------------------------
Package: dtc-1.6.1-x86_64-linux-gnu-1
 Config: devel/dtc-1.6.1-1.cfg
 Summary:
  Device Tree Compiler v1.6.1 for target  on host x86_64-linux-gnu
 URL:
  https://www.devicetree.org/
 Version:
  1.6.1
 Release:
  1
  Sources: 1
    1: https://www.kernel.org/pub/software/utils/dtc/dtc-1.6.1.tar.gz
       sha256: 38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
  Patches: 0
 Preparation:
  build_top=$(pwd)
  %setup source dtc -q -n dtc-1.6.1
  %setup patch dtc -p1
  cd ${build_top}
 Build:
  build_top=$(pwd)
  cd dtc-1.6.1
  # Build and build flags means force build == host
  # gcc is not ready to be compiled with -std=gnu99
  LDFLAGS="${SB_HOST_LDFLAGS}"
  LIBS="${SB_HOST_LIBS}"
  CC=$(echo "gcc ${SB_CFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CXX=$(echo "g++ ${SB_CXXFLAGS}" | sed -e 's,-std=gnu99 ,,')
  CC_FOR_BUILD=${CC}
  CXX_FOR_BUILD=${CXX}
  export CC CXX CC_FOR_BUILD CXX_FOR_BUILD CFLAGS LDFLAGS LIBS
  make PREFIX=/home/tester/rtems-cron-5/tools/5
  cd ${build_top}
 Install:
  build_top=$(pwd)
  rm -rf $SB_BUILD_ROOT
  cd dtc-1.6.1
  make DESTDIR=$SB_BUILD_ROOT PREFIX=/home/tester/rtems-cron-5/tools/5 install
  cd ${build_top}