"Butter bei de Fische" was: Re: [PATCH v3] score: PR1607: Add and use CPU_SIZEOF_POINTER

[Sebastian Huber]

On 11/09/2012 08:44 AM, Thomas Doerfler wrote:
> Sebastian, Ralf, can you both identify a typical piece of assembly code, that
> might be recoded into a more portable code? We could then consider, which versions
> - meet the portability requirements
> - meet the performance requirements
> - are readable and maintainable
> - interface properly to the C portion of the code

#define CPU_SIZEOF_POINTER X

This will define the size of a pointer for the current ABI.

http://en.wikipedia.org/wiki/Application_binary_interface

The type size affects also the selection of the load/store machine 
instructions.  Please remember bugs like this:

http://www.rtems.org/pipermail/rtems-users/2009-March/005030.html

Just a reminder for all people who think that "ABIs are _completely irrelevant_"

We can use CPU_SIZEOF_POINTER to calculate offsets to structure members.  The 
static assertions make sure that this value and the offsets are consistent with 
the current compiler settings.  Examples:

#define PER_CPU_ISR_NEST_LEVEL \
           PER_CPU_END_STACK + 0
#define PER_CPU_EXECUTING \
           PER_CPU_END_STACK + (1 * CPU_SIZEOF_POINTER)

#define ISR_NEST_LEVEL \
          (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL)

They are later used in assembler code like this:

http://git.rtems.org/rtems/tree/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h

[...]
	/* Increment ISR nest level and thread dispatch disable level */
	lis	SCRATCH_REGISTER_2, ISR_NEST_LEVEL at ha
	lwz	SCRATCH_REGISTER_0, ISR_NEST_LEVEL at l(SCRATCH_REGISTER_2)
	lwz	SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level at sdarel(r13)
	addi	SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1
	addi	SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1
	stw	SCRATCH_REGISTER_0, ISR_NEST_LEVEL at l(SCRATCH_REGISTER_2)
	stw	SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level at sdarel(r13)
[...]

The ARMv7-M port uses inline assembler only:

http://git.rtems.org/rtems/tree/cpukit/score/cpu/arm/armv7m-context-switch.c

This works, because the GCC ARM supports the __attribute__((naked)).  One 
drawback is, that this will work only with GCC.

-- 
Sebastian Huber, embedded brains GmbH

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