[PATCH 3/4] powerpc: Add CPU_Exception_frame
Sebastian Huber
sebastian.huber at embedded-brains.de
Mon Nov 26 17:17:04 UTC 2012
The powerpc port uses now a unified CPU_Exception_frame. This resulted
in a CPU_Exception_frame layout change for the MPC5XX.
---
c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h | 118 +++++++-------------
.../new-exceptions/bspsupport/ppc_exc_initialize.c | 53 +++++++++
.../powerpc/new-exceptions/bspsupport/vectors.h | 47 +--------
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 46 ++++++++
4 files changed, 139 insertions(+), 125 deletions(-)
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
index 3ff610e..78e3ab2 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
@@ -34,42 +34,42 @@
#define SRR0_FRAME_OFFSET 8
#define SRR1_FRAME_OFFSET 12
#define EXCEPTION_NUMBER_OFFSET 16
-#define GPR0_OFFSET 20
-#define GPR1_OFFSET 24
-#define GPR2_OFFSET 28
-#define GPR3_OFFSET 32
-#define GPR4_OFFSET 36
-#define GPR5_OFFSET 40
-#define GPR6_OFFSET 44
-#define GPR7_OFFSET 48
-#define GPR8_OFFSET 52
-#define GPR9_OFFSET 56
-#define GPR10_OFFSET 60
-#define GPR11_OFFSET 64
-#define GPR12_OFFSET 68
-#define GPR13_OFFSET 72
-#define GPR14_OFFSET 76
-#define GPR15_OFFSET 80
-#define GPR16_OFFSET 84
-#define GPR17_OFFSET 88
-#define GPR18_OFFSET 92
-#define GPR19_OFFSET 96
-#define GPR20_OFFSET 100
-#define GPR21_OFFSET 104
-#define GPR22_OFFSET 108
-#define GPR23_OFFSET 112
-#define GPR24_OFFSET 116
-#define GPR25_OFFSET 120
-#define GPR26_OFFSET 124
-#define GPR27_OFFSET 128
-#define GPR28_OFFSET 132
-#define GPR29_OFFSET 136
-#define GPR30_OFFSET 140
-#define GPR31_OFFSET 144
-#define EXC_CR_OFFSET 148
-#define EXC_CTR_OFFSET 152
-#define EXC_XER_OFFSET 156
-#define EXC_LR_OFFSET 160
+#define EXC_CR_OFFSET 20
+#define EXC_CTR_OFFSET 24
+#define EXC_XER_OFFSET 28
+#define EXC_LR_OFFSET 32
+#define GPR0_OFFSET 36
+#define GPR1_OFFSET 40
+#define GPR2_OFFSET 44
+#define GPR3_OFFSET 48
+#define GPR4_OFFSET 52
+#define GPR5_OFFSET 56
+#define GPR6_OFFSET 60
+#define GPR7_OFFSET 64
+#define GPR8_OFFSET 68
+#define GPR9_OFFSET 72
+#define GPR10_OFFSET 76
+#define GPR11_OFFSET 80
+#define GPR12_OFFSET 84
+#define GPR13_OFFSET 88
+#define GPR14_OFFSET 92
+#define GPR15_OFFSET 96
+#define GPR16_OFFSET 100
+#define GPR17_OFFSET 104
+#define GPR18_OFFSET 108
+#define GPR19_OFFSET 112
+#define GPR20_OFFSET 116
+#define GPR21_OFFSET 120
+#define GPR22_OFFSET 124
+#define GPR23_OFFSET 128
+#define GPR24_OFFSET 132
+#define GPR25_OFFSET 136
+#define GPR26_OFFSET 140
+#define GPR27_OFFSET 144
+#define GPR28_OFFSET 148
+#define GPR29_OFFSET 152
+#define GPR30_OFFSET 156
+#define GPR31_OFFSET 160
/*
* maintain the EABI requested 8 bytes aligment
* As SVR4 ABI requires 16, make it 16 (as some
@@ -78,6 +78,9 @@
#define EXCEPTION_FRAME_END 176
#ifndef ASM
+
+#include <rtems.h>
+
/*
* default raw exception handlers
*/
@@ -86,49 +89,6 @@ extern void default_exception_vector_code_prolog();
extern int default_exception_vector_code_prolog_size;
extern void initialize_exceptions();
-typedef struct {
- unsigned EXC_SRR0;
- unsigned EXC_SRR1;
- unsigned _EXC_number;
- unsigned GPR0;
- unsigned GPR1;
- unsigned GPR2;
- unsigned GPR3;
- unsigned GPR4;
- unsigned GPR5;
- unsigned GPR6;
- unsigned GPR7;
- unsigned GPR8;
- unsigned GPR9;
- unsigned GPR10;
- unsigned GPR11;
- unsigned GPR12;
- unsigned GPR13;
- unsigned GPR14;
- unsigned GPR15;
- unsigned GPR16;
- unsigned GPR17;
- unsigned GPR18;
- unsigned GPR19;
- unsigned GPR20;
- unsigned GPR21;
- unsigned GPR22;
- unsigned GPR23;
- unsigned GPR24;
- unsigned GPR25;
- unsigned GPR26;
- unsigned GPR27;
- unsigned GPR28;
- unsigned GPR29;
- unsigned GPR30;
- unsigned GPR31;
- unsigned EXC_CR;
- unsigned EXC_CTR;
- unsigned EXC_XER;
- unsigned EXC_LR;
-}CPU_Exception_frame;
-
-
typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr);
/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
index c56003e..35c8e69 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
@@ -27,6 +27,59 @@
#include <bsp/vectors.h>
#include <bsp/bootcard.h>
+#define PPC_EXC_ASSERT_OFFSET(field, off) \
+ RTEMS_STATIC_ASSERT( \
+ offsetof(CPU_Exception_frame, field) + 8 == off, \
+ CPU_Exception_frame_offset_ ## field \
+ )
+
+#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
+ PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
+
+PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
+PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
+PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
+#ifdef __SPE__
+ PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
+ PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
+#endif
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
+
uint32_t ppc_exc_cache_wb_check = 1;
#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
index 8d44d69..9925845 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
@@ -246,51 +246,7 @@ extern "C" {
* @{
*/
-typedef struct {
- unsigned EXC_SRR0;
- unsigned EXC_SRR1;
- unsigned _EXC_number;
- unsigned EXC_CR;
- unsigned EXC_CTR;
- unsigned EXC_XER;
- unsigned EXC_LR;
- #ifdef __SPE__
- uint32_t EXC_SPEFSCR;
- uint64_t EXC_ACC;
- #endif
- PPC_GPR_TYPE GPR0;
- PPC_GPR_TYPE GPR1;
- PPC_GPR_TYPE GPR2;
- PPC_GPR_TYPE GPR3;
- PPC_GPR_TYPE GPR4;
- PPC_GPR_TYPE GPR5;
- PPC_GPR_TYPE GPR6;
- PPC_GPR_TYPE GPR7;
- PPC_GPR_TYPE GPR8;
- PPC_GPR_TYPE GPR9;
- PPC_GPR_TYPE GPR10;
- PPC_GPR_TYPE GPR11;
- PPC_GPR_TYPE GPR12;
- PPC_GPR_TYPE GPR13;
- PPC_GPR_TYPE GPR14;
- PPC_GPR_TYPE GPR15;
- PPC_GPR_TYPE GPR16;
- PPC_GPR_TYPE GPR17;
- PPC_GPR_TYPE GPR18;
- PPC_GPR_TYPE GPR19;
- PPC_GPR_TYPE GPR20;
- PPC_GPR_TYPE GPR21;
- PPC_GPR_TYPE GPR22;
- PPC_GPR_TYPE GPR23;
- PPC_GPR_TYPE GPR24;
- PPC_GPR_TYPE GPR25;
- PPC_GPR_TYPE GPR26;
- PPC_GPR_TYPE GPR27;
- PPC_GPR_TYPE GPR28;
- PPC_GPR_TYPE GPR29;
- PPC_GPR_TYPE GPR30;
- PPC_GPR_TYPE GPR31;
-} BSP_Exception_frame;
+typedef CPU_Exception_frame BSP_Exception_frame;
/** @} */
@@ -539,7 +495,6 @@ int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum);
/*
* Compatibility with pc386
*/
-typedef BSP_Exception_frame CPU_Exception_frame;
typedef exception_handler_t cpuExcHandlerType;
#endif /* ASM */
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index 31b4e7c..290f0db 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -990,6 +990,52 @@ void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
+typedef struct {
+ uint32_t EXC_SRR0;
+ uint32_t EXC_SRR1;
+ uint32_t _EXC_number;
+ uint32_t EXC_CR;
+ uint32_t EXC_CTR;
+ uint32_t EXC_XER;
+ uint32_t EXC_LR;
+ #ifdef __SPE__
+ uint32_t EXC_SPEFSCR;
+ uint64_t EXC_ACC;
+ #endif
+ PPC_GPR_TYPE GPR0;
+ PPC_GPR_TYPE GPR1;
+ PPC_GPR_TYPE GPR2;
+ PPC_GPR_TYPE GPR3;
+ PPC_GPR_TYPE GPR4;
+ PPC_GPR_TYPE GPR5;
+ PPC_GPR_TYPE GPR6;
+ PPC_GPR_TYPE GPR7;
+ PPC_GPR_TYPE GPR8;
+ PPC_GPR_TYPE GPR9;
+ PPC_GPR_TYPE GPR10;
+ PPC_GPR_TYPE GPR11;
+ PPC_GPR_TYPE GPR12;
+ PPC_GPR_TYPE GPR13;
+ PPC_GPR_TYPE GPR14;
+ PPC_GPR_TYPE GPR15;
+ PPC_GPR_TYPE GPR16;
+ PPC_GPR_TYPE GPR17;
+ PPC_GPR_TYPE GPR18;
+ PPC_GPR_TYPE GPR19;
+ PPC_GPR_TYPE GPR20;
+ PPC_GPR_TYPE GPR21;
+ PPC_GPR_TYPE GPR22;
+ PPC_GPR_TYPE GPR23;
+ PPC_GPR_TYPE GPR24;
+ PPC_GPR_TYPE GPR25;
+ PPC_GPR_TYPE GPR26;
+ PPC_GPR_TYPE GPR27;
+ PPC_GPR_TYPE GPR28;
+ PPC_GPR_TYPE GPR29;
+ PPC_GPR_TYPE GPR30;
+ PPC_GPR_TYPE GPR31;
+} CPU_Exception_frame;
+
/*
* _CPU_Initialize_altivec()
*
--
1.7.7
More information about the devel
mailing list