[PATCH 15/15] Provide ChangeLog and README files
Ric Claus
claus at slac.stanford.edu
Tue Nov 27 03:26:53 UTC 2012
---
c/src/lib/libbsp/powerpc/virtex4/ChangeLog | 14 +++++
c/src/lib/libbsp/powerpc/virtex4/README | 86 ++++++++++++++++++++++++++++
c/src/lib/libbsp/powerpc/virtex5/ChangeLog | 15 +++++
c/src/lib/libbsp/powerpc/virtex5/README | 86 ++++++++++++++++++++++++++++
4 files changed, 201 insertions(+), 0 deletions(-)
create mode 100644 c/src/lib/libbsp/powerpc/virtex4/ChangeLog
create mode 100644 c/src/lib/libbsp/powerpc/virtex4/README
create mode 100644 c/src/lib/libbsp/powerpc/virtex5/ChangeLog
create mode 100644 c/src/lib/libbsp/powerpc/virtex5/README
diff --git a/c/src/lib/libbsp/powerpc/virtex4/ChangeLog b/c/src/lib/libbsp/powerpc/virtex4/ChangeLog
new file mode 100644
index 0000000..97e3ee2
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/virtex4/ChangeLog
@@ -0,0 +1,14 @@
+2012-10-18 Sergio Maldonado <smaldona at slac.stanford.edu>
+
+ * Changelog, Makefile.am, libc:
+ Added libc/memcpy.c, optimized memcpy to replace libc memcpy.
+ Added libc/fastcopy.S, optimized block copy.
+
+2012-05-25 Ric Claus <claus at slac.stanford.edu>
+
+ * Changelog, Makefile.am, mmu, bspstart.c, linkcmds, start.S:
+ Added mmu, based vector table at 0x100, fixed bugs.
+
+2011-03-04 Ric Claus <claus at slac.stanford.edu>
+
+ * ChangeLog, virtex4.cfg: added files.
diff --git a/c/src/lib/libbsp/powerpc/virtex4/README b/c/src/lib/libbsp/powerpc/virtex4/README
new file mode 100644
index 0000000..68a0c24
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/virtex4/README
@@ -0,0 +1,86 @@
+# Adapted from virtex BSP
+
+BSP NAME: virtex4
+BOARD: N/A
+BUS: N/A
+CPU FAMILY: ppc
+CPU: PowerPC 405D5
+COPROCESSORS: N/A
+MODE: 32 bit mode
+
+DEBUG MONITOR:
+
+PERIPHERALS
+===========
+TIMERS: 405 internal
+SERIAL PORTS: none
+REAL-TIME CLOCK: none
+DMA: Xilinx virtex internal
+VIDEO: none
+SCSI: none
+NETWORKING: none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER: PPC Decrementer
+IOSUPP DRIVER: N/A
+SHMSUPP: N/A
+TIMER DRIVER: N/A
+TTY DRIVER: N/A
+
+STDIO
+=====
+PORT: N/A
+ELECTRICAL: N/A
+BAUD: N/A
+BITS PER CHARACTER: N/A
+PARITY: N/A
+STOP BITS: N/A
+
+Notes
+=====
+
+Board description
+-----------------
+clock rate: 350 MHz
+ROM: N/A
+RAM: 128MByte DRAM
+
+Virtex only supports single processor operations.
+
+Porting
+-------
+This board support package is written for a naked Virtex 4/PPC FPGA
+system. The rough features of such a board are described above.
+The BSP itself makes no assumptions on what is loaded in the FPGA,
+other than that the CPU has access to some memory, either on-board
+or external, from which code can be run.
+
+This BSP has been constructed so that an application of both firmware
+and software can be layered on top of it by supplying implementations
+for the various 'weak' symbols. These symbols are prefaced with the
+term 'app_'. Applications can thus be built outside of the RTEMS
+directory tree by linking with the appropriate libraries.
+
+The linkcmds file describes the memory layout. Included in this
+definition is a section of memory named MsgArea. Output sent to
+stdout is recorded in this area and can be dumped using the JTAG
+interface, for example.
+
+For adapting this BSP to other boards, the following files should be
+modified:
+
+- c/src/lib/libbsp/powerpc/virtex4/startup/linkcmds
+ for the memory layout required
+
+- c/src/lib/libbsp/powerpc/virtex4/startup/bspstart.c
+ Here you can select the clock source for the timers and the
+ serial interface (system clock or external clock pin), the
+ clock rates, etc.
+
+- c/src/lib/libbsp/powerpc/virtex4/include/bsp.h
+ some BSP-related constants
+
+- c/src/lib/libbsp/powerpc/virtex4/*
+ well, they should be generic, so there _should_ be no reason
+ to mess around there (but who knows...)
diff --git a/c/src/lib/libbsp/powerpc/virtex5/ChangeLog b/c/src/lib/libbsp/powerpc/virtex5/ChangeLog
new file mode 100644
index 0000000..8b106a2
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/virtex5/ChangeLog
@@ -0,0 +1,15 @@
+2012-10-18 Sergio Maldonado <smaldona at slac.stanford.edu>
+
+ * Changelog, Makefile.am, libc:
+ Added libc/memcpy.c, optimized memcpy to replace libc memcpy.
+ Added libc/fastcopy.S, optimized block copy.
+ Enabled GDCBT and GICBT ccr0 bits in start.S.
+
+2012-05-25 Ric Claus <claus at slac.stanford.edu>
+
+ * Changelog, Makefile.am, mmu, bspstart.c, linkcmds, start.S:
+ Added mmu, based vector table at 0x100, fixed bugs.
+
+2011-03-04 Ric Claus <claus at slac.stanford.edu>
+
+ * ChangeLog, virtex5.cfg: added files.
diff --git a/c/src/lib/libbsp/powerpc/virtex5/README b/c/src/lib/libbsp/powerpc/virtex5/README
new file mode 100644
index 0000000..a68bd23
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/virtex5/README
@@ -0,0 +1,86 @@
+# Adapted from virtex BSP
+
+BSP NAME: virtex5
+BOARD: N/A
+BUS: N/A
+CPU FAMILY: ppc
+CPU: PowerPC 440x5
+COPROCESSORS: N/A
+MODE: 32 bit mode
+
+DEBUG MONITOR:
+
+PERIPHERALS
+===========
+TIMERS: 440 internal
+SERIAL PORTS: none
+REAL-TIME CLOCK: none
+DMA: Xilinx virtex internal
+VIDEO: none
+SCSI: none
+NETWORKING: none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER: PPC Decrementer
+IOSUPP DRIVER: N/A
+SHMSUPP: N/A
+TIMER DRIVER: N/A
+TTY DRIVER: N/A
+
+STDIO
+=====
+PORT: N/A
+ELECTRICAL: N/A
+BAUD: N/A
+BITS PER CHARACTER: N/A
+PARITY: N/A
+STOP BITS: N/A
+
+Notes
+=====
+
+Board description
+-----------------
+clock rate: 465 MHz
+ROM: N/A
+RAM: 4GByte DRAM
+
+Virtex only supports single processor operations.
+
+Porting
+-------
+This board support package is written for a naked Virtex 5/PPC FPGA
+system. The rough features of such a board are described above.
+The BSP itself makes no assumptions on what is loaded in the FPGA,
+other than that the CPU has access to some memory, either on-board
+or external, from which code can be run.
+
+This BSP has been constructed so that an application of both firmware
+and software can be layered on top of it by supplying implementations
+for the various 'weak' symbols. These symbols are prefaced with the
+term 'app_'. Applications can thus be built outside of the RTEMS
+directory tree by linking with the appropriate libraries.
+
+The linkcmds file describes the memory layout. Included in this
+definition is a section of memory named MsgArea. Output sent to
+stdout is recorded in this area and can be dumped using the JTAG
+interface, for example.
+
+For adapting this BSP to other boards, the following files should be
+modified:
+
+- c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
+ for the memory layout required
+
+- c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
+ Here you can select the clock source for the timers and the
+ serial interface (system clock or external clock pin), the
+ clock rates, etc.
+
+- c/src/lib/libbsp/powerpc/virtex5/include/bsp.h
+ some BSP-related constants
+
+- c/src/lib/libbsp/powerpc/virtex5/*
+ well, they should be generic, so there _should_ be no reason
+ to mess around there (but who knows...)
--
1.7.1
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