[PATCH 04/12] score: Per-CPU thread dispatch disable level
Sebastian Huber
sebastian.huber at embedded-brains.de
Mon Aug 5 14:08:11 UTC 2013
Use a per-CPU thread dispatch disable level. This is a major
performance improvement for SMP. On non-SMP configurations this may
simplifiy the interrupt entry/exit code.
As a side-effect this fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
---
cpukit/score/Makefile.am | 1 -
cpukit/score/include/rtems/score/isr.h | 22 ----
cpukit/score/include/rtems/score/percpu.h | 21 ++++-
cpukit/score/include/rtems/score/threaddispatch.h | 25 +++--
.../score/src/assertthreaddispatchingrepressed.c | 11 ++-
cpukit/score/src/isrsmp.c | 76 --------------
cpukit/score/src/percpuasm.c | 6 +
cpukit/score/src/schedulersimplesmp.c | 10 ++
cpukit/score/src/threaddispatch.c | 107 +++++++++-----------
cpukit/score/src/threaddispatchdisablelevel.c | 39 +++++---
cpukit/score/src/threadhandler.c | 90 +++++++++++++---
cpukit/score/src/threadloadenv.c | 14 +++-
cpukit/score/src/threadstartmultitasking.c | 9 +-
13 files changed, 227 insertions(+), 204 deletions(-)
delete mode 100644 cpukit/score/src/isrsmp.c
diff --git a/cpukit/score/Makefile.am b/cpukit/score/Makefile.am
index 173f151..4f9164c 100644
--- a/cpukit/score/Makefile.am
+++ b/cpukit/score/Makefile.am
@@ -118,7 +118,6 @@ libscore_a_SOURCES += src/mpci.c src/objectmp.c src/threadmp.c
endif
if HAS_SMP
-libscore_a_SOURCES += src/isrsmp.c
libscore_a_SOURCES += src/schedulersimplesmp.c
libscore_a_SOURCES += src/smp.c
endif
diff --git a/cpukit/score/include/rtems/score/isr.h b/cpukit/score/include/rtems/score/isr.h
index 8d57db2..4d4a5f3 100644
--- a/cpukit/score/include/rtems/score/isr.h
+++ b/cpukit/score/include/rtems/score/isr.h
@@ -96,28 +96,6 @@ SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
*/
void _ISR_Handler_initialization ( void );
-#if defined( RTEMS_SMP )
-/**
- * @brief Enter SMP interrupt code.
- *
- * This method is used to enter the SMP interrupt section.
- *
- * @retval This method returns the isr level.
- */
-int _ISR_SMP_Enter(void);
-
-/**
- * @brief Exit SMP interrupt code.
- *
- * This method is used to exit the SMP interrupt.
- *
- * @retval This method returns 0 on a simple return and returns 1 on a
- * dispatching return.
- */
-int _ISR_SMP_Exit(void);
-
-#endif /* defined( RTEMS_SMP ) */
-
/**
* @brief Install interrupt handler vector.
*
diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h
index 7a4c70e..0ba4bbe 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -166,6 +166,12 @@ typedef struct {
*/
uint32_t isr_nest_level;
+ /**
+ * @brief The thread dispatch critical section nesting counter which is used
+ * to prevent context switches at inopportune moments.
+ */
+ volatile uint32_t thread_dispatch_disable_level;
+
/** This is set to true when this CPU needs to run the dispatcher. */
volatile bool dispatch_necessary;
@@ -267,9 +273,14 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
#if defined( RTEMS_SMP )
static inline Per_CPU_Control *_Per_CPU_Get( void )
{
- _Assert_Thread_dispatching_repressed();
+ Per_CPU_Control *per_cpu =
+ &_Per_CPU_Information[ _SMP_Get_current_processor() ].per_cpu;
- return &_Per_CPU_Information[ _SMP_Get_current_processor() ].per_cpu;
+ _Assert(
+ per_cpu->thread_dispatch_disable_level != 0 || _ISR_Get_level() != 0
+ );
+
+ return per_cpu;
}
#else
#define _Per_CPU_Get() ( &_Per_CPU_Information[ 0 ].per_cpu )
@@ -325,6 +336,8 @@ void _Per_CPU_Wait_for_state(
* On a non SMP system, the _SMP_Get_current_processor() is defined to 0.
* Thus when built for non-SMP, there should be no performance penalty.
*/
+#define _Thread_Dispatch_disable_level \
+ _Per_CPU_Get()->thread_dispatch_disable_level
#define _Thread_Heir \
_Per_CPU_Get()->heir
#define _Thread_Executing \
@@ -373,8 +386,10 @@ void _Per_CPU_Wait_for_state(
*/
#define PER_CPU_ISR_NEST_LEVEL \
PER_CPU_END_STACK
-#define PER_CPU_DISPATCH_NEEDED \
+#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \
PER_CPU_ISR_NEST_LEVEL + 4
+#define PER_CPU_DISPATCH_NEEDED \
+ PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL + 4
#define ISR_NEST_LEVEL \
(SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL)
diff --git a/cpukit/score/include/rtems/score/threaddispatch.h b/cpukit/score/include/rtems/score/threaddispatch.h
index 7e7afb9..13f9475 100644
--- a/cpukit/score/include/rtems/score/threaddispatch.h
+++ b/cpukit/score/include/rtems/score/threaddispatch.h
@@ -14,7 +14,7 @@
#ifndef _RTEMS_SCORE_THREADDISPATCH_H
#define _RTEMS_SCORE_THREADDISPATCH_H
-#include <rtems/score/cpu.h>
+#include <rtems/score/percpu.h>
#include <rtems/score/smplock.h>
#ifdef __cplusplus
@@ -40,13 +40,6 @@ extern "C" {
*/
/**
- * The following declares the dispatch critical section nesting
- * counter which is used to prevent context switches at inopportune
- * moments.
- */
-SCORE_EXTERN volatile uint32_t _Thread_Dispatch_disable_level;
-
-/**
* @brief Indicates if the executing thread is inside a thread dispatch
* critical section.
*
@@ -56,7 +49,21 @@ SCORE_EXTERN volatile uint32_t _Thread_Dispatch_disable_level;
*/
RTEMS_INLINE_ROUTINE bool _Thread_Dispatch_is_enabled(void)
{
- return _Thread_Dispatch_disable_level == 0;
+ bool enabled;
+
+#if defined(RTEMS_SMP)
+ ISR_Level level;
+
+ _ISR_Disable( level );
+#endif
+
+ enabled = _Thread_Dispatch_disable_level == 0;
+
+#if defined(RTEMS_SMP)
+ _ISR_Enable( level );
+#endif
+
+ return enabled;
}
#if defined(RTEMS_SMP)
diff --git a/cpukit/score/src/assertthreaddispatchingrepressed.c b/cpukit/score/src/assertthreaddispatchingrepressed.c
index 44907f6..0d586f8 100644
--- a/cpukit/score/src/assertthreaddispatchingrepressed.c
+++ b/cpukit/score/src/assertthreaddispatchingrepressed.c
@@ -23,6 +23,15 @@
#if defined( RTEMS_DEBUG )
void _Assert_Thread_dispatching_repressed( void )
{
- _Assert( !_Thread_Dispatch_is_enabled() || _ISR_Get_level() != 0 );
+ bool dispatch_is_disabled;
+ ISR_Level level;
+ Per_CPU_Control *per_cpu;
+
+ _ISR_Disable( level );
+ per_cpu = _Per_CPU_Get_by_index( _SMP_Get_current_processor() );
+ dispatch_is_disabled = per_cpu->thread_dispatch_disable_level != 0;
+ _ISR_Enable( level );
+
+ _Assert( dispatch_is_disabled || _ISR_Get_level() != 0 );
}
#endif
diff --git a/cpukit/score/src/isrsmp.c b/cpukit/score/src/isrsmp.c
deleted file mode 100644
index 2f292b0..0000000
--- a/cpukit/score/src/isrsmp.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * @file
- *
- * @brief Initialize, Disable, Enable, Flash, Enter, Exit ISR Implementation
- * @ingroup ScoreISR
- */
-
-/*
- * COPYRIGHT (c) 1989-2011.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- */
-
-#if HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/thread.h>
-#include <rtems/score/threaddispatch.h>
-#include <rtems/score/smp.h>
-
-int _ISR_SMP_Enter(void)
-{
- uint32_t isr_nest_level;
- ISR_Level level;
-
- /* FIXME: Where is the corresponding _ISR_Enable()? */
- _ISR_Disable( level );
-
- isr_nest_level = _ISR_Nest_level++;
-
- _Thread_Disable_dispatch();
-
- return isr_nest_level;
-}
-
-int _ISR_SMP_Exit(void)
-{
- ISR_Level level;
- int retval;
-
- retval = 0;
-
- _ISR_Disable( level );
-
- _ISR_Nest_level--;
-
- if ( _ISR_Nest_level == 0 ) {
- if ( _Thread_Dispatch_necessary ) {
- if ( _Thread_Dispatch_get_disable_level() == 1 ) {
- retval = 1;
- }
- }
- }
-
- /*
- * SPARC has special support to avoid some nasty recursive type behaviour.
- * When dispatching in a thread and we want to return to it then it needs
- * to finish.
- */
- #if defined(__sparc__)
- if ( _CPU_ISR_Dispatch_disable )
- retval = 0;
- #endif
-
- _ISR_Enable( level );
-
- _Thread_Dispatch_decrement_disable_level();
-
- return retval;
-}
diff --git a/cpukit/score/src/percpuasm.c b/cpukit/score/src/percpuasm.c
index 968bc48..ecb4357 100644
--- a/cpukit/score/src/percpuasm.c
+++ b/cpukit/score/src/percpuasm.c
@@ -51,6 +51,12 @@ RTEMS_STATIC_ASSERT(
);
RTEMS_STATIC_ASSERT(
+ offsetof(Per_CPU_Control, thread_dispatch_disable_level)
+ == PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL,
+ PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL
+);
+
+RTEMS_STATIC_ASSERT(
offsetof(Per_CPU_Control, dispatch_necessary) == PER_CPU_DISPATCH_NEEDED,
PER_CPU_DISPATCH_NEEDED
);
diff --git a/cpukit/score/src/schedulersimplesmp.c b/cpukit/score/src/schedulersimplesmp.c
index aeef215..db08b96 100644
--- a/cpukit/score/src/schedulersimplesmp.c
+++ b/cpukit/score/src/schedulersimplesmp.c
@@ -50,6 +50,8 @@ static void _Scheduler_simple_smp_Allocate_processor(
scheduled->is_scheduled = true;
victim->is_scheduled = false;
+ _Per_CPU_Acquire( cpu_of_scheduled );
+
if ( scheduled->is_executing ) {
heir = cpu_of_scheduled->heir;
cpu_of_scheduled->heir = scheduled;
@@ -57,10 +59,18 @@ static void _Scheduler_simple_smp_Allocate_processor(
heir = scheduled;
}
+ _Per_CPU_Release( cpu_of_scheduled );
+
if ( heir != victim ) {
const Per_CPU_Control *cpu_of_executing = _Per_CPU_Get();
heir->cpu = cpu_of_victim;
+
+ /*
+ * FIXME: Here we need atomic store operations with a relaxed memory order.
+ * The _CPU_SMP_Send_interrupt() will ensure that the change can be
+ * observed consistently.
+ */
cpu_of_victim->heir = heir;
cpu_of_victim->dispatch_necessary = true;
diff --git a/cpukit/score/src/threaddispatch.c b/cpukit/score/src/threaddispatch.c
index c659f9f..3b5fb42 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -20,6 +20,7 @@
#include <rtems/score/threaddispatch.h>
#include <rtems/score/apiext.h>
+#include <rtems/score/assert.h>
#include <rtems/score/isr.h>
#include <rtems/score/threadimpl.h>
#include <rtems/score/todimpl.h>
@@ -28,60 +29,47 @@
void _Thread_Dispatch( void )
{
+ Per_CPU_Control *per_cpu;
Thread_Control *executing;
Thread_Control *heir;
ISR_Level level;
- #if defined(RTEMS_SMP)
- /*
- * WARNING: The SMP sequence has severe defects regarding the real-time
- * performance.
- *
- * Consider the following scenario. We have three tasks L (lowest
- * priority), M (middle priority), and H (highest priority). Now let a
- * thread dispatch from M to L happen. An interrupt occurs in
- * _Thread_Dispatch() here:
- *
- * void _Thread_Dispatch( void )
- * {
- * [...]
- *
- * post_switch:
- *
- * _ISR_Enable( level );
- *
- * <-- INTERRUPT
- * <-- AFTER INTERRUPT
- *
- * _Thread_Unnest_dispatch();
- *
- * _API_extensions_Run_post_switch();
- * }
- *
- * The interrupt event makes task H ready. The interrupt code will see
- * _Thread_Dispatch_disable_level > 0 and thus doesn't perform a
- * _Thread_Dispatch(). Now we return to position "AFTER INTERRUPT". This
- * means task L executes now although task H is ready! Task H will execute
- * once someone calls _Thread_Dispatch().
- */
- _Thread_Disable_dispatch();
- #else
- _Thread_Dispatch_set_disable_level( 1 );
- #endif
+#if defined( RTEMS_SMP )
+ _ISR_Disable( level );
+#endif
+
+ per_cpu = _Per_CPU_Get();
+ _Assert( per_cpu->thread_dispatch_disable_level == 0 );
+ per_cpu->thread_dispatch_disable_level = 1;
+
+#if defined( RTEMS_SMP )
+ _ISR_Enable( level );
+#endif
/*
* Now determine if we need to perform a dispatch on the current CPU.
*/
- executing = _Thread_Executing;
- _ISR_Disable( level );
- while ( _Thread_Dispatch_necessary == true ) {
- heir = _Thread_Heir;
- #if defined(RTEMS_SMP)
- executing->is_executing = false;
- heir->is_executing = true;
- #endif
- _Thread_Dispatch_necessary = false;
- _Thread_Executing = heir;
+ executing = per_cpu->executing;
+ _Per_CPU_ISR_disable_and_acquire( per_cpu, level );
+#if defined( RTEMS_SMP )
+ /*
+ * On SMP the complete context switch must be atomic with respect to one
+ * processor. The scheduler must obtain the per-CPU lock to check if a
+ * thread is executing and to update the heir. This ensures that a thread
+ * cannot execute on more than one processor at a time. See also
+ * _Thread_Handler() since _Context_switch() may branch to this function.
+ */
+ if ( per_cpu->dispatch_necessary ) {
+#else
+ while ( per_cpu->dispatch_necessary ) {
+#endif
+ heir = per_cpu->heir;
+ per_cpu->dispatch_necessary = false;
+ per_cpu->executing = heir;
+#if defined( RTEMS_SMP )
+ executing->is_executing = false;
+ heir->is_executing = true;
+#endif
/*
* When the heir and executing are the same, then we are being
@@ -102,16 +90,18 @@ void _Thread_Dispatch( void )
if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE )
heir->cpu_time_budget = _Thread_Ticks_per_timeslice;
+#if !defined( RTEMS_SMP )
_ISR_Enable( level );
+#endif
#ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__
_Thread_Update_cpu_time_used(
executing,
- &_Thread_Time_of_last_context_switch
+ &per_cpu->time_of_last_context_switch
);
#else
{
- _TOD_Get_uptime( &_Thread_Time_of_last_context_switch );
+ _TOD_Get_uptime( &per_cpu->time_of_last_context_switch );
heir->cpu_time_used++;
}
#endif
@@ -165,21 +155,24 @@ void _Thread_Dispatch( void )
#endif
#endif
- executing = _Thread_Executing;
+ /*
+ * We have to obtain these values again after the context switch since the
+ * heir thread may have migrated from another processor. Values from the
+ * stack or non-volatile registers reflect the old execution environment.
+ */
+ per_cpu = _Per_CPU_Get();
+ executing = per_cpu->executing;
+#if !defined( RTEMS_SMP )
_ISR_Disable( level );
+#endif
}
post_switch:
- #ifndef RTEMS_SMP
- _Thread_Dispatch_set_disable_level( 0 );
- #endif
-
- _ISR_Enable( level );
+ _Assert( per_cpu->thread_dispatch_disable_level == 1 );
+ per_cpu->thread_dispatch_disable_level = 0;
- #ifdef RTEMS_SMP
- _Thread_Unnest_dispatch();
- #endif
+ _Per_CPU_Release_and_ISR_enable( per_cpu, level );
_API_extensions_Run_post_switch( executing );
}
diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c
index 816959a..3eda8e6 100644
--- a/cpukit/score/src/threaddispatchdisablelevel.c
+++ b/cpukit/score/src/threaddispatchdisablelevel.c
@@ -30,10 +30,10 @@ void _Thread_Dispatch_initialization( void )
Thread_Dispatch_disable_level_lock_control *level_lock =
&_Thread_Dispatch_disable_level_lock;
- _Thread_Dispatch_disable_level = 0;
+ _Thread_Dispatch_disable_level = 1;
+
_SMP_lock_Initialize( &level_lock->lock );
level_lock->owner_cpu = NO_OWNER_CPU;
- _Thread_Dispatch_set_disable_level( 1 );
}
uint32_t _Thread_Dispatch_get_disable_level(void)
@@ -46,8 +46,9 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
Thread_Dispatch_disable_level_lock_control *level_lock =
&_Thread_Dispatch_disable_level_lock;
ISR_Level isr_level;
- uint32_t self_cpu;
+ uint32_t self_cpu_index;
uint32_t disable_level;
+ Per_CPU_Control *self_cpu;
_ISR_Disable( isr_level );
@@ -55,19 +56,20 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
* We must obtain the processor ID after interrupts are disabled since a
* non-optimizing compiler may store the value on the stack and read it back.
*/
- self_cpu = _SMP_Get_current_processor();
+ self_cpu_index = _SMP_Get_current_processor();
- if ( level_lock->owner_cpu != self_cpu ) {
+ if ( level_lock->owner_cpu != self_cpu_index ) {
_SMP_lock_Acquire( &level_lock->lock );
- level_lock->owner_cpu = self_cpu;
+ level_lock->owner_cpu = self_cpu_index;
level_lock->nest_level = 1;
} else {
++level_lock->nest_level;
}
- disable_level = _Thread_Dispatch_disable_level;
+ self_cpu = _Per_CPU_Get_by_index( self_cpu_index );
+ disable_level = self_cpu->thread_dispatch_disable_level;
++disable_level;
- _Thread_Dispatch_disable_level = disable_level;
+ self_cpu->thread_dispatch_disable_level = disable_level;
_ISR_Enable( isr_level );
@@ -80,12 +82,14 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
&_Thread_Dispatch_disable_level_lock;
ISR_Level isr_level;
uint32_t disable_level;
+ Per_CPU_Control *self_cpu;
_ISR_Disable( isr_level );
- disable_level = _Thread_Dispatch_disable_level;
+ self_cpu = _Per_CPU_Get();
+ disable_level = self_cpu->thread_dispatch_disable_level;
--disable_level;
- _Thread_Dispatch_disable_level = disable_level;
+ self_cpu->thread_dispatch_disable_level = disable_level;
--level_lock->nest_level;
if ( level_lock->nest_level == 0 ) {
@@ -110,13 +114,20 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
uint32_t _Thread_Dispatch_set_disable_level(uint32_t value)
{
+ ISR_Level isr_level;
+ uint32_t disable_level;
+
+ _ISR_Disable( isr_level );
+ disable_level = _Thread_Dispatch_disable_level;
+ _ISR_Enable( isr_level );
+
/*
* If we need the dispatch level to go higher
* call increment method the desired number of times.
*/
- while ( value > _Thread_Dispatch_disable_level ) {
- _Thread_Dispatch_increment_disable_level();
+ while ( value > disable_level ) {
+ disable_level = _Thread_Dispatch_increment_disable_level();
}
/*
@@ -124,8 +135,8 @@ uint32_t _Thread_Dispatch_set_disable_level(uint32_t value)
* call increment method the desired number of times.
*/
- while ( value < _Thread_Dispatch_disable_level ) {
- _Thread_Dispatch_decrement_disable_level();
+ while ( value < disable_level ) {
+ disable_level = _Thread_Dispatch_decrement_disable_level();
}
return value;
diff --git a/cpukit/score/src/threadhandler.c b/cpukit/score/src/threadhandler.c
index 1fde4cd..80941f8 100644
--- a/cpukit/score/src/threadhandler.c
+++ b/cpukit/score/src/threadhandler.c
@@ -19,6 +19,7 @@
#endif
#include <rtems/score/threadimpl.h>
+#include <rtems/score/assert.h>
#include <rtems/score/interr.h>
#include <rtems/score/isrlevel.h>
#include <rtems/score/userextimpl.h>
@@ -46,12 +47,46 @@
#define EXECUTE_GLOBAL_CONSTRUCTORS
#endif
+#if defined(EXECUTE_GLOBAL_CONSTRUCTORS)
+ static bool _Thread_Handler_is_constructor_execution_required(
+ Thread_Control *executing
+ )
+ {
+ static bool doneConstructors;
+ bool doCons = false;
+
+ #if defined(RTEMS_SMP)
+ static SMP_lock_Control constructor_lock = SMP_LOCK_INITIALIZER;
+
+ if ( !doneConstructors ) {
+ _SMP_lock_Acquire( &constructor_lock );
+ #endif
+
+ #if defined(RTEMS_MULTIPROCESSING)
+ doCons = !doneConstructors
+ && _Objects_Get_API( executing->Object.id ) != OBJECTS_INTERNAL_API;
+ if (doCons)
+ doneConstructors = true;
+ #else
+ (void) executing;
+ doCons = !doneConstructors;
+ doneConstructors = true;
+ #endif
+
+ #if defined(RTEMS_SMP)
+ _SMP_lock_Release( &constructor_lock );
+ }
+ #endif
+
+ return doCons;
+ }
+#endif
+
void _Thread_Handler( void )
{
ISR_Level level;
Thread_Control *executing;
#if defined(EXECUTE_GLOBAL_CONSTRUCTORS)
- static bool doneConstructors;
bool doCons;
#endif
@@ -64,23 +99,17 @@ void _Thread_Handler( void )
*/
_Context_Initialization_at_thread_begin();
- /*
- * have to put level into a register for those cpu's that use
- * inline asm here
- */
- level = executing->Start.isr_level;
- _ISR_Set_level(level);
+ #if !defined(RTEMS_SMP)
+ /*
+ * have to put level into a register for those cpu's that use
+ * inline asm here
+ */
+ level = executing->Start.isr_level;
+ _ISR_Set_level( level );
+ #endif
#if defined(EXECUTE_GLOBAL_CONSTRUCTORS)
- #if defined(RTEMS_MULTIPROCESSING)
- doCons = !doneConstructors
- && _Objects_Get_API( executing->Object.id ) != OBJECTS_INTERNAL_API;
- if (doCons)
- doneConstructors = true;
- #else
- doCons = !doneConstructors;
- doneConstructors = true;
- #endif
+ doCons = _Thread_Handler_is_constructor_execution_required( executing );
#endif
/*
@@ -109,7 +138,34 @@ void _Thread_Handler( void )
/*
* At this point, the dispatch disable level BETTER be 1.
*/
- _Thread_Enable_dispatch();
+ #if defined(RTEMS_SMP)
+ {
+ /*
+ * On SMP we enter _Thread_Handler() with interrupts disabled and
+ * _Thread_Dispatch() obtained the per-CPU lock for us. We have to
+ * release it here and set the desired interrupt level of the thread.
+ */
+ Per_CPU_Control *per_cpu = _Per_CPU_Get();
+
+ _Assert( per_cpu->thread_dispatch_disable_level == 1 );
+ _Assert( _ISR_Get_level() != 0 );
+
+ per_cpu->thread_dispatch_disable_level = 0;
+
+ _Per_CPU_Release( per_cpu );
+
+ level = executing->Start.isr_level;
+ _ISR_Set_level( level);
+
+ /*
+ * The thread dispatch level changed from one to zero. Make sure we lose
+ * no thread dispatch necessary update.
+ */
+ _Thread_Dispatch();
+ }
+ #else
+ _Thread_Enable_dispatch();
+ #endif
#if defined(EXECUTE_GLOBAL_CONSTRUCTORS)
/*
diff --git a/cpukit/score/src/threadloadenv.c b/cpukit/score/src/threadloadenv.c
index ad33626..eb3cc63 100644
--- a/cpukit/score/src/threadloadenv.c
+++ b/cpukit/score/src/threadloadenv.c
@@ -26,6 +26,7 @@ void _Thread_Load_environment(
)
{
bool is_fp;
+ uint32_t isr_level;
#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE )
if ( the_thread->Start.fp_context ) {
@@ -40,11 +41,22 @@ void _Thread_Load_environment(
the_thread->budget_algorithm = the_thread->Start.budget_algorithm;
the_thread->budget_callout = the_thread->Start.budget_callout;
+#if defined( RTEMS_SMP )
+ /*
+ * On SMP we have to start the threads with interrupts disabled, see also
+ * _Thread_Handler() and _Thread_Dispatch(). In _Thread_Handler() the
+ * _ISR_Set_level() is used to set the desired interrupt state of the thread.
+ */
+ isr_level = CPU_MODES_INTERRUPT_MASK;
+#else
+ isr_level = the_thread->Start.isr_level;
+#endif
+
_Context_Initialize(
&the_thread->Registers,
the_thread->Start.Initial_stack.area,
the_thread->Start.Initial_stack.size,
- the_thread->Start.isr_level,
+ isr_level,
_Thread_Handler,
is_fp
);
diff --git a/cpukit/score/src/threadstartmultitasking.c b/cpukit/score/src/threadstartmultitasking.c
index b6ff073..74ed40c 100644
--- a/cpukit/score/src/threadstartmultitasking.c
+++ b/cpukit/score/src/threadstartmultitasking.c
@@ -28,6 +28,8 @@ void _Thread_Start_multitasking( Context_Control *context )
#if defined(RTEMS_SMP)
_Per_CPU_Change_state( self_cpu, PER_CPU_STATE_UP );
+ _Per_CPU_Acquire( self_cpu );
+
self_cpu->executing->is_executing = false;
heir->is_executing = true;
#endif
@@ -70,10 +72,11 @@ void _Thread_Start_multitasking( Context_Control *context )
#if defined(RTEMS_SMP)
} else {
/*
- * Threads begin execution in the _Thread_Handler() function. This function
- * will call _Thread_Enable_dispatch().
+ * Threads begin execution in the _Thread_Handler() function. This
+ * function will set the thread dispatch disable level to zero and calls
+ * _Per_CPU_Release().
*/
- _Thread_Disable_dispatch();
+ self_cpu->thread_dispatch_disable_level = 1;
_CPU_Context_switch_to_first_task_smp( &heir->Registers );
}
--
1.7.7
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