[PATCH 2/2] bsp/lm4f120: new BSP to support TI LM4F120 XL LaunchPad board

[Eugeniy Meshcheryakov]

Hi,

>    uint32_t rcc = syscon->rcc;
> +  uint32_t rcc2 = syscon->rcc2;
>  
>    rcc = (rcc & ~SYSCONRCC_USESYSDIV) | SYSCONRCC_BYPASS;
> +  rcc2 |= SYSCONRCC2_BYPASS2;
> +
> +  syscon->rcc = rcc;
> +  syscon->rcc2 = rcc2;
> +
> +  rcc &= SYSCONRCC_MOSCDIS;
>    syscon->rcc = rcc;
> +  lm3s69xx_syscon_delay_3x_clocks(524288);
>  
>    rcc = (rcc & ~(SYSCONRCC_PWRDN | SYSCONRCC_XTAL_MSK | SYSCONRCC_OSCSRC_MSK))
>        | SYSCONRCC_XTAL(LM3S69XX_XTAL_CONFIG) | SYSCONRCC_OSCSRC_MOSC;
> -  syscon->rcc = rcc;
> +  rcc2 = (rcc2 & ~(SYSCONRCC2_PWRDN2 | SYSCONRCC2_USERCC2 | SYSCONRCC2_OSCSRC2_MSK))
> +      | SYSCONRCC2_USERCC2 | SYSCONRCC2_OSCSRC2_MSK;
           ^^^^^^^^^^^^^^^^^^
Here is one more problem. You are using RCC2 unconditionally, so I think
you do not need most of the code that uses RCC here. I think the problem
you saw was because you were overwritting settings made to RCC by
writing to RCC2 or other way around. Please use only RCC2 here, except
maybe for bits that are in RCC but not in RCC2. But then be careful with
cached values of registers. Especially you do not have to set clock
divisor value in RCC.

> +
> +  syscon->misc &= (SYSCONMISC_PLLLMIS);
>  
> -  rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_SYSDIV(sysdiv_val / 2 - 1)
> -      | SYSCONRCC_USESYSDIV;
>    syscon->rcc = rcc;
> +  syscon->rcc2 = rcc2;
> +  lm3s69xx_syscon_delay_3x_clocks(16);
> +
> +  if (sysdiv_val % 2 == 0) {
> +      rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_SYSDIV(sysdiv_val / 2 - 1)
> +          | SYSCONRCC_USESYSDIV;
> +      rcc2 = (rcc2 & ~SYSCONRCC2_SYSDIV2_MSK) | SYSCONRCC2_SYSDIV2(sysdiv_val / 2 - 1);
> +
> +      rcc2 &= ~(SYSCONRCC2_DIV400);
> +  }
> +  else {
> +      // need to use RCC2 and DIV400
> +      rcc = (rcc & ~SYSCONRCC_SYSDIV_MSK) | SYSCONRCC_USESYSDIV;
> +      rcc2 = (rcc2 & ~SYSCONRCC2_SYSDIV2EXT_MSK) | SYSCONRCC2_SYSDIV2EXT(sysdiv_val - 1)
> +          | SYSCONRCC2_USERCC2 | SYSCONRCC2_DIV400;
> +  }
> +  syscon->rcc = rcc;
> +  syscon->rcc2 = rcc2;
>  
>    while ((syscon->ris & SYSCONRIS_PLLLRIS) == 0)
>        /* Wait for PLL lock */;
>  
>    rcc &= ~SYSCONRCC_BYPASS;
> +  rcc2 &= ~(SYSCONRCC2_BYPASS2);
> +
>    syscon->rcc = rcc;
> +  syscon->rcc2 = rcc2;
> +  lm3s69xx_syscon_delay_3x_clocks(16);
>  }

Regards,
Eugeniy Meshcheryakov
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