Atomic Operations and Required Architecture Support for RTEMS SMP

[Gedare Bloom]

On Wed, Aug 28, 2013 at 9:19 AM, Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
> Hello,
>
> as part of a GSoC project we made the atomic operations API compatible with
> the C11 operations and use them for the implementation.  I added some tests
> today and now begin to think if this was really such a good idea:
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58259
>
> Surprisingly it seems that the atomic operations support is not shared by
> the C and C++ compiler parts in GCC.
>
> I just realized that the C11 atomic_flag type has no load operation.  This
> makes it not suitable to implement a simple test and test and set lock.  So
> this type is useless for us.  The only special thing with atomic_flag is
> that it is guaranteed to be lock free.  This is the minimum requirement for
> atomic operations.
>
> This leads to the following question: What is the RTEMS (!) minimum
> requirement for SMP support?
>
> I think an architecture must support a compare and swap instruction or the
> load linked and store conditional model.  We should make it clear that a
> simple atomic swap is not enough to support SMP.
>
To avoid ABA Problem the architecture apparently should have LL/SC or
double-word CAS. http://en.wikipedia.org/wiki/ABA_problem

Options moving forward include:
* Revert to custom implementations based on upstream *BSD.
* Try to fix upstream newlib/gcc code
* Use some library like http://concurrencykit.org/ that we looked at
before, but it does not support ARM right now.

> Under this requirement we can remove the atomic flag from the RTEMS API.
>
> --
> Sebastian Huber, embedded brains GmbH
>
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>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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