[rtems commit] Add Moxie CPU support
Joel Sherrill
joel.sherrill at OARcorp.com
Thu Feb 28 19:10:14 UTC 2013
Hi
I have a follow up patch to address some issues:
+ /*PAGE is obsolete
+ blank lines between comment blocks and methods
are slowly on the way out. Many are gone.
But there are others some of which are longer term comments
on how the port develops as the gaps gets filled in.
+ Check for blanks at the end of line before submitting and
remove them.
+ cpu.h has XXX for many places where Moxie specific
comments could go. Or NONE if you don't have anything
to say like on stack grows up
+ With Google Code In, we got most ports to have their comments
in Doxygen format. Some Doxygen notation is in place.
+ _CPU_Null_fp_context - Does the Moxie have an FPU? This isn't
really used as best I can tell. It isn't initialized.
+ Does the Moxie have a bit scan or find first bit type instruction?
+ Will the Moxie use Simple Vectored Interrupts or is it an
architecture that will usually have an external PIC?
+ We need a chapter in doc/cpu_supplement on the Moxie.
Thanks. It is really much easier (for me) to review code in place,
fix some, pass some back to you, etc. than to keep reviewing
large patches.
--joel
On 2/28/2013 11:19 AM, Gedare Bloom wrote:
> Module: rtems
> Branch: master
> Commit: ff11282c63811ff893a35fbc16e195e0e8089f4d
> Changeset: http://git.rtems.org/rtems/commit/?id=ff11282c63811ff893a35fbc16e195e0e8089f4d
>
> Author: Anthony Green <green at moxielogic.com>
> Date: Wed Feb 27 13:13:19 2013 -0500
>
> Add Moxie CPU support
>
> Signed-off-by: Anthony Green <green at moxielogic.com>
>
> ---
>
> cpukit/score/cpu/moxie/Makefile.am | 19 +
> cpukit/score/cpu/moxie/cpu.c | 150 +++
> cpukit/score/cpu/moxie/cpu_asm.S | 117 +++
> .../score/cpu/moxie/moxie-exception-frame-print.c | 18 +
> cpukit/score/cpu/moxie/preinstall.am | 41 +
> cpukit/score/cpu/moxie/rtems/asm.h | 116 +++
> cpukit/score/cpu/moxie/rtems/score/cpu.h | 1090 ++++++++++++++++++++
> cpukit/score/cpu/moxie/rtems/score/moxie.h | 43 +
> cpukit/score/cpu/moxie/rtems/score/types.h | 53 +
> 9 files changed, 1647 insertions(+), 0 deletions(-)
>
> diff --git a/cpukit/score/cpu/moxie/Makefile.am b/cpukit/score/cpu/moxie/Makefile.am
> new file mode 100644
> index 0000000..931ca06
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/Makefile.am
> @@ -0,0 +1,19 @@
> +##
> +## $Id: Makefile.am,v 1.35 2006/01/12 09:57:43 ralf Exp $
> +##
> +
> +include $(top_srcdir)/automake/compile.am
> +
> +include_rtemsdir = $(includedir)/rtems
> +include_rtems_HEADERS = rtems/asm.h
> +
> +include_rtems_scoredir = $(includedir)/rtems/score
> +include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/moxie.h \
> + rtems/score/types.h
> +
> +noinst_LIBRARIES = libscorecpu.a
> +libscorecpu_a_SOURCES = cpu.c moxie-exception-frame-print.c cpu_asm.S
> +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
> +
> +include $(srcdir)/preinstall.am
> +include $(top_srcdir)/automake/local.am
> diff --git a/cpukit/score/cpu/moxie/cpu.c b/cpukit/score/cpu/moxie/cpu.c
> new file mode 100644
> index 0000000..b5e2a2b
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/cpu.c
> @@ -0,0 +1,150 @@
> +/*
> + * Moxie CPU Dependent Source
> + *
> + * COPYRIGHT (c) 2011 Anthony Green
> + *
> + * Based on example code and other ports with this copyright:
> + *
> + * COPYRIGHT (c) 1989-1999, 2010.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifdef HAVE_CONFIG_H
> +#include "config.h"
> +#endif
> +
> +#include <rtems/system.h>
> +#include <rtems/score/isr.h>
> +#include <rtems/score/wkspace.h>
> +
> +/* _CPU_Initialize
> + *
> + * This routine performs processor dependent initialization.
> + *
> + * INPUT PARAMETERS: NONE
> + */
> +
> +
> +void _CPU_Initialize(void)
> +{
> + /*
> + * If there is not an easy way to initialize the FP context
> + * during Context_Initialize, then it is usually easier to
> + * save an "uninitialized" FP context here and copy it to
> + * the task's during Context_Initialize.
> + */
> +
> + /* FP context initialization support goes here */
> +}
> +
> +/*PAGE
> + *
> + * _CPU_ISR_Get_level
> + *
> + * This routine returns the current interrupt level.
> + */
> +
> +uint32_t _CPU_ISR_Get_level( void )
> +{
> + return 0;
> +}
> +
> +/*PAGE
> + *
> + * _CPU_ISR_install_raw_handler
> + */
> +
> +void _CPU_ISR_install_raw_handler(
> + uint32_t vector,
> + proc_ptr new_handler,
> + proc_ptr *old_handler
> +)
> +{
> + /*
> + * This is where we install the interrupt handler into the "raw" interrupt
> + * table used by the CPU to dispatch interrupt handlers.
> + * Use Debug level IRQ Handlers
> + */
> + /* H8BD_Install_IRQ(vector,new_handler,old_handler); */
> +}
> +
> +/*PAGE
> + *
> + * _CPU_ISR_install_vector
> + *
> + * This kernel routine installs the RTEMS handler for the
> + * specified vector.
> + *
> + * Input parameters:
> + * vector - interrupt vector number
> + * old_handler - former ISR for this vector number
> + * new_handler - replacement ISR for this vector number
> + *
> + * Output parameters: NONE
> + *
> + */
> +
> +void _CPU_ISR_install_vector(
> + uint32_t vector,
> + proc_ptr new_handler,
> + proc_ptr *old_handler
> +)
> +{
> + *old_handler = _ISR_Vector_table[ vector ];
> +
> + /*
> + * If the interrupt vector table is a table of pointer to isr entry
> + * points, then we need to install the appropriate RTEMS interrupt
> + * handler for this vector number.
> + */
> +
> + _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
> +
> + /*
> + * We put the actual user ISR address in '_ISR_vector_table'. This will
> + * be used by the _ISR_Handler so the user gets control.
> + */
> +
> + _ISR_Vector_table[ vector ] = new_handler;
> +}
> +
> +/*PAGE
> + *
> + * _CPU_Install_interrupt_stack
> + */
> +
> +void _CPU_Install_interrupt_stack( void )
> +{
> +}
> +
> +/*PAGE
> + *
> + * _CPU_Thread_Idle_body
> + *
> + * NOTES:
> + *
> + * 1. This is the same as the regular CPU independent algorithm.
> + *
> + * 2. If you implement this using a "halt", "idle", or "shutdown"
> + * instruction, then don't forget to put it in an infinite loop.
> + *
> + * 3. Be warned. Some processors with onboard DMA have been known
> + * to stop the DMA if the CPU were put in IDLE mode. This might
> + * also be a problem with other on-chip peripherals. So use this
> + * hook with caution.
> + */
> +
> +#if 0
> +void *_CPU_Thread_Idle_body( uintptr_t ignored )
> +{
> +
> + for( ; ; )
> + IDLE_Monitor();
> + /*asm(" sleep \n"); */
> + /* insert your "halt" instruction here */ ;
> +}
> +#endif
> diff --git a/cpukit/score/cpu/moxie/cpu_asm.S b/cpukit/score/cpu/moxie/cpu_asm.S
> new file mode 100644
> index 0000000..31d2039
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/cpu_asm.S
> @@ -0,0 +1,117 @@
> +/*
> + * Moxie CPU functions
> + * Copyright (C) 2011 Anthony Green
> + *
> + * Based on example code and other ports with this copyright:
> + *
> + * COPYRIGHT (c) 1989-1999.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifdef HAVE_CONFIG_H
> +#include "config.h"
> +#endif
> +
> +#include <rtems/asm.h>
> +
> + .text
> + .align 2
> +
> + .global SYM(_CPU_Context_switch)
> +
> +SYM(_CPU_Context_switch):
> + sto.l 0($r0), $fp
> + sto.l 4($r0), $sp
> + sto.l 8($r0), $r0
> + sto.l 12($r0), $r1
> + sto.l 16($r0), $r2
> + sto.l 20($r0), $r3
> + sto.l 24($r0), $r4
> + sto.l 28($r0), $r5
> + sto.l 32($r0), $r6
> + sto.l 36($r0), $r7
> + sto.l 40($r0), $r8
> + sto.l 44($r0), $r9
> + sto.l 48($r0), $r10
> + sto.l 52($r0), $r11
> + sto.l 56($r0), $r12
> + sto.l 60($r0), $r13
> +
> +restore:
> + ldo.l $fp, 0($r1)
> + ldo.l $sp, 4($r1)
> + ldo.l $r0, 8($r1)
> + ldo.l $r2, 16($r1)
> + ldo.l $r3, 20($r1)
> + ldo.l $r4, 24($r1)
> + ldo.l $r5, 28($r1)
> + ldo.l $r6, 32($r1)
> + ldo.l $r7, 36($r1)
> + ldo.l $r8, 40($r1)
> + ldo.l $r9, 44($r1)
> + ldo.l $r10, 48($r1)
> + ldo.l $r11, 52($r1)
> + ldo.l $r12, 56($r1)
> + ldo.l $r13, 60($r1)
> + ldo.l $r1, 12($r1)
> +
> + ret
> +
> + .align 2
> +
> + .global SYM(_CPU_Context_restore)
> +
> +SYM(_CPU_Context_restore):
> + mov $r1, $r0
> + jmpa restore
> +
> +
> +/*
> + VHandler for Vectored Interrupts
> +
> + All IRQ's are vectored to routine _ISR_#vector_number
> + This routine stacks er0 and loads er0 with vector number
> + before transferring to here
> +
> +*/
> + .align 2
> + .global SYM(_ISR_Handler)
> + .extern SYM(_Vector_table)
> +
> +
> +SYM(_ISR_Handler):
> + brk
> +
> +
> +/*
> + Called from ISR_Handler as a way of ending IRQ
> + but allowing dispatch to another task.
> + Must use RTE as CCR is still on stack but IRQ has been serviced.
> + CCR and PC occupy same word so rte can be used.
> + now using task stack
> +*/
> +
> + .align 2
> + .global SYM(_ISR_Dispatch)
> +
> +SYM(_ISR_Dispatch):
> + brk
> +
> +
> + .align 2
> + .global SYM(_CPU_Context_save_fp)
> +
> +SYM(_CPU_Context_save_fp):
> + brk
> +
> +
> + .align 2
> + .global SYM(_CPU_Context_restore_fp)
> +
> +SYM(_CPU_Context_restore_fp):
> + brk
> +
> diff --git a/cpukit/score/cpu/moxie/moxie-exception-frame-print.c b/cpukit/score/cpu/moxie/moxie-exception-frame-print.c
> new file mode 100644
> index 0000000..3882fb6
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/moxie-exception-frame-print.c
> @@ -0,0 +1,18 @@
> +/*
> + * Copyright (c) 2013 Anthony Green
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifdef HAVE_CONFIG_H
> + #include "config.h"
> +#endif
> +
> +#include <rtems/score/cpu.h>
> +
> +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
> +{
> + /* TODO */
> +}
> diff --git a/cpukit/score/cpu/moxie/preinstall.am b/cpukit/score/cpu/moxie/preinstall.am
> new file mode 100644
> index 0000000..62a2390
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/preinstall.am
> @@ -0,0 +1,41 @@
> +## Automatically generated by ampolish3 - Do not edit
> +
> +if AMPOLISH3
> +$(srcdir)/preinstall.am: Makefile.am
> + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
> +endif
> +
> +PREINSTALL_DIRS =
> +DISTCLEANFILES = $(PREINSTALL_DIRS)
> +
> +all-am: $(PREINSTALL_FILES)
> +
> +PREINSTALL_FILES =
> +CLEANFILES = $(PREINSTALL_FILES)
> +
> +$(PROJECT_INCLUDE)/rtems/$(dirstamp):
> + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
> + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> +
> +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
> +
> +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
> + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
> + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> +
> +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
> +
> +$(PROJECT_INCLUDE)/rtems/score/moxie.h: rtems/score/moxie.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/moxie.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/moxie.h
> +
> +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
> +
> diff --git a/cpukit/score/cpu/moxie/rtems/asm.h b/cpukit/score/cpu/moxie/rtems/asm.h
> new file mode 100644
> index 0000000..5ef1d13
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/rtems/asm.h
> @@ -0,0 +1,116 @@
> +/**
> + * @file rtems/asm.h
> + *
> + * This include file attempts to address the problems
> + * caused by incompatible flavors of assemblers and
> + * toolsets. It primarily addresses variations in the
> + * use of leading underscores on symbols and the requirement
> + * that register names be preceded by a %.
> + */
> +
> +/*
> + * NOTE: The spacing in the use of these macros
> + * is critical to them working as advertised.
> + *
> + * COPYRIGHT:
> + *
> + * This file is based on similar code found in newlib available
> + * from ftp.cygnus.com. The file which was used had no copyright
> + * notice. This file is freely distributable as long as the source
> + * of the file is noted. This file is:
> + *
> + * COPYRIGHT (c) 2011
> + * Anthony Green
> + *
> + * COPYRIGHT (c) 1989-1999, 2010.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + *
> + * $Id: asm.h,v 1.9 2010/06/29 00:31:09 joel Exp $
> + */
> +
> +#ifndef _RTEMS_ASM_H
> +#define _RTEMS_ASM_H
> +
> +/*
> + * Indicate we are in an assembly file and get the basic CPU definitions.
> + */
> +
> +#include <rtems/score/moxie.h>
> +
> +/*
> + * Recent versions of GNU cpp define variables which indicate the
> + * need for underscores and percents. If not using GNU cpp or
> + * the version does not support this, then you will obviously
> + * have to define these as appropriate.
> + */
> +
> +#ifndef __USER_LABEL_PREFIX__
> +#define __USER_LABEL_PREFIX__
> +#endif
> +
> +#ifndef __REGISTER_PREFIX__
> +#define __REGISTER_PREFIX__ "$"
> +#endif
> +
> +#include <rtems/concat.h>
> +
> +/* Use the right prefix for global labels. */
> +
> +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
> +
> +/* Use the right prefix for registers. */
> +
> +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
> +
> +/*
> + * define macros for all of the registers on this CPU
> + *
> + * EXAMPLE: #define d0 REG (d0)
> + */
> +#define fp REG(fp)
> +#define sp REG(sp)
> +#define r0 REG(r0)
> +#define r1 REG(r1)
> +#define r2 REG(r2)
> +#define r3 REG(r3)
> +#define r4 REG(r4)
> +#define r5 REG(r5)
> +#define r6 REG(r6)
> +#define r7 REG(r7)
> +#define r8 REG(r8)
> +#define r9 REG(r9)
> +#define r10 REG(r10)
> +#define r11 REG(r11)
> +#define r12 REG(r12)
> +#define r13 REG(r13)
> +
> +/*
> + * Define macros to handle section beginning and ends.
> + */
> +
> +
> +#define BEGIN_CODE_DCL .text
> +#define END_CODE_DCL
> +#define BEGIN_DATA_DCL .data
> +#define END_DATA_DCL
> +#define BEGIN_CODE asm ( ".text
> +#define END_CODE ");
> +#define BEGIN_DATA
> +#define END_DATA
> +#define BEGIN_BSS
> +#define END_BSS
> +#define END
> +
> +/*
> + * Following must be tailor for a particular flavor of the C compiler.
> + * They may need to put underscores in front of the symbols.
> + */
> +
> +#define PUBLIC(sym) .globl SYM (sym)
> +#define EXTERN(sym) .globl SYM (sym)
> +
> +#endif
> diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h
> new file mode 100644
> index 0000000..a390af0
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/rtems/score/cpu.h
> @@ -0,0 +1,1090 @@
> +/**
> + * @file rtems/score/cpu.h
> + */
> +
> +/*
> + * This include file contains information pertaining to the Moxie
> + * processor.
> + *
> + * Copyright (c) 2013 Anthony Green
> + *
> + * Based on code with the following copyright..
> + * COPYRIGHT (c) 1989-2006, 2010.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifndef _RTEMS_SCORE_CPU_H
> +#define _RTEMS_SCORE_CPU_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <rtems/score/types.h>
> +#include <rtems/score/moxie.h> /* pick up machine definitions */
> +
> +#include <rtems/bspIo.h> /* printk */
> +
> +/* conditional compilation parameters */
> +
> +/*
> + * Should the calls to _Thread_Enable_dispatch be inlined?
> + *
> + * If TRUE, then they are inlined.
> + * If FALSE, then a subroutine call is made.
> + *
> + * Basically this is an example of the classic trade-off of size
> + * versus speed. Inlining the call (TRUE) typically increases the
> + * size of RTEMS while speeding up the enabling of dispatching.
> + * [NOTE: In general, the _Thread_Dispatch_disable_level will
> + * only be 0 or 1 unless you are in an interrupt handler and that
> + * interrupt handler invokes the executive.] When not inlined
> + * something calls _Thread_Enable_dispatch which in turns calls
> + * _Thread_Dispatch. If the enable dispatch is inlined, then
> + * one subroutine call is avoided entirely.]
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_INLINE_ENABLE_DISPATCH FALSE
> +
> +/*
> + * Should the body of the search loops in _Thread_queue_Enqueue_priority
> + * be unrolled one time? In unrolled each iteration of the loop examines
> + * two "nodes" on the chain being searched. Otherwise, only one node
> + * is examined per iteration.
> + *
> + * If TRUE, then the loops are unrolled.
> + * If FALSE, then the loops are not unrolled.
> + *
> + * The primary factor in making this decision is the cost of disabling
> + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
> + * body of the loop. On some CPUs, the flash is more expensive than
> + * one iteration of the loop body. In this case, it might be desirable
> + * to unroll the loop. It is important to note that on some CPUs, this
> + * code is the longest interrupt disable period in RTEMS. So it is
> + * necessary to strike a balance when setting this parameter.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
> +
> +/*
> + * Should this target use 16 or 32 bit object Ids?
> + *
> + */
> +#define RTEMS_USE_32_BIT_OBJECT
> +
> +/*
> + * Does RTEMS manage a dedicated interrupt stack in software?
> + *
> + * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
> + * If FALSE, nothing is done.
> + *
> + * If the CPU supports a dedicated interrupt stack in hardware,
> + * then it is generally the responsibility of the BSP to allocate it
> + * and set it up.
> + *
> + * If the CPU does not support a dedicated interrupt stack, then
> + * the porter has two options: (1) execute interrupts on the
> + * stack of the interrupted task, and (2) have RTEMS manage a dedicated
> + * interrupt stack.
> + *
> + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
> + *
> + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
> + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
> + * possible that both are FALSE for a particular CPU. Although it
> + * is unclear what that would imply about the interrupt processing
> + * procedure on that CPU.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
> +
> +/*
> + * Does the CPU follow the simple vectored interrupt model?
> + *
> + * If TRUE, then RTEMS allocates the vector table it internally manages.
> + * If FALSE, then the BSP is assumed to allocate and manage the vector
> + * table
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX document implementation including references if appropriate
> + */
> +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
> +
> +/*
> + * Does this CPU have hardware support for a dedicated interrupt stack?
> + *
> + * If TRUE, then it must be installed during initialization.
> + * If FALSE, then no installation is performed.
> + *
> + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
> + *
> + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
> + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
> + * possible that both are FALSE for a particular CPU. Although it
> + * is unclear what that would imply about the interrupt processing
> + * procedure on that CPU.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
> +
> +/*
> + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
> + *
> + * If TRUE, then the memory is allocated during initialization.
> + * If FALSE, then the memory is allocated during initialization.
> + *
> + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
> +
> +/*
> + * Does the CPU have hardware floating point?
> + *
> + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
> + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
> + *
> + * If there is a FP coprocessor such as the i387 or mc68881, then
> + * the answer is TRUE.
> + *
> + * The macro name "MOXIE_HAS_FPU" should be made CPU specific.
> + * It indicates whether or not this CPU model has FP support. For
> + * example, it would be possible to have an i386_nofp CPU model
> + * which set this to false to indicate that you have an i386 without
> + * an i387 and wish to leave floating point support out of RTEMS.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_HARDWARE_FP FALSE
> +
> +/*
> + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
> + *
> + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
> + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
> + *
> + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_ALL_TASKS_ARE_FP FALSE
> +
> +/*
> + * Should the IDLE task have a floating point context?
> + *
> + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
> + * and it has a floating point context which is switched in and out.
> + * If FALSE, then the IDLE task does not have a floating point context.
> + *
> + * Setting this to TRUE negatively impacts the time required to preempt
> + * the IDLE task from an interrupt because the floating point context
> + * must be saved as part of the preemption.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_IDLE_TASK_IS_FP FALSE
> +
> +/*
> + * Should the saving of the floating point registers be deferred
> + * until a context switch is made to another different floating point
> + * task?
> + *
> + * If TRUE, then the floating point context will not be stored until
> + * necessary. It will remain in the floating point registers and not
> + * disturned until another floating point task is switched to.
> + *
> + * If FALSE, then the floating point context is saved when a floating
> + * point task is switched out and restored when the next floating point
> + * task is restored. The state of the floating point registers between
> + * those two operations is not specified.
> + *
> + * If the floating point context does NOT have to be saved as part of
> + * interrupt dispatching, then it should be safe to set this to TRUE.
> + *
> + * Setting this flag to TRUE results in using a different algorithm
> + * for deciding when to save and restore the floating point context.
> + * The deferred FP switch algorithm minimizes the number of times
> + * the FP context is saved and restored. The FP context is not saved
> + * until a context switch is made to another, different FP task.
> + * Thus in a system with only one FP task, the FP context will never
> + * be saved or restored.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_USE_DEFERRED_FP_SWITCH TRUE
> +
> +/*
> + * Does this port provide a CPU dependent IDLE task implementation?
> + *
> + * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
> + * must be provided and is the default IDLE thread body instead of
> + * _Internal_threads_Idle_thread_body.
> + *
> + * If FALSE, then use the generic IDLE thread body if the BSP does
> + * not provide one.
> + *
> + * This is intended to allow for supporting processors which have
> + * a low power or idle mode. When the IDLE thread is executed, then
> + * the CPU can be powered down.
> + *
> + * The order of precedence for selecting the IDLE thread body is:
> + *
> + * 1. BSP provided
> + * 2. CPU dependent (if provided)
> + * 3. generic (if no BSP and no CPU dependent)
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + * The port initially called a BSP dependent routine called
> + * IDLE_Monitor. The idle task body can be overridden by
> + * the BSP in newer versions of RTEMS.
> + */
> +
> +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
> +
> +/*
> + * Does the stack grow up (toward higher addresses) or down
> + * (toward lower addresses)?
> + *
> + * If TRUE, then the grows upward.
> + * If FALSE, then the grows toward smaller addresses.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_STACK_GROWS_UP FALSE
> +
> +/*
> + * The following is the variable attribute used to force alignment
> + * of critical RTEMS structures. On some processors it may make
> + * sense to have these aligned on tighter boundaries than
> + * the minimum requirements of the compiler in order to have as
> + * much of the critical data area as possible in a cache line.
> + *
> + * The placement of this macro in the declaration of the variables
> + * is based on the syntactically requirements of the GNU C
> + * "__attribute__" extension. For example with GNU C, use
> + * the following to force a structures to a 32 byte boundary.
> + *
> + * __attribute__ ((aligned (32)))
> + *
> + * NOTE: Currently only the Priority Bit Map table uses this feature.
> + * To benefit from using this, the data must be heavily
> + * used so it will stay in the cache and used frequently enough
> + * in the executive to justify turning this on.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_STRUCTURE_ALIGNMENT
> +
> +#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
> +#define CPU_TIMESTAMP_USE_INT64 FALSE
> +#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
> +
> +/*
> + * Define what is required to specify how the network to host conversion
> + * routines are handled.
> + */
> +
> +#define CPU_BIG_ENDIAN TRUE
> +#define CPU_LITTLE_ENDIAN FALSE
> +
> +/*
> + * The following defines the number of bits actually used in the
> + * interrupt field of the task mode. How those bits map to the
> + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_MODES_INTERRUPT_MASK 0x00000001
> +
> +/*
> + * Processor defined structures required for cpukit/score.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +/* may need to put some structures here. */
> +
> +/*
> + * Contexts
> + *
> + * Generally there are 2 types of context to save.
> + * 1. Interrupt registers to save
> + * 2. Task level registers to save
> + *
> + * This means we have the following 3 context items:
> + * 1. task level context stuff:: Context_Control
> + * 2. floating point task stuff:: Context_Control_fp
> + * 3. special interrupt level context :: Context_Control_interrupt
> + *
> + * On some processors, it is cost-effective to save only the callee
> + * preserved registers during a task context switch. This means
> + * that the ISR code needs to save those registers which do not
> + * persist across function calls. It is not mandatory to make this
> + * distinctions between the caller/callee saves registers for the
> + * purpose of minimizing context saved during task switch and on interrupts.
> + * If the cost of saving extra registers is minimal, simplicity is the
> + * choice. Save the same context on interrupt entry as for tasks in
> + * this case.
> + *
> + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
> + * care should be used in designing the context area.
> + *
> + * On some CPUs with hardware floating point support, the Context_Control_fp
> + * structure will not be used or it simply consist of an array of a
> + * fixed number of bytes. This is done when the floating point context
> + * is dumped by a "FP save context" type instruction and the format
> + * is not really defined by the CPU. In this case, there is no need
> + * to figure out the exact format -- only the size. Of course, although
> + * this is enough information for RTEMS, it is probably not enough for
> + * a debugger such as gdb. But that is another problem.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +
> +
> +#define nogap __attribute__ ((packed))
> +
> +typedef struct {
> + void *fp nogap;
> + void *sp nogap;
> + uint32_t r0 nogap;
> + uint32_t r1 nogap;
> + uint32_t r2 nogap;
> + uint32_t r3 nogap;
> + uint32_t r4 nogap;
> + uint32_t r5 nogap;
> + uint32_t r6 nogap;
> + uint32_t r7 nogap;
> + uint32_t r8 nogap;
> + uint32_t r9 nogap;
> + uint32_t r10 nogap;
> + uint32_t r11 nogap;
> + uint32_t r12 nogap;
> + uint32_t r13 nogap;
> +} Context_Control;
> +
> +#define _CPU_Context_Get_SP( _context ) \
> + (_context)->sp
> +
> +typedef struct {
> + double some_float_register[2];
> +} Context_Control_fp;
> +
> +typedef struct {
> + uint32_t special_interrupt_register;
> +} CPU_Interrupt_frame;
> +
> +/*
> + * This variable is optional. It is used on CPUs on which it is difficult
> + * to generate an "uninitialized" FP context. It is filled in by
> + * _CPU_Initialize and copied into the task's FP context area during
> + * _CPU_Context_Initialize.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
> +
> +/*
> + * Nothing prevents the porter from declaring more CPU specific variables.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +/* XXX: if needed, put more variables here */
> +
> +/*
> + * The size of the floating point context area. On some CPUs this
> + * will not be a "sizeof" because the format of the floating point
> + * area is not defined -- only the size is. This is usually on
> + * CPUs with a "floating point save context" instruction.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
> +
> +/*
> + * Amount of extra stack (above minimum stack size) required by
> + * system initialization thread. Remember that in a multiprocessor
> + * system the system intialization thread becomes the MP server thread.
> + *
> + * MOXIE Specific Information:
> + *
> + * It is highly unlikely the MOXIE will get used in a multiprocessor system.
> + */
> +
> +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
> +
> +/*
> + * This defines the number of entries in the ISR_Vector_table managed
> + * by RTEMS.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64
> +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
> +
> +/*
> + * This is defined if the port has a special way to report the ISR nesting
> + * level. Most ports maintain the variable _ISR_Nest_level.
> + */
> +
> +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
> +
> +/*
> + * Should be large enough to run all RTEMS tests. This ensures
> + * that a "reasonable" small application should not have any problems.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_STACK_MINIMUM_SIZE (1536)
> +
> +/**
> + * Size of a pointer.
> + *
> + * This must be an integer literal that can be used by the assembler. This
> + * value will be used to calculate offsets of structure members. These
> + * offsets will be used in assembler code.
> + */
> +#define CPU_SIZEOF_POINTER 4
> +
> +/*
> + * CPU's worst alignment requirement for data types on a byte boundary. This
> + * alignment does not take into account the requirements for the stack.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_ALIGNMENT 8
> +
> +/*
> + * This number corresponds to the byte alignment requirement for the
> + * heap handler. This alignment requirement may be stricter than that
> + * for the data types alignment specified by CPU_ALIGNMENT. It is
> + * common for the heap to follow the same alignment requirement as
> + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
> + * then this should be set to CPU_ALIGNMENT.
> + *
> + * NOTE: This does not have to be a power of 2. It does have to
> + * be greater or equal to than CPU_ALIGNMENT.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
> +
> +/*
> + * This number corresponds to the byte alignment requirement for memory
> + * buffers allocated by the partition manager. This alignment requirement
> + * may be stricter than that for the data types alignment specified by
> + * CPU_ALIGNMENT. It is common for the partition to follow the same
> + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
> + * enough for the partition, then this should be set to CPU_ALIGNMENT.
> + *
> + * NOTE: This does not have to be a power of 2. It does have to
> + * be greater or equal to than CPU_ALIGNMENT.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
> +
> +/*
> + * This number corresponds to the byte alignment requirement for the
> + * stack. This alignment requirement may be stricter than that for the
> + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
> + * is strict enough for the stack, then this should be set to 0.
> + *
> + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_STACK_ALIGNMENT 0
> +
> +/*
> + * ISR handler macros
> + */
> +
> +/*
> + * Support routine to initialize the RTEMS vector table after it is allocated.
> + */
> +
> +#define _CPU_Initialize_vectors()
> +
> +/*
> + * Disable all interrupts for an RTEMS critical section. The previous
> + * level is returned in _level.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
> +
> +/*
> + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
> + * This indicates the end of an RTEMS critical section. The parameter
> + * _level is not modified.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_ISR_Enable( _isr_cookie )
> +
> +/*
> + * This temporarily restores the interrupt to _level before immediately
> + * disabling them again. This is used to divide long RTEMS critical
> + * sections into two or more parts. The parameter _level is not
> + * modified.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_ISR_Flash( _isr_cookie )
> +
> +/*
> + * Map interrupt level in task mode onto the hardware that the CPU
> + * actually provides. Currently, interrupt levels which do not
> + * map onto the CPU in a generic fashion are undefined. Someday,
> + * it would be nice if these were "mapped" by the application
> + * via a callout. For example, m68k has 8 levels 0 - 7, levels
> + * 8 - 255 would be available for bsp/application specific meaning.
> + * This could be used to manage a programmable interrupt controller
> + * via the rtems_task_mode directive.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_ISR_Set_level( _new_level ) \
> + { \
> + if (_new_level) asm volatile ( "nop\n" ); \
> + else asm volatile ( "nop\n" ); \
> + }
> +
> +uint32_t _CPU_ISR_Get_level( void );
> +
> +/* end of ISR handler macros */
> +
> +/* Context handler macros */
> +
> +/*
> + * Initialize the context to a state suitable for starting a
> + * task after a context restore operation. Generally, this
> + * involves:
> + *
> + * - setting a starting address
> + * - preparing the stack
> + * - preparing the stack and frame pointers
> + * - setting the proper interrupt level in the context
> + * - initializing the floating point context
> + *
> + * This routine generally does not set any unnecessary register
> + * in the context. The state of the "general data" registers is
> + * undefined at task start time.
> + *
> + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
> + * point thread. This is typically only used on CPUs where the
> + * FPU may be easily disabled by software such as on the SPARC
> + * where the PSR contains an enable FPU bit.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +
> +#define CPU_CCR_INTERRUPTS_ON 0x80
> +#define CPU_CCR_INTERRUPTS_OFF 0x00
> +
> +#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
> + _isr, _entry_point, _is_fp ) \
> + /* Locate Me */ \
> + do { \
> + uintptr_t _stack; \
> + \
> + _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \
> + *((proc_ptr *)(_stack)) = (_entry_point); \
> + _stack -= 4; \
> + (_the_context)->fp = (void *)_stack; \
> + (_the_context)->sp = (void *)_stack; \
> + } while (0)
> +
> +
> +/*
> + * This routine is responsible for somehow restarting the currently
> + * executing task. If you are lucky, then all that is necessary
> + * is restoring the context. Otherwise, there will need to be
> + * a special assembly routine which does something special in this
> + * case. Context_Restore should work most of the time. It will
> + * not work if restarting self conflicts with the stack frame
> + * assumptions of restoring a context.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_Context_Restart_self( _the_context ) \
> + _CPU_Context_restore( (_the_context) );
> +
> +/*
> + * The purpose of this macro is to allow the initial pointer into
> + * a floating point context area (used to save the floating point
> + * context) to be at an arbitrary place in the floating point
> + * context area.
> + *
> + * This is necessary because some FP units are designed to have
> + * their context saved as a stack which grows into lower addresses.
> + * Other FP units can be saved by simply moving registers into offsets
> + * from the base of the context area. Finally some FP units provide
> + * a "dump context" instruction which could fill in from high to low
> + * or low to high based on the whim of the CPU designers.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_Context_Fp_start( _base, _offset ) \
> + ( (void *) (_base) + (_offset) )
> +
> +/*
> + * This routine initializes the FP context area passed to it to.
> + * There are a few standard ways in which to initialize the
> + * floating point context. The code included for this macro assumes
> + * that this is a CPU in which a "initial" FP context was saved into
> + * _CPU_Null_fp_context and it simply copies it to the destination
> + * context passed to it.
> + *
> + * Other models include (1) not doing anything, and (2) putting
> + * a "null FP status word" in the correct place in the FP context.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_Context_Initialize_fp( _destination ) \
> + { \
> + *(*(_destination)) = _CPU_Null_fp_context; \
> + }
> +
> +/* end of Context handler macros */
> +
> +/* Fatal Error manager macros */
> +
> +/*
> + * This routine copies _error into a known place -- typically a stack
> + * location or a register, optionally disables interrupts, and
> + * halts/stops the CPU.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define _CPU_Fatal_halt( _error ) \
> + printk("Fatal Error %d Halted\n",_error); \
> + for(;;)
> +
> +
> +/* end of Fatal Error manager macros */
> +
> +/* Bitfield handler macros */
> +
> +/*
> + * This routine sets _output to the bit number of the first bit
> + * set in _value. _value is of CPU dependent type Priority_Bit_map_control.
> + * This type may be either 16 or 32 bits wide although only the 16
> + * least significant bits will be used.
> + *
> + * There are a number of variables in using a "find first bit" type
> + * instruction.
> + *
> + * (1) What happens when run on a value of zero?
> + * (2) Bits may be numbered from MSB to LSB or vice-versa.
> + * (3) The numbering may be zero or one based.
> + * (4) The "find first bit" instruction may search from MSB or LSB.
> + *
> + * RTEMS guarantees that (1) will never happen so it is not a concern.
> + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
> + * _CPU_Priority_bits_index(). These three form a set of routines
> + * which must logically operate together. Bits in the _value are
> + * set and cleared based on masks built by _CPU_Priority_mask().
> + * The basic major and minor values calculated by _Priority_Major()
> + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
> + * to properly range between the values returned by the "find first bit"
> + * instruction. This makes it possible for _Priority_Get_highest() to
> + * calculate the major and directly index into the minor table.
> + * This mapping is necessary to ensure that 0 (a high priority major/minor)
> + * is the first bit found.
> + *
> + * This entire "find first bit" and mapping process depends heavily
> + * on the manner in which a priority is broken into a major and minor
> + * components with the major being the 4 MSB of a priority and minor
> + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
> + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
> + * to the lowest priority.
> + *
> + * If your CPU does not have a "find first bit" instruction, then
> + * there are ways to make do without it. Here are a handful of ways
> + * to implement this in software:
> + *
> + * - a series of 16 bit test instructions
> + * - a "binary search using if's"
> + * - _number = 0
> + * if _value > 0x00ff
> + * _value >>=8
> + * _number = 8;
> + *
> + * if _value > 0x0000f
> + * _value >=8
> + * _number += 4
> + *
> + * _number += bit_set_table[ _value ]
> + *
> + * where bit_set_table[ 16 ] has values which indicate the first
> + * bit set
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
> +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
> +
> +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> +
> +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
> + { \
> + (_output) = 0; /* do something to prevent warnings */ \
> + }
> +
> +#endif
> +
> +/* end of Bitfield handler macros */
> +
> +/*
> + * This routine builds the mask which corresponds to the bit fields
> + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
> + * for that routine.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> +
> +#define _CPU_Priority_Mask( _bit_number ) \
> + ( 1 << (_bit_number) )
> +
> +#endif
> +
> +/*
> + * This routine translates the bit numbers returned by
> + * _CPU_Bitfield_Find_first_bit() into something suitable for use as
> + * a major or minor component of a priority. See the discussion
> + * for that routine.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> +
> +#define _CPU_Priority_bits_index( _priority ) \
> + (_priority)
> +
> +#endif
> +
> +/* end of Priority handler macros */
> +
> +/* functions */
> +
> +/*
> + * _CPU_Initialize
> + *
> + * This routine performs CPU dependent initialization.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Initialize(void);
> +
> +/*
> + * _CPU_ISR_install_raw_handler
> + *
> + * This routine installs a "raw" interrupt handler directly into the
> + * processor's vector table.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_ISR_install_raw_handler(
> + uint32_t vector,
> + proc_ptr new_handler,
> + proc_ptr *old_handler
> +);
> +
> +/*
> + * _CPU_ISR_install_vector
> + *
> + * This routine installs an interrupt vector.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_ISR_install_vector(
> + uint32_t vector,
> + proc_ptr new_handler,
> + proc_ptr *old_handler
> +);
> +
> +/*
> + * _CPU_Install_interrupt_stack
> + *
> + * This routine installs the hardware interrupt stack pointer.
> + *
> + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
> + * is TRUE.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Install_interrupt_stack( void );
> +
> +/*
> + * _CPU_Internal_threads_Idle_thread_body
> + *
> + * This routine is the CPU dependent IDLE thread body.
> + *
> + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
> + * is TRUE.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void *_CPU_Thread_Idle_body( uint32_t );
> +
> +/*
> + * _CPU_Context_switch
> + *
> + * This routine switches from the run context to the heir context.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Context_switch(
> + Context_Control *run,
> + Context_Control *heir
> +);
> +
> +/*
> + * _CPU_Context_restore
> + *
> + * This routine is generallu used only to restart self in an
> + * efficient manner. It may simply be a label in _CPU_Context_switch.
> + *
> + * NOTE: May be unnecessary to reload some registers.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Context_restore(
> + Context_Control *new_context
> +);
> +
> +/*
> + * _CPU_Context_save_fp
> + *
> + * This routine saves the floating point context passed to it.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Context_save_fp(
> + Context_Control_fp **fp_context_ptr
> +);
> +
> +/*
> + * _CPU_Context_restore_fp
> + *
> + * This routine restores the floating point context passed to it.
> + *
> + * MOXIE Specific Information:
> + *
> + * XXX
> + */
> +
> +void _CPU_Context_restore_fp(
> + Context_Control_fp **fp_context_ptr
> +);
> +
> +/**
> + * @brief The set of registers that specifies the complete processor state.
> + *
> + * The CPU exception frame may be available in fatal error conditions like for
> + * example illegal opcodes, instruction fetch errors, or data access errors.
> + *
> + * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
> + * rtems_exception_frame_print().
> + */
> +typedef struct {
> + uint32_t integer_registers [16];
> +} CPU_Exception_frame;
> +
> +/**
> + * @brief Prints the exception frame via printk().
> + *
> + * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
> + */
> +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
> +
> +/* The following routine swaps the endian format of an unsigned int.
> + * It must be static because it is referenced indirectly.
> + *
> + * This version will work on any processor, but if there is a better
> + * way for your CPU PLEASE use it. The most common way to do this is to:
> + *
> + * swap least significant two bytes with 16-bit rotate
> + * swap upper and lower 16-bits
> + * swap most significant two bytes with 16-bit rotate
> + *
> + * Some CPUs have special instructions which swap a 32-bit quantity in
> + * a single instruction (e.g. i486). It is probably best to avoid
> + * an "endian swapping control bit" in the CPU. One good reason is
> + * that interrupts would probably have to be disabled to ensure that
> + * an interrupt does not try to access the same "chunk" with the wrong
> + * endian. Another good reason is that on some CPUs, the endian bit
> + * endianness for ALL fetches -- both code and data -- so the code
> + * will be fetched incorrectly.
> + *
> + * MOXIE Specific Information:
> + *
> + * This is the generic implementation.
> + */
> +
> +static inline uint32_t CPU_swap_u32(
> + uint32_t value
> +)
> +{
> + uint32_t byte1, byte2, byte3, byte4, swapped;
> +
> + byte4 = (value >> 24) & 0xff;
> + byte3 = (value >> 16) & 0xff;
> + byte2 = (value >> 8) & 0xff;
> + byte1 = value & 0xff;
> +
> + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
> + return( swapped );
> +}
> +
> +#define CPU_swap_u16( value ) \
> + (((value&0xff) << 8) | ((value >> 8)&0xff))
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif
> diff --git a/cpukit/score/cpu/moxie/rtems/score/moxie.h b/cpukit/score/cpu/moxie/rtems/score/moxie.h
> new file mode 100644
> index 0000000..115985d
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/rtems/score/moxie.h
> @@ -0,0 +1,43 @@
> +/**
> + * @file rtems/score/moxie.h
> + */
> +
> +/*
> + * This file contains information pertaining to the Moxie processor.
> + *
> + * COPYRIGHT (c) 2011, 2013
> + * Anthony Green
> + *
> + * Based on code with the following copyright...
> + * COPYRIGHT (c) 1989-1999, 2010.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifndef _RTEMS_SCORE_MOXIE_H
> +#define _RTEMS_SCORE_MOXIE_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> + * This file contains the information required to build
> + * RTEMS for a particular member of the "moxie"
> + * family when executing in protected mode. It does
> + * this by setting variables to indicate which implementation
> + * dependent features are present in a particular member
> + * of the family.
> + */
> +
> +#define CPU_NAME "Moxie"
> +#define CPU_MODEL_NAME "MoxieLite"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif
> diff --git a/cpukit/score/cpu/moxie/rtems/score/types.h b/cpukit/score/cpu/moxie/rtems/score/types.h
> new file mode 100644
> index 0000000..5bf1434
> --- /dev/null
> +++ b/cpukit/score/cpu/moxie/rtems/score/types.h
> @@ -0,0 +1,53 @@
> +/**
> + * @file rtems/score/types.h
> + */
> +
> +/*
> + * This file contains information pertaining to the Moxie processor.
> + *
> + * COPYRIGHT (c) 2011
> + * Anthony Green
> + *
> + * Based on code with the following copyright...
> + * COPYRIGHT (c) 1989-1999, 2010.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.com/license/LICENSE.
> + */
> +
> +#ifndef _RTEMS_SCORE_TYPES_H
> +#define _RTEMS_SCORE_TYPES_H
> +
> +#include <rtems/score/basedefs.h>
> +
> +#ifndef ASM
> +
> +#include <stdbool.h>
> +#include <stdint.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> + * This section defines the basic types for this processor.
> + */
> +typedef uint16_t Priority_bit_map_Control;
> +typedef void moxie_isr;
> +typedef void ( *moxie_isr_entry )( void );
> +
> +#ifdef RTEMS_DEPRECATED_TYPES
> +typedef bool boolean; /* Boolean value */
> +typedef float single_precision; /* single precision float */
> +typedef double double_precision; /* double precision float */
> +#endif
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* !ASM */
> +
> +#endif
>
> _______________________________________________
> rtems-vc mailing list
> rtems-vc at rtems.org
> http://www.rtems.org/mailman/listinfo/rtems-vc
--
Joel Sherrill, Ph.D. Director of Research & Development
joel.sherrill at OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
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