[PATCH 4/9] score: Simplify _CORE_semaphore_Seize_isr_disable
Sebastian Huber
sebastian.huber at embedded-brains.de
Wed Jun 5 15:22:02 UTC 2013
---
cpukit/rtems/src/semobtain.c | 2 +-
cpukit/score/inline/rtems/score/coresem.inl | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/cpukit/rtems/src/semobtain.c b/cpukit/rtems/src/semobtain.c
index fe5710e..14ed515 100644
--- a/cpukit/rtems/src/semobtain.c
+++ b/cpukit/rtems/src/semobtain.c
@@ -70,7 +70,7 @@ rtems_status_code rtems_semaphore_obtain(
id,
((_Options_Is_no_wait( option_set )) ? false : true),
timeout,
- &level
+ level
);
return _Semaphore_Translate_core_semaphore_return_code(
_Thread_Executing->Wait.return_code );
diff --git a/cpukit/score/inline/rtems/score/coresem.inl b/cpukit/score/inline/rtems/score/coresem.inl
index 69a7b26..aa021eb 100644
--- a/cpukit/score/inline/rtems/score/coresem.inl
+++ b/cpukit/score/inline/rtems/score/coresem.inl
@@ -70,7 +70,7 @@ RTEMS_INLINE_ROUTINE uint32_t _CORE_semaphore_Get_count(
* @param[in] id is the Id of the owning API level Semaphore object
* @param[in] wait is true if the thread is willing to wait
* @param[in] timeout is the maximum number of ticks to block
- * @param[in] level_p is a temporary variable used to contain the ISR
+ * @param[in] level is a temporary variable used to contain the ISR
* disable level cookie
*
* @note There is currently no MACRO version of this routine.
@@ -80,7 +80,7 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable(
Objects_Id id,
bool wait,
Watchdog_Interval timeout,
- ISR_Level *level_p
+ ISR_Level level
)
{
Thread_Control *executing;
@@ -91,12 +91,12 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable(
executing->Wait.return_code = CORE_SEMAPHORE_STATUS_SUCCESSFUL;
if ( the_semaphore->count != 0 ) {
the_semaphore->count -= 1;
- _ISR_Enable( *level_p );
+ _ISR_Enable( level );
return;
}
if ( !wait ) {
- _ISR_Enable( *level_p );
+ _ISR_Enable( level );
executing->Wait.return_code = CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT;
return;
}
@@ -105,7 +105,7 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable(
_Thread_queue_Enter_critical_section( &the_semaphore->Wait_queue );
executing->Wait.queue = &the_semaphore->Wait_queue;
executing->Wait.id = id;
- _ISR_Enable( *level_p );
+ _ISR_Enable( level );
_Thread_queue_Enqueue( &the_semaphore->Wait_queue, timeout );
_Thread_Enable_dispatch();
--
1.7.7
More information about the devel
mailing list