ISR Model for moxie

[Joel Sherrill]

Moving this back to rtems-devel

On 3/2/2013 7:31 PM, Anthony Green wrote:
> On Sat, Mar 2, 2013 at 9:50 AM, Joel Sherrill <Joel.Sherrill at oarcorp.com> wrote:
>> Before worrying about the details, let's talk in broad strokes.
>>
>> Is there a manual somewhere describing what the hardware does on an exception/interrupt?
> I just wrote down the basics in just a couple of sentences:
>
> http://moxielogic.org/wiki/index.php/Exceptions
>
>
>> I think you said there were only a few hardware "vectors" and software relied on an external PIC to determine the source. if this is right, then you are looking at the PIC model and there may be a first level decode to take you to say alignment trap handler or memory exception versus a method preferably in C which decodes and does vectoring for PIC sources plus maybe a decrementer like the PowerPC.
> This sounds right.  In the case of an external hardware interrupt,
> I'll have to read the interrupt number from the memory mapped PIC -
> but divide by zero and software interrupts can be handled directly.
You want the PIC interrupt model not the Simple Vectored Model.

I think you want to follow the ARM model and look at a recent BSP like
the lpc24xx or lpc32xx.

In assembly, I would expect you to have a common entry point for all
sources based upon what you describe. Then some quick checks to
get to handlers for exceptions like divide by zero, a sw interrupt
dispatcher, and call the "real interrupt" dispatcher written in C which
uses the shared interrupt framework.

Sebastian should comment but the part in assembly that takes the
"event" and decides where to go will be shared across all Moxie BSPs.
The divide by zero, alignment faults, etc will be common. The software
interrupt handling may be completely shared. Depends what it is used
for.

Each BSP will provide the interrupt dispatcher written in C invoked
from that assembly code. That code plus some other glue required by
the shared PIC interrupt framework is BSP specific.

The MIPS Malta BSP is also recent enough where it should provide another
archtiecture's view of this.

>> Of arm, PowerPC, MIPS and x86 which does the Moxies most resemble in this area?
> I'm not familiar enough with them.
>
> Note that none of the moxie applications so far have required
> interrupts.  They simply poll the IO devices! (and don't require
> anything like a rtc).  So I'm just making this up as I go.  I have
> what I've described above working in qemu, and it's going to be simple
> enough to implement in FPGA, but I'm also open to suggestions.
What you describe is perfectly fine. You just have to write the code that
design implies. :)
> AG
>
>
>> On all of these, the ISR model is PIC and the BSP provides code for a standard framework. Let us know the answer to the above and we can guide you to an architecture and BSP as model.
>>
>> --joel
>>
>> Anthony Green <green at moxielogic.com> wrote:
>>
>>
>> Hey Joel,
>>
>>    I'm looking for a little guidance in implementing ISRs for RTEMS.
>> I've attached two files that show how exceptions are handled on moxie.
>>   There's just a simple exception routine that looks in special
>> registers to figure out what happened.  The ISR handler in RTEMS
>> appears to take no arguments, for instance, and is based on a vector
>> model.  Any advice?
>>
>> Thanks,
>>
>> AG


-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
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