[PATCH 3/4] sparc: Document register g7 usage

Sebastian Huber sebastian.huber at embedded-brains.de
Tue Apr 22 08:46:45 UTC 2014

 doc/cpu_supplement/sparc.t |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t
index 320c250..a6862c8 100644
--- a/doc/cpu_supplement/sparc.t
+++ b/doc/cpu_supplement/sparc.t
@@ -401,6 +401,9 @@ The registers g2 through g4 are reserved for applications.  GCC uses them as
 volatile registers by default.  So they are treated like volatile registers in
 RTEMS as well.
+The register g7 is reserved for the operating system and contains the thread
+pointer used for thread-local storage (TLS) as mandated by the SPARC ABI.
 @subsubsection Floating Point Registers
 The SPARC V7 architecture includes thirty-two,

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