[PATCH 2/5] bsp/arm: Correct cache misalignment handling

[Ralf Kirchner]

---
 c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h   |   10 ++++------
 c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h |   10 +++++-----
 2 Dateien geändert, 9 Zeilen hinzugefügt(+), 11 Zeilen entfernt(-)

diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index fd57328..8af65b3 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -977,8 +977,7 @@ cache_l2c_310_flush_range( const void *addr, size_t n_bytes )
   if ( n_bytes != 0 ) {
     uint32_t       adx       = (uint32_t) addr
                                & ~CACHE_L2C_310_DATA_LINE_MASK;
-    const uint32_t ADDR_LAST =
-      ( (uint32_t) addr + n_bytes - 1 ) & ~CACHE_L2C_310_DATA_LINE_MASK;
+    const uint32_t ADDR_LAST = (uint32_t) addr + n_bytes - 1;
     volatile L2CC *l2cc      = (volatile L2CC *) BSP_ARM_L2CC_BASE;
 
     CACHE_ARM_ERRATA_764369_HANDLER();
@@ -1021,15 +1020,14 @@ static inline void
 cache_l2c_310_invalidate_range( const void *addr, size_t n_bytes )
 {
   if ( n_bytes != 0 ) {
-    uint32_t       adx  = (uint32_t) addr
+    uint32_t       adx       = (uint32_t) addr
                          & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
-    const uint32_t end  =
-      ( adx + n_bytes ) & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
+    const uint32_t ADDR_LAST = addr + n_bytes - 1;
     volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
 
     /* Back starting address up to start of a line and invalidate until end */
     for (;
-         adx < end;
+         adx <= ADDR_LAST;
          adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
       /* Invalidate L2 cache line */
       l2cc->inv_pa = adx;
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
index 0db511d..1cff72f 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
@@ -251,7 +251,7 @@ static inline void arm_cache_l1_flush_data_range(
     uint32_t       adx       = (uint32_t) d_addr
                                & ~ARM_CACHE_L1_DATA_LINE_MASK;
     const uint32_t ADDR_LAST =
-      ( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
+      (uint32_t)( (size_t) d_addr + n_bytes - 1 );
       
     ARM_CACHE_L1_ERRATA_764369_HANDLER();
 
@@ -304,13 +304,13 @@ static inline void arm_cache_l1_invalidate_data_range(
     uint32_t       adx = (uint32_t) d_addr
                          & ~ARM_CACHE_L1_DATA_LINE_MASK;
     const uint32_t end =
-      ( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
+      (uint32_t)( (size_t)d_addr + n_bytes -1);
 
     ARM_CACHE_L1_ERRATA_764369_HANDLER();
     
     /* Back starting address up to start of a line and invalidate until end */
     for (;
-         adx < end;
+         adx <= end;
          adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
         /* Invalidate the Instruction cache line */
         arm_cp15_data_cache_invalidate_line( (void*)adx );
@@ -329,7 +329,7 @@ static inline void arm_cache_l1_invalidate_instruction_range(
     uint32_t       adx = (uint32_t) i_addr
                          & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
     const uint32_t end =
-      ( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
+      (uint32_t)( (size_t)i_addr + n_bytes -1);
 
     arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
     
@@ -337,7 +337,7 @@ static inline void arm_cache_l1_invalidate_instruction_range(
     
     /* Back starting address up to start of a line and invalidate until end */
     for (;
-         adx < end;
+         adx <= end;
          adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
         /* Invalidate the Instruction cache line */
         arm_cp15_instruction_cache_invalidate_line( (void*)adx );
-- 
1.7.10.4