[PATCH] Add new documentation section for OpenRISC CPU architecture.

[Hesham ALMatary]

---
 doc/cpu_supplement/Makefile.am         |  6 +++
 doc/cpu_supplement/cpu_supplement.texi |  2 +
 doc/cpu_supplement/or1k.t              | 78 ++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 doc/cpu_supplement/or1k.t

diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 3083922..300ff78 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -23,6 +23,7 @@ GENERATED_FILES += m32r.texi
 GENERATED_FILES += m68k.texi
 GENERATED_FILES += microblaze.texi
 GENERATED_FILES += mips.texi
+GENERATED_FILES += or1k.texi
 GENERATED_FILES += powerpc.texi
 GENERATED_FILES += nios2.texi
 GENERATED_FILES += sh.texi
@@ -101,6 +102,11 @@ mips.texi: mips.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+or1k.texi: or1k.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 powerpc.texi: powerpc.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
index 1087538..5c484d0 100644
--- a/doc/cpu_supplement/cpu_supplement.texi
+++ b/doc/cpu_supplement/cpu_supplement.texi
@@ -73,6 +73,7 @@
 * M68xxx and Coldfire Specific Information::
 * Xilinx MicroBlaze Specific Information::
 * MIPS Specific Information::
+* OpenRISC 1000 Specific Information::
 * Altera Nios II Specific Information::
 * PowerPC Specific Information::
 * SuperH Specific Information::
@@ -97,6 +98,7 @@
 @include microblaze.texi
 @include mips.texi
 @include nios2.texi
+ at include or1k.texi
 @include powerpc.texi
 @include sh.texi
 @include sparc.texi
diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t
new file mode 100644
index 0000000..219f23b
--- /dev/null
+++ b/doc/cpu_supplement/or1k.t
@@ -0,0 +1,78 @@
+ at c
+ at c  COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
+ at c  All rights reserved.
+
+ at ifinfo
+ at end ifinfo
+ at chapter OpenRISC 1000 Specific Information
+
+This chapter discusses the 
+ at uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture}
+dependencies in this port of RTEMS. There are many implementations 
+for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic 
+features that all implementations should have. 
+
+ at subheading Architecture Documents
+
+For information on the OpenRISC 1000 architecture refer to the
+ at uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}.
+
+ at section Calling Conventions
+
+Please refer to the
+ at uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}.
+
+ at subsection Floating Point Unit
+
+A floating point unit is currently not supported.
+
+ at section Memory Model
+
+A flat 32-bit memory model is supported.
+
+ at section Interrupt Processing
+
+OpenRISC 1000 architecture has 13 exception types:
+
+ at itemize @bullet
+
+ at item Reset
+ at item Bus Error
+ at item Data Page Fault
+ at item Instruction Page Fault
+ at item Tick Timer
+ at item Alignment
+ at item Illegal Instruction
+ at item External Interrupt
+ at item D-TLB Miss
+ at item I-TLB Miss
+ at item Range
+ at item System Call
+ at item Floating Point
+ at item Trap
+
+ at end itemize
+
+ at subsection Interrupt Levels
+
+There are only two levels: interrupts enabled and interrupts disabled.
+ 
+ at subsection Interrupt Stack
+
+OpenRISC RTEMS port uses RTEMS SW interrupt stack.
+The stack for interrupts is allocated during interrupt driver initilization.
+When an  interrup entered, the _ISR_Handler routine is resposible for 
+switching from the interrupted task stack to RTEMS SW interrupt stack. 
+
+ at section Default Fatal Error Processing
+
+The default fatal error handler for this architecture performs the
+following actions:
+
+ at itemize @bullet
+ at item disables operating system supported interrupts (IRQ),
+ at item places the error code in @code{r0}, and
+ at item executes an infinite loop to simulate a halt processor instruction.
+ at end itemize
+
+
-- 
1.9.3