[PATCH] Add support for OpenRISC - Fixed issues
Joel Sherrill
joel.sherrill at oarcorp.com
Tue Aug 12 18:37:36 UTC 2014
OK with me.
It will be easier to address issues once merged anyway.
I plan to commit, try to build, report, then Hesham can rebase and report.
On August 12, 2014 12:49:10 PM CDT, Gedare Bloom <gedare at rtems.org> wrote:
>OK from me.
>
>On Tue, Aug 12, 2014 at 11:57 AM, Hesham ALMatary
><heshamelmatary at gmail.com> wrote:
>> This work is based on the old or32 port (that has been
>> removed back in 2005) authored by Chris Ziomkowski. The patch
>includes the
>> basic functions every port should implement like: context switch,
>exception
>> handling, OpenRISC ABI and machine definitions and configurations.
>>
>> ---
>> cpukit/configure.ac | 1 +
>> cpukit/score/cpu/Makefile.am | 1 +
>> cpukit/score/cpu/or1k/Makefile.am | 36 +
>> cpukit/score/cpu/or1k/cpu.c | 112 +++
>> cpukit/score/cpu/or1k/or1k-context-initialize.c | 43 +
>> cpukit/score/cpu/or1k/or1k-context-switch.S | 115 +++
>> cpukit/score/cpu/or1k/or1k-exception-default.c | 24 +
>> cpukit/score/cpu/or1k/or1k-exception-frame-print.c | 22 +
>> cpukit/score/cpu/or1k/or1k-exception-handler-low.S | 217 ++++
>> cpukit/score/cpu/or1k/rtems/asm.h | 99 ++
>> cpukit/score/cpu/or1k/rtems/score/cpu.h | 1051
>++++++++++++++++++++
>> cpukit/score/cpu/or1k/rtems/score/cpu_asm.h | 74 ++
>> cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 371 +++++++
>> cpukit/score/cpu/or1k/rtems/score/or1k.h | 49 +
>> cpukit/score/cpu/or1k/rtems/score/types.h | 51 +
>> 15 files changed, 2266 insertions(+)
>> create mode 100644 cpukit/score/cpu/or1k/Makefile.am
>> create mode 100644 cpukit/score/cpu/or1k/cpu.c
>> create mode 100644 cpukit/score/cpu/or1k/or1k-context-initialize.c
>> create mode 100644 cpukit/score/cpu/or1k/or1k-context-switch.S
>> create mode 100644 cpukit/score/cpu/or1k/or1k-exception-default.c
>> create mode 100644
>cpukit/score/cpu/or1k/or1k-exception-frame-print.c
>> create mode 100644
>cpukit/score/cpu/or1k/or1k-exception-handler-low.S
>> create mode 100644 cpukit/score/cpu/or1k/rtems/asm.h
>> create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu.h
>> create mode 100644 cpukit/score/cpu/or1k/rtems/score/cpu_asm.h
>> create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
>> create mode 100644 cpukit/score/cpu/or1k/rtems/score/or1k.h
>> create mode 100644 cpukit/score/cpu/or1k/rtems/score/types.h
>>
>> diff --git a/cpukit/configure.ac b/cpukit/configure.ac
>> index 19e5b81..56815e2 100644
>> --- a/cpukit/configure.ac
>> +++ b/cpukit/configure.ac
>> @@ -382,6 +382,7 @@ score/cpu/m32r/Makefile
>> score/cpu/mips/Makefile
>> score/cpu/moxie/Makefile
>> score/cpu/nios2/Makefile
>> +score/cpu/or1k/Makefile
>> score/cpu/powerpc/Makefile
>> score/cpu/sh/Makefile
>> score/cpu/sparc/Makefile
>> diff --git a/cpukit/score/cpu/Makefile.am
>b/cpukit/score/cpu/Makefile.am
>> index 8d28fc2..69abcd6 100644
>> --- a/cpukit/score/cpu/Makefile.am
>> +++ b/cpukit/score/cpu/Makefile.am
>> @@ -14,6 +14,7 @@ DIST_SUBDIRS += mips
>> DIST_SUBDIRS += moxie
>> DIST_SUBDIRS += nios2
>> DIST_SUBDIRS += no_cpu
>> +DIST_SUBDIRS += or1k
>> DIST_SUBDIRS += powerpc
>> DIST_SUBDIRS += sh
>> DIST_SUBDIRS += sparc
>> diff --git a/cpukit/score/cpu/or1k/Makefile.am
>b/cpukit/score/cpu/or1k/Makefile.am
>> new file mode 100644
>> index 0000000..b3a8ade
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/Makefile.am
>> @@ -0,0 +1,36 @@
>> +include $(top_srcdir)/automake/compile.am
>> +
>> +CLEANFILES =
>> +DISTCLEANFILES =
>> +
>> +include_rtemsdir = $(includedir)/rtems
>> +
>> +include_rtems_HEADERS = rtems/asm.h
>> +
>> +include_rtems_scoredir = $(includedir)/rtems/score
>> +
>> +include_rtems_score_HEADERS =
>> +include_rtems_score_HEADERS += rtems/score/cpu.h
>> +include_rtems_score_HEADERS += rtems/score/cpu_asm.h
>> +include_rtems_score_HEADERS += rtems/score/types.h
>> +include_rtems_score_HEADERS += rtems/score/or1k.h
>> +include_rtems_score_HEADERS += rtems/score/or1k-utility.h
>> +
>> +
>> +
>> +noinst_LIBRARIES = libscorecpu.a
>> +
>> +libscorecpu_a_SOURCES =
>> +libscorecpu_a_SOURCES += cpu.c
>> +libscorecpu_a_SOURCES += or1k-context-switch.S
>> +libscorecpu_a_SOURCES += or1k-context-initialize.c
>> +libscorecpu_a_SOURCES += or1k-exception-default.c
>> +libscorecpu_a_SOURCES += or1k-exception-frame-print.c
>> +libscorecpu_a_SOURCES += or1k-exception-handler-low.S
>> +
>> +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
>> +
>> +all-local: $(PREINSTALL_FILES)
>> +
>> +include $(srcdir)/preinstall.am
>> +include $(top_srcdir)/automake/local.am
>> diff --git a/cpukit/score/cpu/or1k/cpu.c
>b/cpukit/score/cpu/or1k/cpu.c
>> new file mode 100644
>> index 0000000..9ba49a5
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/cpu.c
>> @@ -0,0 +1,112 @@
>> +/*
>> + * Opencore OR1K CPU Dependent Source
>> + *
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + * COPYRIGHT (c) 1989-1999.
>> + * On-Line Applications Research Corporation (OAR).
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + *
>> + */
>> +
>> +#include <rtems/system.h>
>> +#include <rtems/score/isr.h>
>> +#include <rtems/score/wkspace.h>
>> +#include <bsp/linker-symbols.h>
>> +#include <rtems/score/cpu.h>
>> +
>> +/**
>> + * @brief Performs processor dependent initialization.
>> + */
>> +void _CPU_Initialize(void)
>> +{
>> + /* Do nothing */
>> +}
>> +
>> +/**
>> + * @brief Sets the hardware interrupt level by the level value.
>> + *
>> + * @param[in] level for or1k can only range over two values:
>> + * 0 (enable interrupts) and 1 (disable interrupts). In future
>> + * implementations if fast context switch is implemented, the level
>> + * can range from 0 to 15. @see OpenRISC architecture manual.
>> + *
>> + */
>> +void _CPU_ISR_Set_level(uint32_t level)
>> +{
>> + uint32_t sr = 0;
>> + level = (level > 0)? 1 : 0;
>> +
>> + /* map level bit to or1k interrupt enable/disable bit in sr
>register */
>> + level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> +
>> + if (level == 0){ /* Enable all interrupts */
>> + sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
>> +
>> + } else{
>> + sr &= ~CPU_OR1K_SPR_SR_IEE;
>> + }
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
>> + }
>> +
>> +uint32_t _CPU_ISR_Get_level( void )
>> +{
>> + uint32_t sr = 0;
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> +
>> + return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
>> +}
>> +
>> +void _CPU_ISR_install_raw_handler(
>> + uint32_t vector,
>> + proc_ptr new_handler,
>> + proc_ptr *old_handler
>> +)
>> +{
>> +}
>> +
>> +void _CPU_ISR_install_vector(
>> + uint32_t vector,
>> + proc_ptr new_handler,
>> + proc_ptr *old_handler
>> +)
>> +{
>> + proc_ptr *table =
>> + (proc_ptr *) bsp_start_vector_table_begin;
>> + proc_ptr current_handler;
>> +
>> + ISR_Level level;
>> +
>> + _ISR_Disable( level );
>> +
>> + current_handler = table [vector];
>> +
>> + /* The current handler is now the old one */
>> + if (old_handler != NULL) {
>> + *old_handler = (proc_ptr) current_handler;
>> + }
>> +
>> + /* Write only if necessary to avoid writes to a maybe read-only
>memory */
>> + if (current_handler != new_handler) {
>> + table [vector] = new_handler;
>> + }
>> +
>> + _ISR_Enable( level );
>> +}
>> +
>> +void _CPU_Install_interrupt_stack( void )
>> +{
>> +}
>> +
>> +void _CPU_Thread_Idle_body( void )
>> +{
>> + do {
>> + _OR1K_CPU_Sleep();
>> + } while (1);
>> +}
>> diff --git a/cpukit/score/cpu/or1k/or1k-context-initialize.c
>b/cpukit/score/cpu/or1k/or1k-context-initialize.c
>> new file mode 100644
>> index 0000000..aed0618
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/or1k-context-initialize.c
>> @@ -0,0 +1,43 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * COPYRIGHT (c) 1989-2006
>> + * On-Line Applications Research Corporation (OAR).
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#ifdef HAVE_CONFIG_H
>> + #include "config.h"
>> +#endif
>> +
>> +#include <string.h>
>> +
>> +#include <rtems/score/cpu.h>
>> +#include <rtems/score/interr.h>
>> +#include <rtems/score/or1k-utility.h>
>> +
>> +void _CPU_Context_Initialize(
>> + Context_Control *context,
>> + void *stack_area_begin,
>> + size_t stack_area_size,
>> + uint32_t new_level,
>> + void (*entry_point)( void ),
>> + bool is_fp,
>> + void *tls_area
>> +)
>> +{
>> + uint32_t stack = (uint32_t) stack_area_begin;
>> + uint32_t sr;
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> +
>> + memset(context, 0, sizeof(*context));
>> +
>> + context->r1 = stack;
>> + context->r2 = stack;
>> + context->r9 = (uint32_t) entry_point;
>> + context->sr = sr;
>> +}
>> diff --git a/cpukit/score/cpu/or1k/or1k-context-switch.S
>b/cpukit/score/cpu/or1k/or1k-context-switch.S
>> new file mode 100644
>> index 0000000..fa24c93
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/or1k-context-switch.S
>> @@ -0,0 +1,115 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#ifdef HAVE_CONFIG_H
>> + #include "config.h"
>> +#endif
>> +
>> +#include <rtems/asm.h>
>> +#include "rtems/score/or1k-utility.h"
>> +
>> +.text
>> +.align 4
>> +
>> +PUBLIC(_CPU_Context_switch)
>> +PUBLIC(_CPU_Context_restore)
>> +PUBLIC(_CPU_Context_restore_fp)
>> +PUBLIC(_CPU_Context_save_fp)
>> +
>> +SYM(_CPU_Context_switch):
>> + l.sw 0(r3),r1
>> + l.sw 4(r3),r2
>> + l.sw 8(r3),r3
>> + l.sw 12(r3),r4
>> + l.sw 16(r3),r5
>> + l.sw 20(r3),r6
>> + l.sw 24(r3),r7
>> + l.sw 28(r3),r8
>> + l.sw 32(r3),r9
>> + /* Skip r10 as it's preserved to be used by TLS */
>> + /* The following set if registers are preserved across function
>calls */
>> + l.sw 52(r3),r14
>> + l.sw 60(r3),r16
>> + l.sw 68(r3),r18
>> + l.sw 76(r3),r20
>> + l.sw 84(r3),r22
>> + l.sw 92(r3),r24
>> + l.sw 100(r3),r26
>> + l.sw 108(r3),r28
>> + l.sw 116(r3),r30
>> +
>> + /* Supervision Register */
>> + l.mfspr r13,r0, CPU_OR1K_SPR_SR
>> + l.sw 124(r3),r13
>> +
>> + /* EPCR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
>> + l.sw 128(r3), r13 /* epcr */
>> +
>> + /* EEAR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
>> + l.sw 132(r3), r13 /* eear */
>> +
>> + /* ESR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
>> + l.sw 136(r3), r13 /* esr */
>> +
>> +SYM(restore):
>> + l.lwz r13,124(r4)
>> + l.mtspr r0,r13, CPU_OR1K_SPR_SR
>> +
>> + /* Exception level related registers */
>> +
>> + /* EPCR */
>> + l.lwz r13, 128(r4)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
>> +
>> + /* EEAR */
>> + l.lwz r13, 132(r4)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
>> +
>> + /* ESR */
>> + l.lwz r13, 136(r4)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
>> +
>> + l.lwz r1,0(r4)
>> + l.lwz r2,4(r4)
>> + l.lwz r3,8(r4)
>> + /* Skip r4 as it contains the current buffer address */
>> + l.lwz r5,16(r4)
>> + l.lwz r6,20(r4)
>> + l.lwz r7,24(r4)
>> + l.lwz r8,28(r4)
>> + l.lwz r9,32(r4)
>> + l.lwz r14,52(r4)
>> + l.lwz r16,60(r4)
>> + l.lwz r18,68(r4)
>> + l.lwz r20,76(r4)
>> + l.lwz r22,84(r4)
>> + l.lwz r24,92(r4)
>> + l.lwz r26,100(r4)
>> + l.lwz r28,108(r4)
>> + l.lwz r30,116(r4)
>> +
>> + l.lwz r4,12(r4)
>> +
>> + l.jr r9
>> + l.nop
>> +
>> + SYM(_CPU_Context_restore):
>> + l.add r4,r3,r0
>> + l.add r13,r0,r0
>> + l.j restore
>> + l.nop
>> +
>> + SYM(_CPU_Context_restore_fp):
>> + l.nop
>> +
>> + SYM(_CPU_Context_save_fp):
>> + l.nop
>> +
>> diff --git a/cpukit/score/cpu/or1k/or1k-exception-default.c
>b/cpukit/score/cpu/or1k/or1k-exception-default.c
>> new file mode 100644
>> index 0000000..906822d
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/or1k-exception-default.c
>> @@ -0,0 +1,24 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#ifdef HAVE_CONFIG_H
>> + #include "config.h"
>> +#endif
>> +
>> +#include <rtems/score/cpu.h>
>> +#include <rtems/fatal.h>
>> +#include <bsp/linker-symbols.h>
>> +#include <stdio.h>
>> +
>> +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame
>*frame);
>> +
>> +void _OR1K_Exception_default(uint32_t vector, CPU_Exception_frame
>*frame)
>> +{
>> + rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code)
>frame );
>> +}
>> +
>> diff --git a/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
>b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
>> new file mode 100644
>> index 0000000..75e169c
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/or1k-exception-frame-print.c
>> @@ -0,0 +1,22 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#ifdef HAVE_CONFIG_H
>> + #include "config.h"
>> +#endif
>> +
>> +#include <rtems/score/cpu.h>
>> +#include <rtems/bspIo.h>
>> +
>> +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
>> +{
>> + uint32_t i;
>> + for ( i = 0; i < 32; ++i ) {
>> + printk( "r%02i = 0x%016x\n",i, frame->r[i]);
>> + }
>> +}
>> diff --git a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
>b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
>> new file mode 100644
>> index 0000000..61f7b83
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
>> @@ -0,0 +1,217 @@
>> +/**
>> + * @file
>> + *
>> + * @ingroup ScoreCPU
>> + *
>> + * @brief OR1K exception support implementation.
>> + */
>> +
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + *
>> + */
>> +
>> +#ifdef HAVE_CONFIG_H
>> +#include "config.h"
>> +#endif
>> +
>> +#include <rtems/asm.h>
>> +#include <rtems/score/percpu.h>
>> +#include "rtems/score/or1k-utility.h"
>> +
>> +.align 4
>> +.text
>> +PUBLIC(_ISR_Handler)
>> +.type _ISR_Handler, at function
>> +
>> + SYM(_ISR_Handler):
>> +
>> + l.addi r1, r1, -140
>> +
>> + l.sw 8(r1),r2
>> + /* r3 is saved by BSP exception handler */
>> + l.sw 16(r1),r4
>> + l.sw 20(r1),r5
>> + l.sw 24(r1),r6
>> + l.sw 28(r1),r7
>> + l.sw 32(r1),r8
>> + l.sw 36(r1),r9
>> + l.sw 40(r1),r10
>> + l.sw 44(r1),r11
>> + l.sw 48(r1),r12
>> + l.sw 52(r1),r13
>> + l.sw 56(r1),r14
>> + l.sw 60(r1),r15
>> + l.sw 64(r1),r16
>> + l.sw 68(r1),r17
>> + l.sw 72(r1),r18
>> + l.sw 76(r1),r19
>> + l.sw 80(r1),r20
>> + l.sw 84(r1),r21
>> + l.sw 88(r1),r22
>> + l.sw 92(r1),r23
>> + l.sw 96(r1),r24
>> + l.sw 100(r1),r25
>> + l.sw 104(r1),r26
>> + l.sw 108(r1),r27
>> + l.sw 112(r1),r28
>> + l.sw 116(r1),r29
>> + l.sw 120(r1),r30
>> + l.sw 124(r1),r31
>> +
>> + /* Exception level related registers */
>> +
>> + /* EPCR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
>> + l.sw 128(r1), r13 /* epcr */
>> +
>> + /* EEAR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
>> + l.sw 132(r1), r13 /* eear */
>> +
>> + /* ESR */
>> + l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
>> + l.sw 136(r1), r13 /* esr */
>> +
>> + /* Increment nesting level */
>> + l.movhi r6, hi(ISR_NEST_LEVEL)
>> + l.ori r6, r6, lo(ISR_NEST_LEVEL)
>> +
>> + /* Disable multitasking */
>> + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
>> + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
>> +
>> + l.lwz r5, 0(r6)
>> + l.lwz r7, 0(r8)
>> + l.addi r5, r5, 1
>> + l.addi r7, r7, 1
>> + l.sw 0(r6), r5
>> + l.sw 0(r8), r7
>> +
>> + /* Save interrupted task stack pointer */
>> + l.addi r4, r1, 144
>> + l.sw 4(r1), r4
>> +
>> + /* Save interrupted task r3 (first arg) value */
>> + l.addi r4, r1, 140
>> + l.lwz r4, 0(r4)
>> + l.sw 12(r1), r4
>> +
>> + /* Keep r1 (Exception frame address) in r14 */
>> + l.add r14, r1, r0
>> +
>> + /* Call the exception handler from vector table */
>> +
>> + /* First function arg for C handler is vector number,
>> + * and the second is a pointer to exception frame.
>> + */
>> + l.add r13, r3, r0
>> + l.add r4, r1, r0
>> + l.slli r13, r13, 2
>> + l.addi r13, r13, lo(bsp_start_vector_table_begin)
>> + l.lwz r13, 0(r13)
>> +
>> + /* Do not switch stacks if we are in a nested interrupt. At
>> + * this point r5 should be holding ISR_NEST_LEVEL value.
>> + */
>> + l.sfgtui r5, 2
>> + l.bf jump_to_c_handler
>> + l.nop
>> +
>> + /* Switch to RTEMS dedicated interrupt stack */
>> + l.movhi r1, hi(INTERRUPT_STACK_HIGH)
>> + l.ori r1, r1, lo(INTERRUPT_STACK_HIGH)
>> + l.lwz r1, 0(r1)
>> +
>> +jump_to_c_handler:
>> + l.jalr r13
>> + l.nop
>> +
>> + /* Switch back to the interrupted task stack */
>> + l.add r1, r14, r0
>> +
>> + /* Check if dispatch needed */
>> + l.movhi r31, hi(DISPATCH_NEEDED)
>> + l.ori r31, r31, lo(DISPATCH_NEEDED)
>> + l.lwz r31, 0(r31)
>> + l.sfeq r31, r0
>> + l.bf exception_frame_restore
>> + l.nop
>> +
>> + l.movhi r13, hi(_Thread_Dispatch)
>> + l.ori r13, r13, lo(_Thread_Dispatch)
>> + l.jalr r13
>> + l.nop
>> +
>> + SYM(exception_frame_restore):
>> +
>> + /* Exception level related registers */
>> +
>> + /* EPCR */
>> + l.lwz r13, 128(r1)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
>> +
>> + /* EEAR */
>> + l.lwz r13, 132(r1)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
>> +
>> + /* ESR */
>> + l.lwz r13, 136(r1)
>> + l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
>> +
>> + /* Increment nesting level */
>> + l.movhi r6, hi(ISR_NEST_LEVEL)
>> + l.ori r6, r6, lo(ISR_NEST_LEVEL)
>> +
>> + /* Disable multitasking */
>> + l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
>> + l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
>> +
>> + l.lwz r5, 0(r6)
>> + l.lwz r7, 0(r8)
>> + l.addi r5, r5, -1
>> + l.addi r7, r7, -1
>> + l.sw 0(r6), r5
>> + l.sw 0(r8), r7
>> +
>> + l.lwz r2, 8(r1)
>> + l.lwz r3, 12(r1)
>> + l.lwz r4, 16(r1)
>> + l.lwz r5, 20(r1)
>> + l.lwz r6, 24(r1)
>> + l.lwz r7, 28(r1)
>> + l.lwz r8, 32(r1)
>> + l.lwz r9, 36(r1)
>> + l.lwz r10, 40(r1)
>> + l.lwz r11, 44(r1)
>> + l.lwz r12, 48(r1)
>> + l.lwz r13, 52(r1)
>> + l.lwz r14, 56(r1)
>> + l.lwz r15, 60(r1)
>> + l.lwz r16, 64(r1)
>> + l.lwz r17, 68(r1)
>> + l.lwz r18, 72(r1)
>> + l.lwz r19, 76(r1)
>> + l.lwz r20, 80(r1)
>> + l.lwz r21, 84(r1)
>> + l.lwz r22, 88(r1)
>> + l.lwz r23, 92(r1)
>> + l.lwz r24, 96(r1)
>> + l.lwz r25, 100(r1)
>> + l.lwz r26, 104(r1)
>> + l.lwz r27, 108(r1)
>> + l.lwz r28, 112(r1)
>> + l.lwz r29, 116(r1)
>> + l.lwz r30, 120(r1)
>> +
>> + l.addi r1, r1, 140
>> +
>> + l.addi r1, r1, 4
>> +
>> + l.rfe
>> + l.nop
>> +
>> diff --git a/cpukit/score/cpu/or1k/rtems/asm.h
>b/cpukit/score/cpu/or1k/rtems/asm.h
>> new file mode 100644
>> index 0000000..4d2c226
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/rtems/asm.h
>> @@ -0,0 +1,99 @@
>> +/**
>> + * @file rtems/asm.h
>> + *
>> + * This include file attempts to address the problems
>> + * caused by incompatible flavors of assemblers and
>> + * toolsets. It primarily addresses variations in the
>> + * use of leading underscores on symbols and the requirement
>> + * that register names be preceded by a %.
>> + */
>> +
>> +/*
>> + * NOTE: The spacing in the use of these macros
>> + * is critical to them working as advertised.
>> + *
>> + * COPYRIGHT:
>> + *
>> + * This file is based on similar code found in newlib available
>> + * from ftp.cygnus.com. The file which was used had no copyright
>> + * notice. This file is freely distributable as long as the source
>> + * of the file is noted. This file is:
>> + *
>> + * COPYRIGHT (c) 1994-1997.
>> + * On-Line Applications Research Corporation (OAR).
>> + *
>> + */
>> +
>> +#ifndef __OR1K_ASM_h
>> +#define __OR1K_ASM_h
>> +
>> +/*
>> + * Indicate we are in an assembly file and get the basic CPU
>definitions.
>> + */
>> +
>> +#ifndef ASM
>> +#define ASM
>> +#endif
>> +#include <rtems/score/cpuopts.h>
>> +#include <rtems/score/or1k.h>
>> +
>> +/*
>> + * Recent versions of GNU cpp define variables which indicate the
>> + * need for underscores and percents. If not using GNU cpp or
>> + * the version does not support this, then you will obviously
>> + * have to define these as appropriate.
>> + */
>> +
>> +#ifndef __USER_LABEL_PREFIX__
>> +#define __USER_LABEL_PREFIX__ _
>> +#endif
>> +
>> +#ifndef __REGISTER_PREFIX__
>> +#define __REGISTER_PREFIX__
>> +#endif
>> +
>> +/* ANSI concatenation macros. */
>> +
>> +#define CONCAT1(a, b) CONCAT2(a, b)
>> +#define CONCAT2(a, b) a ## b
>> +
>> +/* Use the right prefix for global labels. */
>> +
>> +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
>> +
>> +/* Use the right prefix for registers. */
>> +
>> +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
>> +
>> +/*
>> + * define macros for all of the registers on this CPU
>> + *
>> + * EXAMPLE: #define d0 REG (d0)
>> + */
>> +
>> +/*
>> + * Define macros to handle section beginning and ends.
>> + */
>> +
>> +
>> +#define BEGIN_CODE_DCL .text
>> +#define END_CODE_DCL
>> +#define BEGIN_DATA_DCL .data
>> +#define END_DATA_DCL
>> +#define BEGIN_CODE .text
>> +#define END_CODE
>> +#define BEGIN_DATA
>> +#define END_DATA
>> +#define BEGIN_BSS
>> +#define END_BSS
>> +#define END
>> +
>> +/*
>> + * Following must be tailor for a particular flavor of the C
>compiler.
>> + * They may need to put underscores in front of the symbols.
>> + */
>> +
>> +#define PUBLIC(sym) .global SYM (sym)
>> +#define EXTERN(sym) .global SYM (sym)
>> +
>> +#endif
>> diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h
>b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>> new file mode 100644
>> index 0000000..72b7089
>> --- /dev/null
>> +++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
>> @@ -0,0 +1,1051 @@
>> +/**
>> + * @file rtems/score/cpu.h
>> + */
>> +
>> +/*
>> + * This include file contains macros pertaining to the Opencores
>> + * or1k processor family.
>> + *
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + * COPYRIGHT (c) 1989-1999.
>> + * On-Line Applications Research Corporation (OAR).
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + *
>> + * This file adapted from no_cpu example of the RTEMS distribution.
>> + * The body has been modified for the Opencores OR1k implementation
>by
>> + * Chris Ziomkowski. <chris at asics.ws>
>> + *
>> + */
>> +
>> +#ifndef _OR1K_CPU_H
>> +#define _OR1K_CPU_H
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +
>> +#include <rtems/score/or1k.h> /* pick up machine
>definitions */
>> +#include <rtems/score/or1k-utility.h>
>> +#include <rtems/score/types.h>
>> +#ifndef ASM
>> +#include <rtems/bspIo.h>
>> +#include <stdint.h>
>> +#include <stdio.h> /* for printk */
>> +#endif
>> +
>> +/* conditional compilation parameters */
>> +
>> +/*
>> + * Should the calls to _Thread_Enable_dispatch be inlined?
>> + *
>> + * If TRUE, then they are inlined.
>> + * If FALSE, then a subroutine call is made.
>> + *
>> + * Basically this is an example of the classic trade-off of size
>> + * versus speed. Inlining the call (TRUE) typically increases the
>> + * size of RTEMS while speeding up the enabling of dispatching.
>> + * [NOTE: In general, the _Thread_Dispatch_disable_level will
>> + * only be 0 or 1 unless you are in an interrupt handler and that
>> + * interrupt handler invokes the executive.] When not inlined
>> + * something calls _Thread_Enable_dispatch which in turns calls
>> + * _Thread_Dispatch. If the enable dispatch is inlined, then
>> + * one subroutine call is avoided entirely.]
>> + *
>> + */
>> +
>> +#define CPU_INLINE_ENABLE_DISPATCH FALSE
>> +
>> +/*
>> + * Should the body of the search loops in
>_Thread_queue_Enqueue_priority
>> + * be unrolled one time? In unrolled each iteration of the loop
>examines
>> + * two "nodes" on the chain being searched. Otherwise, only one
>node
>> + * is examined per iteration.
>> + *
>> + * If TRUE, then the loops are unrolled.
>> + * If FALSE, then the loops are not unrolled.
>> + *
>> + * The primary factor in making this decision is the cost of
>disabling
>> + * and enabling interrupts (_ISR_Flash) versus the cost of rest of
>the
>> + * body of the loop. On some CPUs, the flash is more expensive
>than
>> + * one iteration of the loop body. In this case, it might be
>desirable
>> + * to unroll the loop. It is important to note that on some CPUs,
>this
>> + * code is the longest interrupt disable period in RTEMS. So it is
>> + * necessary to strike a balance when setting this parameter.
>> + *
>> + */
>> +
>> +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
>> +
>> +/*
>> + * Does RTEMS manage a dedicated interrupt stack in software?
>> + *
>> + * If TRUE, then a stack is allocated in
>_ISR_Handler_initialization.
>> + * If FALSE, nothing is done.
>> + *
>> + * If the CPU supports a dedicated interrupt stack in hardware,
>> + * then it is generally the responsibility of the BSP to allocate
>it
>> + * and set it up.
>> + *
>> + * If the CPU does not support a dedicated interrupt stack, then
>> + * the porter has two options: (1) execute interrupts on the
>> + * stack of the interrupted task, and (2) have RTEMS manage a
>dedicated
>> + * interrupt stack.
>> + *
>> + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be
>TRUE.
>> + *
>> + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
>> + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
>> + * possible that both are FALSE for a particular CPU. Although it
>> + * is unclear what that would imply about the interrupt processing
>> + * procedure on that CPU.
>> + *
>> + * Currently, for or1k port, _ISR_Handler is responsible for
>switching to
>> + * RTEMS dedicated interrupt task.
>> + *
>> + */
>> +
>> +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
>> +
>> +/*
>> + * Does this CPU have hardware support for a dedicated interrupt
>stack?
>> + *
>> + * If TRUE, then it must be installed during initialization.
>> + * If FALSE, then no installation is performed.
>> + *
>> + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be
>TRUE.
>> + *
>> + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
>> + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
>> + * possible that both are FALSE for a particular CPU. Although it
>> + * is unclear what that would imply about the interrupt processing
>> + * procedure on that CPU.
>> + *
>> + */
>> +
>> +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
>> +
>> +/*
>> + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt
>Manager?
>> + *
>> + * If TRUE, then the memory is allocated during initialization.
>> + * If FALSE, then the memory is allocated during initialization.
>> + *
>> + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
>> + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
>> + *
>> + */
>> +
>> +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
>> +
>> +/*
>> + * Does the RTEMS invoke the user's ISR with the vector number and
>> + * a pointer to the saved interrupt frame (1) or just the vector
>> + * number (0)?
>> + *
>> + */
>> +
>> +#define CPU_ISR_PASSES_FRAME_POINTER 1
>> +
>> +/*
>> + * Does the CPU have hardware floating point?
>> + *
>> + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is
>supported.
>> + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is
>ignored.
>> + *
>> + * If there is a FP coprocessor such as the i387 or mc68881, then
>> + * the answer is TRUE.
>> + *
>> + * The macro name "OR1K_HAS_FPU" should be made CPU specific.
>> + * It indicates whether or not this CPU model has FP support. For
>> + * example, it would be possible to have an i386_nofp CPU model
>> + * which set this to false to indicate that you have an i386
>without
>> + * an i387 and wish to leave floating point support out of RTEMS.
>> + *
>> + * The CPU_SOFTWARE_FP is used to indicate whether or not there
>> + * is software implemented floating point that must be context
>> + * switched. The determination of whether or not this applies
>> + * is very tool specific and the state saved/restored is also
>> + * compiler specific.
>> + *
>> + * Or1k Specific Information:
>> + *
>> + * At this time there are no implementations of Or1k that are
>> + * expected to implement floating point. More importantly, the
>> + * floating point architecture is expected to change significantly
>> + * before such chips are fabricated.
>> + */
>> +
>> +#define CPU_HARDWARE_FP FALSE
>> +#define CPU_SOFTWARE_FP FALSE
>> +
>> +/*
>> + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
>> + *
>> + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is
>assumed.
>> + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is
>followed.
>> + *
>> + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
>> + *
>> + */
>> +
>> +#define CPU_ALL_TASKS_ARE_FP FALSE
>> +
>> +/*
>> + * Should the IDLE task have a floating point context?
>> + *
>> + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT
>task
>> + * and it has a floating point context which is switched in and
>out.
>> + * If FALSE, then the IDLE task does not have a floating point
>context.
>> + *
>> + * Setting this to TRUE negatively impacts the time required to
>preempt
>> + * the IDLE task from an interrupt because the floating point
>context
>> + * must be saved as part of the preemption.
>> + *
>> + */
>> +
>> +#define CPU_IDLE_TASK_IS_FP FALSE
>> +
>> +/*
>> + * Should the saving of the floating point registers be deferred
>> + * until a context switch is made to another different floating
>point
>> + * task?
>> + *
>> + * If TRUE, then the floating point context will not be stored
>until
>> + * necessary. It will remain in the floating point registers and
>not
>> + * disturned until another floating point task is switched to.
>> + *
>> + * If FALSE, then the floating point context is saved when a
>floating
>> + * point task is switched out and restored when the next floating
>point
>> + * task is restored. The state of the floating point registers
>between
>> + * those two operations is not specified.
>> + *
>> + * If the floating point context does NOT have to be saved as part
>of
>> + * interrupt dispatching, then it should be safe to set this to
>TRUE.
>> + *
>> + * Setting this flag to TRUE results in using a different algorithm
>> + * for deciding when to save and restore the floating point
>context.
>> + * The deferred FP switch algorithm minimizes the number of times
>> + * the FP context is saved and restored. The FP context is not
>saved
>> + * until a context switch is made to another, different FP task.
>> + * Thus in a system with only one FP task, the FP context will
>never
>> + * be saved or restored.
>> + *
>> + */
>> +
>> +#define CPU_USE_DEFERRED_FP_SWITCH TRUE
>> +
>> +/*
>> + * Does this port provide a CPU dependent IDLE task implementation?
>> + *
>> + * If TRUE, then the routine _CPU_Thread_Idle_body
>> + * must be provided and is the default IDLE thread body instead of
>> + * _CPU_Thread_Idle_body.
>> + *
>> + * If FALSE, then use the generic IDLE thread body if the BSP does
>> + * not provide one.
>> + *
>> + * This is intended to allow for supporting processors which have
>> + * a low power or idle mode. When the IDLE thread is executed,
>then
>> + * the CPU can be powered down.
>> + *
>> + * The order of precedence for selecting the IDLE thread body is:
>> + *
>> + * 1. BSP provided
>> + * 2. CPU dependent (if provided)
>> + * 3. generic (if no BSP and no CPU dependent)
>> + *
>> + */
>> +
>> +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
>> +
>> +/*
>> + * Does the stack grow up (toward higher addresses) or down
>> + * (toward lower addresses)?
>> + *
>> + * If TRUE, then the grows upward.
>>
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