[PATCH 1/2] Add or1k tick timer register definitions

[Joel Sherrill]

I committed this. I didn't see anything and if I missed
something, they can just be fixed on top of it.

--joel
On 8/18/2014 4:06 PM, Hesham ALMatary wrote:
> ---
>  cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
> index 74c14d7..6b238b1 100644
> --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
> +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h
> @@ -258,7 +258,21 @@
>  /*Context ID (Fast Context Switching) */
>  #define CPU_OR1K_SPR_SR_CID   (F << CPU_OR1K_SPR_SR_SHAMT_CID)
>  
> +/* Tick timer configuration bits */
> +#define CPU_OR1K_SPR_TTMR_SHAMT_IP    28
> +#define CPU_OR1K_SPR_TTMR_SHAMT_IE    29
> +#define CPU_OR1K_SPR_TTMR_SHAMT_MODE  30
> +
> +#define CPU_OR1K_SPR_TTMR_TP_MASK       (0x0FFFFFFF)
> +#define CPU_OR1K_SPR_TTMR_IP            (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP)
> +#define CPU_OR1K_SPR_TTMR_IE            (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE)
> +#define CPU_OR1K_SPR_TTMR_MODE_RESTART  (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
> +#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
> +#define CPU_OR1K_SPR_TTMR_MODE_CONT     (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
> +
>  /* Power management register bits */
> +
> +/* Shift amount macros for bit positions in Power Management register */
>  #define CPU_OR1K_SPR_PMR_SHAMT_SDF  0
>  #define CPU_OR1K_SPR_PMR_SHAMT_DME  4
>  #define CPU_OR1K_SPR_PMR_SHAMT_SME  5
> @@ -271,8 +285,6 @@
>  #define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE)
>  #define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME)
>  
> -/* Shift amount macros for bit positions in Power Management register */
> -
>  #ifndef ASM
>  
>  #include <stddef.h>

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
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