arm/nds - cache_manager.c build failure

[Gedare Bloom]

On Fri, Aug 22, 2014 at 10:45 AM, Joel Sherrill
<joel.sherrill at oarcorp.com> wrote:
>
> On 8/22/2014 9:38 AM, Gedare Bloom wrote:
>> Looks like this function needs a guard on #if
>> defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
>>
>>
>> see rtems_cache_invalidate_multiple_instruction_lines()
> Or CPU_INSTRUCTION_CACHE_ALIGNMENT needs to be always defined.
> I did a full build of all tests on all BSPs using the latest RSB tools and
> only a couple of BSPs failed this way.
>
The prevailing solution is to put the guard in the code. Your solution
could be proposed, but I'd wait til after release.

>
>> On Fri, Aug 22, 2014 at 10:30 AM, Joel Sherrill
>> <joel.sherrill at oarcorp.com> wrote:
>>> Hi
>>>
>>> I am guessing some conditional path isn't being covered right to
>>> get CPU_INSTRUCTION_CACHE_ALIGNMENT defined. Could
>>> someone please take a look at this and fix it?
>>>
>>> arm-rtems4.11-gcc --pipe -B../../../../../.././lib/
>>> -B../../../../../.././nds/lib/ -specs bsp_specs -qrtems
>>> -DHAVE_CONFIG_H
>>> -I../../../../../../../../rtems/c/src/lib/libbsp/arm/nds/../../shared/include
>>> -mstructure-size-boundary=8 -mcpu=arm9tdmi -mfpu=vfp -mfloat-abi=soft
>>> -mthumb-interwork  -O2 -Wall -Wmissing-prototypes
>>> -Wimplicit-function-declaration -Wstrict-prototypes -Wnested-externs -MT
>>> libbsp_a-cache_manager.o -MD -MP -MF .deps/libbsp_a-cache_manager.Tpo -c
>>> -o libbsp_a-cache_manager.o `test -f
>>> '../../../libcpu/shared/src/cache_manager.c' || echo
>>> '../../../../../../../../rtems/c/src/lib/libbsp/arm/nds/'`../../../libcpu/shared/src/cache_manager.c
>>> ../../../../../../../../rtems/c/src/lib/libbsp/arm/nds/../../../libcpu/shared/src/cache_manager.c:
>>> In function '_invalidate_multiple_instruction_lines_no_range_functions':
>>> ../../../../../../../../rtems/c/src/lib/libbsp/arm/nds/../../../libcpu/shared/src/cache_manager.c:458:40:
>>> error: 'CPU_INSTRUCTION_CACHE_ALIGNMENT' undeclared (first use in this
>>> function)
>>>    i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT
>>> - 1));
>>>                                         ^
>>>
>>> --
>>> Joel Sherrill, Ph.D.             Director of Research & Development
>>> joel.sherrill at OARcorp.com        On-Line Applications Research
>>> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
>>> Support Available                (256) 722-9985
>>>
>>> _______________________________________________
>>> devel mailing list
>>> devel at rtems.org
>>> http://lists.rtems.org/mailman/listinfo/devel
>
> --
> Joel Sherrill, Ph.D.             Director of Research & Development
> joel.sherrill at OARcorp.com        On-Line Applications Research
> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
> Support Available                (256) 722-9985
>