BSP Build Failures Appeal

[Pavel Pisa]

Hello Chris,

On Sunday 24 of August 2014 05:33:45 Chris Johns wrote:
> On 23/08/2014 1:57 am, Joel Sherrill wrote:
> > The build failures I reported were with the latest RSB tools
> > Please pitch in and let's resolve them.
>
> I have a regression build that includes building all BSPs using ...
>
> $ rm -rf build rsb-report-* log_* && ../source-builder/sb-set-builder
> --prefix=$HOME/development/rtems/4.11 --log=log_all_rtems --with-rtems
> --trace --regression 4.11/rtems-all
>
> ... running on sync.rtems.org as I am also seeing failures. This should
> give me a list of error reports with the first failure on an architecture.
>
> > I left a similar build going for the weekend but using the
> > head of gcc, newlib, and binutils. Hopefully the results
> > are similar.
>
> Given the churn GSoC patches are creating I think we are still a while
> away from a freeze before release branching 4.11.

I have fault with latest RTEMS git on 

  tms570ls3137_hdk_intram
  tms570ls3137_hdk_sdram
  arm-lpc17xx_ea_ram
  arm-lpc40xx_ea_ram

I.e. next target

../../../git/rtems/configure --target=arm-rtems4.11 --prefix=/opt/rtems4.11 \
  --enable-rtems-inlines --disable-multiprocessing --enable-cxx \
  --enable-rdbg --enable-maintainer-mode --enable-tests \
  --enable-networking --enable-posix --enable-itron --disable-ada \
  --disable-expada --disable-multilib --disable-docs \
  --enable-rtemsbsp="tms570ls3137_hdk_sdram" \
  CONSOLE_USE_INTERRUPTS=0

Log follows at end of email.

I expect that source of breakage is next commit

  score: Add SMP support to the cache manager
  http://git.rtems.org/rtems/commit/?id=ddbc3f8d83678313ca61d2936e6efd50b3e044b0

and the fact that CPU_INSTRUCTION_CACHE_ALIGNMENT does not get into defines
for the most (or at least these without real cache) of ARM targets.

May it be that some disable of SMP for CPUkit would help to these targets.
But generally I am little afraid if cache management code does not
cause overhead on systems without cache. In the theory there should
be two builds of CPUkit for each multilib variant - one with SMP
and another without if there is expected to build multiple BSPs
against single CPUkit build. As I understand that is used for distribution
but not common for source users who build for single BSP usually.
But should be checked by someone who knows RTEMS better than me.

Best wishes,

              Pavel


arm-rtems4.11-gcc --pipe -B../../../../../.././lib/ -B../../../../../.././lpc40xx_ea_ram/lib/ -specs 
bsp_specs -qrtems -DHAVE_CONFIG_H   -I../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/arm/shared/include   -mthumb -march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mtune=cortex-m4 -O2 -g -Wall -Wmissing-prototypes -Wimplicit-function-declaration -Wstrict-prototypes -Wnested-externs -MT 
libbsp_a-cache_manager.o -MD -MP -MF .deps/libbsp_a-cache_manager.Tpo -c -o libbsp_a-cache_manager.o 
`test -f '../../../libcpu/shared/src/cache_manager.c' || 
echo '../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/'`../../../libcpu/shared/src/cache_manager.c
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c: In 
function '_invalidate_multiple_instruction_lines_no_range_functions':
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:458:40: 
error: 'CPU_INSTRUCTION_CACHE_ALIGNMENT' undeclared (first use in this function)
   i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
                                        ^
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:458:40: note: each undeclared identifier 
is reported only once for each function it appears in
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:460:5: warning: implicit declaration of 
function '_CPU_cache_invalidate_1_instruction_line' [-Wimplicit-function-declaration]
     _CPU_cache_invalidate_1_instruction_line( i_addr );
     ^
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:460:5: warning: nested extern declaration 
of '_CPU_cache_invalidate_1_instruction_line' [-Wnested-externs]
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c: At top level:
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:440:1: 
warning: '_invalidate_multiple_instruction_lines_no_range_functions' defined but not used [-Wunused-function]
 _invalidate_multiple_instruction_lines_no_range_functions(
 ^
makearm-rtems4.11-gcc --pipe -B../../../../../.././lib/ -B../../../../../.././lpc40xx_ea_ram/lib/ -specs 
bsp_specs -qrtems -DHAVE_CONFIG_H   -I../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/arm/shared/include   -mthumb -march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mtune=cortex-m4 -O2 -g -Wall -Wmissing-prototypes -Wimplicit-function-declaration -Wstrict-prototypes -Wnested-externs -MT 
libbsp_a-cache_manager.o -MD -MP -MF .deps/libbsp_a-cache_manager.Tpo -c -o libbsp_a-cache_manager.o 
`test -f '../../../libcpu/shared/src/cache_manager.c' || 
echo '../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/'`../../../libcpu/shared/src/cache_manager.c
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c: In 
function '_invalidate_multiple_instruction_lines_no_range_functions':
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:458:40: 
error: 'CPU_INSTRUCTION_CACHE_ALIGNMENT' undeclared (first use in this function)
   i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
                                        ^
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:458:40: note: each undeclared identifier 
is reported only once for each function it appears in
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:460:5: warning: implicit declaration of 
function '_CPU_cache_invalidate_1_instruction_line' [-Wimplicit-function-declaration]
     _CPU_cache_invalidate_1_instruction_line( i_addr );
     ^
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:460:5: warning: nested extern declaration 
of '_CPU_cache_invalidate_1_instruction_line' [-Wnested-externs]
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c: At top level:
../../../../../../../../../../git/rtems/c/src/lib/libbsp/arm/lpc24xx/../../../libcpu/shared/src/cache_manager.c:440:1: 
warning: '_invalidate_multiple_instruction_lines_no_range_functions' defined but not used [-Wunused-function]
 _invalidate_multiple_instruction_lines_no_range_functions(
 ^
make[6]: *** [libbsp_a-cache_manager.o] Error 1
make[6]: Leaving directory `/home/pi/repo/rtems/build/arm-lpc40xx_ea_ram/rtems/arm-rtems4.11/c/lpc40xx_ea_ram/lib/libbsp/arm/lpc24xx'
[6]: *** [libbsp_a-cache_manager.o] Error 1
make[6]: Leaving directory `/home/pi/repo/rtems/build/arm-lpc40xx_ea_ram/rtems/arm-rtems4.11/c/lpc40xx_ea_ram/lib/libbsp/arm/lpc24xx'