[PATCH 10/17] bsp/arm: Add SCU errata handling for L2C-310 cache

[Ralf Kirchner]

---
 .../libbsp/arm/shared/include/arm-a9mpcore-regs.h  |    5 ++-
 .../libbsp/arm/shared/include/arm-a9mpcore-start.h |   35 ++++++++++++++++----
 2 Dateien geändert, 33 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-)

diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
index 28640d2..861d1ae 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
@@ -58,7 +58,10 @@ typedef struct {
 #define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
 #define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
 #define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
-  uint32_t reserved_10[12];
+  uint32_t reserved_09[8];
+  uint32_t diagn_ctrl;
+#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
+  uint32_t reserved_10[3];
   uint32_t fltstart;
   uint32_t fltend;
   uint32_t reserved_48[2];
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
index ad4cf42..647a4da 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
@@ -30,6 +30,7 @@
 #include <bsp.h>
 #include <bsp/start.h>
 #include <bsp/arm-a9mpcore-regs.h>
+#include <bsp/arm-errata.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,6 +51,19 @@ arm_cp15_set_auxiliary_control(uint32_t val);
 BSP_START_TEXT_SECTION static inline void
 arm_cp15_set_vector_base_address(void *base);
 
+#if ( defined(RTEMS_SMP) )
+  BSP_START_TEXT_SECTION static void inline arm_a9mpcore_start_errata_764369_handler( 
+    volatile a9mpcore_scu *scu 
+  )
+  {
+    if( arm_errata_is_applicable_processor_errata_764369() ) {
+      scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
+    }
+  }
+#else /* #if ( defined(RTEMS_SMP) ) */
+  #define arm_a9mpcore_start_errata_764369_handler( scu )
+#endif /* #if ( defined(RTEMS_SMP) ) */
+
 BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_set_vector_base(void)
 {
   /*
@@ -70,6 +84,12 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_set_vector_base(void)
   }
 }
 
+BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_enable( volatile a9mpcore_scu *scu )
+{
+  arm_a9mpcore_start_errata_764369_handler( scu );
+  scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
+}
+
 BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate(const uint32_t cpu_id, const uint32_t ways)
 {
   volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
@@ -79,23 +99,26 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate(const uin
 
 BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
 {
-#ifdef RTEMS_SMP
   volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
   uint32_t cpu_id;
-  uint32_t actlr;
 
   /* Enable Snoop Control Unit (SCU) */
-  scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
+  arm_a9mpcore_start_scu_enable( scu );
 
+#ifdef RTEMS_SMP
   /* Enable cache coherency support for this processor */
-  actlr = arm_cp15_get_auxiliary_control();
-  actlr |= ARM_CORTEX_A9_ACTL_SMP;
-  arm_cp15_set_auxiliary_control(actlr);
+  {
+    uint32_t actlr = arm_cp15_get_auxiliary_control();
+    actlr |= ARM_CORTEX_A9_ACTL_SMP;
+    arm_cp15_set_auxiliary_control(actlr);
+  }
+#endif
 
   cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
   
   arm_a9mpcore_start_scu_invalidate(cpu_id, 0xF);
   
+#ifdef RTEMS_SMP
   if (cpu_id != 0) {
     arm_a9mpcore_start_set_vector_base();
 
-- 
1.7.10.4