[PATCH] (2 commits squashed into one) Beagle BSP for review

Ben Gras beng at shrike-systems.com
Thu Jul 24 01:00:29 UTC 2014


All,

Full details on how to reproduce all the work from source repositories to
scripts & utilities to write a complete sd card booting RTEMS and test the
whole thing:

http://www.shrike-systems.com/beagleboard-xm-beaglebone-black-and-everything-else-rtems-on-the-beagles.html

I am submitting the attached patch for review for merging. If accepted for
merging, please use the top two commits on

https://github.com/bengras/rtems/tree/beaglebone-wip

which have the same net effect but preserve Claas' work because of the
earlier commit. The squashed version attached is for more convenient review.

I was ironing out more wrinkles but given recent interest it seems smarter
to merge sooner and keep polishing from mainline. Nevertheless I have put a
lot of work into getting it into good shape already.

I have rebased everything on the very latest master and verified

   1. That building all the tools and utilities from scratch work, using
   the RTEMS Source Builder repository (Ubuntu + FreeBSD).
   2. That building the beaglebone and bbxm BSPs and linking them with all
   the testsuite programs works (Ubuntu + FreeBSD).
   3. That the beaglexm-emulating linaro qemu executes all of those tests
   properly, invoked using a single command line with the scripts in the RTEMS
   tools repository, even though not all pass currently (Ubuntu + FreeBSD).
   4. That loading & running over JTAG works, both interactively with gdb
   and in a batch using gdb and the test runner.
   5. That running RTEMS executables using u-boot on the beaglebones from
   sd card work; both with and without MMU enabled at RTEMS start time.
   6. That Claas' earlier commit builds.

Thanks so far to Chris and Brandon for help, support, instructions and
advice in various forms :)

Test results on qemu:
Passed:   497 Failed:     3 Timeouts:   1 Invalid:    0

The test results on bbxm over jtag (older):
Passed:   475 Failed:     7 Timeouts:  10 Invalid:    0

I want to iron out more wrinkles and build support (ethernet) but giving
the bsp more exposure and having it in mainline so i don't have to keep
rebasing & testing would be nice at this point.
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From 70bc9cf5ca04b48e9ddf7c71b1c2dd989bb3a504 Mon Sep 17 00:00:00 2001
From: Ben Gras <beng at shrike-systems.com>
Date: Wed, 22 Aug 2012 14:39:02 +0200
Subject: [PATCH] BSP for several Beagle products

Specifically the beagleboard, beagleboard xM, beaglebone, beaglebone black.

More info on these targets: http://www.beagleboard.org/

    This commit forms a basic BSP by combining Claas's work with
        . new clock and irq code and definitions for
          beagle targets (beagleboard and beaglebones), mostly
          reused from the Minix codebase, thus making
          irqs, ticks and non-polled console mode work too
        . new timer code for ns timing with high timer resolution,
          24MHz on the AM335X and 13MHz on the DM37XX
        . select the console uart based on target at configure time
        . removing all the lpc32xx-specific macros and code and
          other unused code and definitions that the beagle bsp
          was based on
        . re-using some standard functions instead of lpc32xx versions
        . fixed some whitespace problem in preinstall.am
        . fixed some compile warnings
        . configure MMU: set 1MB sections directly in the TTBR,
	  just to show the difference between cacheable RAM and
	  non-cacheable device memory and invalid ranges; this lets us
	  turn on caches and not rely on boot loader MMU configuration.
	  Verified to work when MMU is initially either on or off when
	  RTEMS gets control.

    Signed-Off-By: Ben Gras <beng at shrike-systems.com>
---
 c/src/lib/libbsp/arm/acinclude.m4                  |   2 +
 c/src/lib/libbsp/arm/beagle/Makefile.am            | 131 ++++
 c/src/lib/libbsp/arm/beagle/README                 | 119 +++
 c/src/lib/libbsp/arm/beagle/README.JTAG            |  20 +
 c/src/lib/libbsp/arm/beagle/TESTING                |  21 +
 c/src/lib/libbsp/arm/beagle/TODO                   |  21 +
 c/src/lib/libbsp/arm/beagle/bsp_specs              |  13 +
 c/src/lib/libbsp/arm/beagle/clock.c                | 362 ++++++++++
 c/src/lib/libbsp/arm/beagle/configure.ac           |  37 +
 .../lib/libbsp/arm/beagle/console/console-config.c | 153 ++++
 c/src/lib/libbsp/arm/beagle/include/bsp.h          | 801 +++++++++++++++++++++
 c/src/lib/libbsp/arm/beagle/include/i2c.h          | 368 ++++++++++
 c/src/lib/libbsp/arm/beagle/include/irq.h          |  23 +
 c/src/lib/libbsp/arm/beagle/irq.c                  | 145 ++++
 c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg |   5 +
 c/src/lib/libbsp/arm/beagle/make/custom/beagle.inc |  11 +
 .../arm/beagle/make/custom/beagleboardorig.cfg     |   2 +
 .../arm/beagle/make/custom/beagleboardxm.cfg       |   2 +
 .../arm/beagle/make/custom/beagleboneblack.cfg     |   2 +
 .../arm/beagle/make/custom/beaglebonewhite.cfg     |   2 +
 c/src/lib/libbsp/arm/beagle/misc/i2c.c             | 450 ++++++++++++
 c/src/lib/libbsp/arm/beagle/preinstall.am          | 132 ++++
 c/src/lib/libbsp/arm/beagle/simscripts/bbxm.cfg    | 174 +++++
 .../lib/libbsp/arm/beagle/simscripts/gdbinit.bbxm  |  16 +
 .../arm/beagle/simscripts/qemu-beagleboard.in      |  64 ++
 c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh   |  89 +++
 c/src/lib/libbsp/arm/beagle/startup/bspreset.c     |  42 ++
 c/src/lib/libbsp/arm/beagle/startup/bspstart.c     |  29 +
 .../lib/libbsp/arm/beagle/startup/bspstarthooks.c  |  32 +
 c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c  |  58 ++
 .../lib/libbsp/arm/beagle/startup/linkcmds.beagle  |  46 ++
 c/src/lib/libbsp/bfin/acinclude.m4                 |   4 +-
 c/src/lib/libbsp/powerpc/acinclude.m4              |   4 +-
 33 files changed, 3376 insertions(+), 4 deletions(-)
 create mode 100644 c/src/lib/libbsp/arm/beagle/Makefile.am
 create mode 100644 c/src/lib/libbsp/arm/beagle/README
 create mode 100644 c/src/lib/libbsp/arm/beagle/README.JTAG
 create mode 100644 c/src/lib/libbsp/arm/beagle/TESTING
 create mode 100644 c/src/lib/libbsp/arm/beagle/TODO
 create mode 100644 c/src/lib/libbsp/arm/beagle/bsp_specs
 create mode 100644 c/src/lib/libbsp/arm/beagle/clock.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/configure.ac
 create mode 100644 c/src/lib/libbsp/arm/beagle/console/console-config.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/include/bsp.h
 create mode 100644 c/src/lib/libbsp/arm/beagle/include/i2c.h
 create mode 100644 c/src/lib/libbsp/arm/beagle/include/irq.h
 create mode 100644 c/src/lib/libbsp/arm/beagle/irq.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beagle.inc
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beagleboardorig.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/misc/i2c.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/preinstall.am
 create mode 100644 c/src/lib/libbsp/arm/beagle/simscripts/bbxm.cfg
 create mode 100644 c/src/lib/libbsp/arm/beagle/simscripts/gdbinit.bbxm
 create mode 100644 c/src/lib/libbsp/arm/beagle/simscripts/qemu-beagleboard.in
 create mode 100644 c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
 create mode 100644 c/src/lib/libbsp/arm/beagle/startup/bspreset.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/startup/bspstart.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/startup/bspstarthooks.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
 create mode 100644 c/src/lib/libbsp/arm/beagle/startup/linkcmds.beagle

diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4
index 9192267..24d4e94 100644
--- a/c/src/lib/libbsp/arm/acinclude.m4
+++ b/c/src/lib/libbsp/arm/acinclude.m4
@@ -4,6 +4,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
   case "$1" in
   altera-cyclone-v )
     AC_CONFIG_SUBDIRS([altera-cyclone-v]);;
+  beagle )
+    AC_CONFIG_SUBDIRS([beagle]);;
   csb336 )
     AC_CONFIG_SUBDIRS([csb336]);;
   csb337 )
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am
new file mode 100644
index 0000000..8050b88
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am
@@ -0,0 +1,131 @@
+##
+#
+# @file
+#
+# @brief Makefile of LibBSP for the BeagleBoards.
+#
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+
+include_bspdir = $(includedir)/bsp
+include_libcpudir = $(includedir)/libcpu
+
+dist_project_lib_DATA = bsp_specs
+
+###############################################################################
+#                  Header                                                     #
+###############################################################################
+
+include_HEADERS = include/bsp.h
+include_HEADERS += ../../shared/include/tm27.h
+
+nodist_include_HEADERS = ../../shared/include/coverhd.h \
+  include/bspopts.h
+
+nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
+
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../shared/include/utility.h
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += ../../shared/include/stackalloc.h
+include_bsp_HEADERS += ../../shared/include/uart-output-char.h
+include_bsp_HEADERS += ../../shared/tod.h
+include_bsp_HEADERS += ../shared/include/arm-a8core-start.h
+include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
+include_bsp_HEADERS += ../shared/include/arm-errata.h
+include_bsp_HEADERS += ../shared/include/arm-release-id.h
+include_bsp_HEADERS += ../shared/include/start.h
+include_bsp_HEADERS += include/irq.h
+include_bsp_HEADERS += include/i2c.h
+
+include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
+
+###############################################################################
+#                  Data                                                       #
+###############################################################################
+
+noinst_LIBRARIES = libbspstart.a
+
+libbspstart_a_SOURCES = ../shared/start/start.S
+
+project_lib_DATA = start.$(OBJEXT)
+
+project_lib_DATA += startup/linkcmds
+project_lib_DATA += startup/linkcmds.beagle
+
+EXTRA_DIST = startup/linkcmds.beagle
+
+###############################################################################
+#                  LibBSP                                                     #
+###############################################################################
+
+noinst_LIBRARIES += libbsp.a
+
+libbsp_a_SOURCES =
+libbsp_a_CPPFLAGS =
+libbsp_a_LIBADD =
+
+# Shared
+libbsp_a_SOURCES += ../../shared/bootcard.c
+libbsp_a_SOURCES += ../../shared/bspclean.c
+libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
+libbsp_a_SOURCES += ../../shared/bsplibc.c
+libbsp_a_SOURCES += ../../shared/bsppost.c
+libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
+libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
+libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
+libbsp_a_SOURCES += ../../shared/sbrk.c
+libbsp_a_SOURCES += ../../shared/src/stackalloc.c
+libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
+libbsp_a_SOURCES += ../../shared/timerstub.c
+libbsp_a_SOURCES += ../../shared/cpucounterread.c
+libbsp_a_SOURCES += ../shared/abort/simple_abort.c
+libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
+libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
+
+# Startup
+libbsp_a_SOURCES += startup/bspreset.c
+libbsp_a_SOURCES += startup/bspstart.c
+libbsp_a_SOURCES += startup/bspstarthooks.c
+libbsp_a_SOURCES += startup/bspstartmmu.c
+
+# IRQ
+libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c
+libbsp_a_SOURCES += ../../shared/src/irq-info.c
+libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
+libbsp_a_SOURCES += ../../shared/src/irq-server.c
+libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += irq.c
+
+# Console
+libbsp_a_SOURCES += ../../shared/console.c \
+        ../../shared/console_select.c \
+  console/console-config.c \
+        ../../shared/console_read.c \
+        ../../shared/console_write.c \
+        ../../shared/console_control.c
+
+# I2C
+libbsp_a_SOURCES += misc/i2c.c
+
+# Clock
+libbsp_a_SOURCES += clock.c
+libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
+
+# Cache
+libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+
+###############################################################################
+#                  Special Rules                                              #
+###############################################################################
+
+DISTCLEANFILES = include/bspopts.h
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/arm/beagle/README b/c/src/lib/libbsp/arm/beagle/README
new file mode 100644
index 0000000..abdb176
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/README
@@ -0,0 +1,119 @@
+BSP for beagleboard xm, beaglebone (original aka white), and beaglebone black.
+
+original beagleboard isn't tested.
+
+wiki: http://www.rtems.org/wiki/index.php/Beagleboard
+
+My blog post detailing all the building and using; there is more detail there
+than in this README:
+http://www.shrike-systems.com/beagleboard-xm-beaglebone-black-and-everything-else-rtems-on-the-beagles.html
+
+1.   *** CONFIGURING ************
+
+bsp-specific build options in the environment at build time:
+CONSOLE_POLLED=1 use polled i/o for console, required to run testsuite
+CONSOLE_BAUD=... override default console baud rate
+
+BSPs recognized are:
+beagleboardorig  original beagleboard
+beagleboardxm    beagleboard xm
+beaglebonewhite  original beaglebone
+beagleboneblack  beaglebone black
+
+Currently the only distinction in the BSP are between the beagleboards and
+the beaglebones, but the 4 names are specified in case hardware-specific
+distinctions are made in the future, so this can be done without changing the
+usage.
+
+
+2.   *** BUILDING    ************
+
+To build BSPs for the beaglebone white and beagleboard xm:
+
+$ mkdir b-beagle
+$ cd b-beagle
+$ ../claas-rtems/configure --target=arm-rtems4.11 --enable-rtemsbsp="beaglebonewhite beagleboardxm"
+$ make all
+
+This should give you .exes somewhere.
+
+Then you need 'mkimage' to transform a .exe file to a u-boot image
+file. first make a flat binary:
+
+$ arm-rtems4.11-objcopy $exe -O binary $exe.bin
+$ gzip -9 $exe.bin
+$ mkimage -A arm -O rtems -T kernel -a 0x80000000 -e 0x80000000 -n RTEMS -d $exe.bin.gz rtems-app.img
+
+All beagles have memory starting at 0x80000000 so the load & run syntax is the same.
+
+3.   *** BOOTING     ************
+
+Then, boot the beaglebone with u-boot on an SD card and load rtems-app.img
+from u-boot. Interrupt the u-boot boot to get a prompt.
+
+Set up a tftp server and a network connection for netbooting. And to
+copy rtems-app.img to the tftp dir. Otherwise copy the .img to the FAT
+partition on the SD card and make uboot load & run that.
+
+4.   *** BEAGLEBONES ************
+
+(tested on both beaglebones)
+
+Beaglebone original (white) or beaglebone black netbooting:
+
+uboot# setenv ipaddr 192.168.12.20
+uboot# setenv serverip 192.168.12.10
+uboot# echo starting from TFTP 
+uboot# tftp 0x80800000 rtems-app.img
+uboot# dcache off ; icache off
+uboot# bootm 0x80800000
+
+Beaglebone original (white) or beaglebone black from a FAT partition:
+
+uboot# fatload mmc :1 0x80800000 ticker.img
+uboot# dcache off ; icache off
+uboot# bootm 0x80800000
+
+4.   *** BEAGLEBOARD ************
+
+(tested on xm)
+
+For the beagleboard the necessary commands are a bit different because
+of the ethernet over usb:
+
+uboot# setenv serverip 192.168.12.10
+uboot# setenv ipaddr 192.168.12.62
+uboot# setenv usbnet_devaddr e8:03:9a:24:f9:10
+uboot# setenv usbethaddr e8:03:9a:24:f9:11
+uboot# usb start
+uboot# echo starting from TFTP
+uboot# tftp 0x80800000 rtems-app.img
+uboot# dcache off ; icache off
+uboot# bootm 0x80800000
+
+
+4.   *** SD CARD ****************
+
+There is a script here that automatically writes an SD card for any of
+the beagle targets.
+
+Let's write one for the Beaglebone Black:
+
+    % cd $HOME/development/rtems/rtems-src/c/src/lib/libbsp/arm/beagle/simscripts
+    % sh sdcard.sh $HOME/development/rtems/4.11 $HOME/development/rtems/b-beagle/arm-rtems4.11/c/beagleboneblack/testsuites/samples/hello/hello.exe
+
+The script should give you a whole bunch of output, ending in:
+
+    Result is in bone_hello.exe-sdcard.img.
+
+There you go. dd that to an SD card and boot!
+
+The script needs to know whether it's for a Beagleboard xM or one of
+the Beaglebones. This is to know which uboot to use. It will detect this
+from the path the executable is in, so you have to specify the full path.
+
+
+Good luck & enjoy!
+
+Ben Gras
+beng at shrike-systems.com
diff --git a/c/src/lib/libbsp/arm/beagle/README.JTAG b/c/src/lib/libbsp/arm/beagle/README.JTAG
new file mode 100644
index 0000000..8d30590
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/README.JTAG
@@ -0,0 +1,20 @@
+To run RTEMS from scratch (without any other bootcode) on the beagles,
+you can comfortably load the executables over JTAG using gdb. This is
+necessarily target-specific however.
+
+1. BBXM
+
+  - For access to JTAG using openocd, see simscripts/bbxm.cfg.
+  - openocd then offers access to gdb using simscripts/gdbinit.bbxm.
+  - start openocd using bbxm.cfg
+  - copy your .exe to a new dir and that gdbinit file as .gdbinit in the same dir
+  - go there and start gdb:
+    $ arm-rtems4.11-gdb hello.exe
+  - gdb will invoke the BBXM hardware initialization in the bbxm.cfg
+    and load the ELF over JTAG. type 'c' (for continue) to run it.
+  - breakpoints, C statement and single-instruction stepping work.
+
+2. beaglebone white
+
+This has been tested with openocd and works but not in as much detail as for
+the BBXM yet (i.e. loading an executable from scratch).
diff --git a/c/src/lib/libbsp/arm/beagle/TESTING b/c/src/lib/libbsp/arm/beagle/TESTING
new file mode 100644
index 0000000..d6a367f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/TESTING
@@ -0,0 +1,21 @@
+To build and run the tests for this BSP, use the RTEMS tester.
+The necessary software can be built with the RTEMS source builder.
+
+To build the BSP for testing:
+	- set CONSOLE_POLLED=1 in the configure environment, some tests
+	  assume console i/o is polled
+	- add --enable-tests to the configure line
+
+1. Qemu
+
+Linaro Qemu can emulate the beagleboard xm and so run all regression
+tests in software. Build the bbxm.bset from the RTEMS source builder and
+you will get qemu linaro that can run them. There is a beagleboardxm_qemu
+bsp in the RTEMS tester to invoke it with every test.
+
+2. bbxm hardware
+
+This requires JTAG, see README.JTAG. Use the beagleboardxm bsp in the
+RTEMS tester. It starts gdb to connect to openocd to reset the target
+and load the RTEMS executable for each test iteration.
+
diff --git a/c/src/lib/libbsp/arm/beagle/TODO b/c/src/lib/libbsp/arm/beagle/TODO
new file mode 100644
index 0000000..087b761
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/TODO
@@ -0,0 +1,21 @@
+ . run testsuite
+ . test reset xm and clock xm
+ . waf compatability
+
+verified:
+ . printk, printf, interrupt uart, timer (+nsec), clocks
+ . different Hz
+ . warnings
+ . timer wraparound is ok
+ . reset bbone
+ . i turn caches and mmu on
+ . works when booted with and without mmu on (cache off/on in uboot)
+ . needed vbar; used standard arm_cp15_set_vector_base_address
+ . minimize irq.h
+ . coding conventions, spacing
+ . doxygen
+
+open:
+ . how to handle the interrupt?
+ . uboot env
+ . minimize Makefile.am
diff --git a/c/src/lib/libbsp/arm/beagle/bsp_specs b/c/src/lib/libbsp/arm/beagle/bsp_specs
new file mode 100644
index 0000000..082653a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/bsp_specs
@@ -0,0 +1,13 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
+
+*link:
+%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
+
+*endfile:
+%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s }
diff --git a/c/src/lib/libbsp/arm/beagle/clock.c b/c/src/lib/libbsp/arm/beagle/clock.c
new file mode 100644
index 0000000..d58cb97
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/clock.c
@@ -0,0 +1,362 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Clock driver configuration.
+ */
+
+/*
+ * Copyright (c) 2014 Ben Gras <beng at shrike-systems.com>.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+struct omap_timer_registers;
+
+struct omap_timer
+{
+  uint32_t base;
+  int irq_nr;
+  struct omap_timer_registers *regs;
+};
+
+struct omap_timer_registers
+{
+  uint32_t TIDR;
+  uint32_t TIOCP_CFG;
+  uint32_t TISTAT;
+  uint32_t TISR;
+  uint32_t TIER;
+  uint32_t TWER;
+  uint32_t TCLR;
+  uint32_t TCRR;
+  uint32_t TLDR;
+  uint32_t TTGR;
+  uint32_t TWPS;
+  uint32_t TMAR;
+  uint32_t TCAR1;
+  uint32_t TSICR;
+  uint32_t TCAR2;
+  uint32_t TPIR;
+  uint32_t TNIR;
+  uint32_t TCVR;
+  uint32_t TOCR;
+  uint32_t TOWR;
+
+};
+
+static struct omap_timer_registers regs_v1 = {
+  .TIDR = OMAP3_TIMER_TIDR,
+  .TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG,
+  .TISTAT = OMAP3_TIMER_TISTAT,
+  .TISR = OMAP3_TIMER_TISR,
+  .TIER = OMAP3_TIMER_TIER,
+  .TWER = OMAP3_TIMER_TWER,
+  .TCLR = OMAP3_TIMER_TCLR,
+  .TCRR = OMAP3_TIMER_TCRR,
+  .TLDR = OMAP3_TIMER_TLDR,
+  .TTGR = OMAP3_TIMER_TTGR,
+  .TWPS = OMAP3_TIMER_TWPS,
+  .TMAR = OMAP3_TIMER_TMAR,
+  .TCAR1 = OMAP3_TIMER_TCAR1,
+  .TSICR = OMAP3_TIMER_TSICR,
+  .TCAR2 = OMAP3_TIMER_TCAR2,
+  .TPIR = OMAP3_TIMER_TPIR,
+  .TNIR = OMAP3_TIMER_TNIR,
+  .TCVR = OMAP3_TIMER_TCVR,
+  .TOCR = OMAP3_TIMER_TOCR,
+  .TOWR = OMAP3_TIMER_TOWR,
+};
+
+/* AM335X has a different ip block for the non 1ms timers */
+static struct omap_timer_registers regs_v2 = {
+  .TIDR = AM335X_TIMER_TIDR,
+  .TIOCP_CFG = AM335X_TIMER_TIOCP_CFG,
+  .TISTAT = AM335X_TIMER_IRQSTATUS_RAW,
+  .TISR = AM335X_TIMER_IRQSTATUS,
+  .TIER = AM335X_TIMER_IRQENABLE_SET,
+  .TWER = AM335X_TIMER_IRQWAKEEN,
+  .TCLR = AM335X_TIMER_TCLR,
+  .TCRR = AM335X_TIMER_TCRR,
+  .TLDR = AM335X_TIMER_TLDR,
+  .TTGR = AM335X_TIMER_TTGR,
+  .TWPS = AM335X_TIMER_TWPS,
+  .TMAR = AM335X_TIMER_TMAR,
+  .TCAR1 = AM335X_TIMER_TCAR1,
+  .TSICR = AM335X_TIMER_TSICR,
+  .TCAR2 = AM335X_TIMER_TCAR2,
+  .TPIR = -1,		/* UNDEF */
+  .TNIR = -1,		/* UNDEF */
+  .TCVR = -1,		/* UNDEF */
+  .TOCR = -1,		/* UNDEF */
+  .TOWR = -1		/* UNDEF */
+};
+/* which timers are in use? target-dependent.
+ * initialize at compile time.
+ */
+#if IS_DM3730
+
+static struct omap_timer dm37xx_timer = {
+  .base = OMAP3_GPTIMER1_BASE,
+  .irq_nr = OMAP3_GPT1_IRQ,
+  .regs = &regs_v1
+};
+
+/* free running timer */
+static struct omap_timer dm37xx_fr_timer = {
+  .base = OMAP3_GPTIMER10_BASE,
+  .irq_nr = OMAP3_GPT10_IRQ,
+  .regs = &regs_v1
+};
+
+static struct omap_timer *fr_timer = &dm37xx_fr_timer;
+static struct omap_timer *timer = &dm37xx_timer;
+#endif
+
+#if IS_AM335X
+
+/* normal timer */
+static struct omap_timer am335x_timer = {
+  .base = AM335X_DMTIMER1_1MS_BASE,
+  .irq_nr = AM335X_INT_TINT1_1MS,
+  .regs = &regs_v1
+};
+
+/* free running timer */
+static struct omap_timer am335x_fr_timer = {
+  .base = AM335X_DMTIMER7_BASE,
+  .irq_nr = AM335X_INT_TINT7,
+  .regs = &regs_v2
+};
+
+
+
+static struct omap_timer *fr_timer = &am335x_fr_timer;
+static struct omap_timer *timer = &am335x_timer;
+#endif
+
+static int done = 0;
+
+#if IS_AM335X
+#define FRCLOCK_HZ (16*1500000)
+#endif
+
+#if IS_DM3730
+#define FRCLOCK_HZ (8*1625000)
+#endif
+
+#ifndef FRCLOCK_HZ
+#error expected IS_AM335X or IS_DM3730 to be defined.
+#endif
+
+static void
+omap3_frclock_init(void)
+{
+  uint32_t tisr;
+
+#if IS_DM3730
+  /* Stop timer */
+  mmio_clear(fr_timer->base + fr_timer->regs->TCLR,
+      OMAP3_TCLR_ST);
+
+  /* Use functional clock source for GPTIMER10 */
+  mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
+#endif
+
+#if IS_AM335X
+  /* Disable the module and wait for the module to be disabled */
+  set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,
+      CM_MODULEMODE_DISABLED);
+  while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST)
+      != CM_CLKCTRL_IDLEST_DISABLE);
+
+  set32(CLKSEL_TIMER7_CLK, CLKSEL_TIMER7_CLK_SEL_MASK,
+      CLKSEL_TIMER7_CLK_SEL_SEL2);
+  while ((read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK)
+      != CLKSEL_TIMER7_CLK_SEL_SEL2);
+
+  /* enable the module and wait for the module to be ready */
+  set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,
+      CM_MODULEMODE_ENABLE);
+  while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST)
+      != CM_CLKCTRL_IDLEST_FUNC);
+
+  /* Stop timer */
+  mmio_clear(fr_timer->base + fr_timer->regs->TCLR,
+      OMAP3_TCLR_ST);
+#endif
+
+  /* Start and auto-reload at 0 */
+  mmio_write(fr_timer->base + fr_timer->regs->TLDR, 0x0);
+  mmio_write(fr_timer->base + fr_timer->regs->TCRR, 0x0);
+
+  /* Set up overflow interrupt */
+  tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
+      OMAP3_TISR_TCAR_IT_FLAG;
+  /* Clear interrupt status */
+  mmio_write(fr_timer->base + fr_timer->regs->TISR, tisr);
+  mmio_write(fr_timer->base + fr_timer->regs->TIER,
+      OMAP3_TIER_OVF_IT_ENA);
+
+  /* Start timer, without prescaler */
+  mmio_set(fr_timer->base + fr_timer->regs->TCLR,
+      OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST);
+  done = 1;
+}
+
+static inline uint32_t
+read_frc(void)
+{
+  if (done == 0) {
+    return 0;
+  }
+  return mmio_read(fr_timer->base + fr_timer->regs->TCRR);
+}
+
+static uint32_t last_tick_nanoseconds;
+
+static void
+beagle_clock_initialize(void)
+{
+  uint32_t freq = 1000000UL/rtems_configuration_get_microseconds_per_tick();
+
+  /* we only support 1ms resolution */
+  uint32_t tisr;
+#if IS_DM3730
+  /* Stop timer */
+  mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST);
+
+  /* Use 32 KHz clock source for GPTIMER1 */
+  mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
+#endif
+
+#if IS_AM335X
+  /* disable the module and wait for the module to be disabled */
+  set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,
+      CM_MODULEMODE_DISABLED);
+  while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST)
+      != CM_CLKCTRL_IDLEST_DISABLE);
+
+  set32(CLKSEL_TIMER1MS_CLK, CLKSEL_TIMER1MS_CLK_SEL_MASK,
+      CLKSEL_TIMER1MS_CLK_SEL_SEL2);
+  while ((read32(CLKSEL_TIMER1MS_CLK) &
+    CLKSEL_TIMER1MS_CLK_SEL_MASK) !=
+      CLKSEL_TIMER1MS_CLK_SEL_SEL2);
+
+  /* enable the module and wait for the module to be ready */
+  set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,
+      CM_MODULEMODE_ENABLE);
+  while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST)
+      != CM_CLKCTRL_IDLEST_FUNC);
+
+  /* Stop timer */
+  mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST);
+#endif
+
+  /* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */
+  mmio_write(timer->base + timer->regs->TPIR, 232000);
+  mmio_write(timer->base + timer->regs->TNIR, -768000);
+  mmio_write(timer->base + timer->regs->TLDR,
+      0xffffffff - (32768 / freq) + 1);
+  mmio_write(timer->base + timer->regs->TCRR,
+      0xffffffff - (32768 / freq) + 1);
+
+  /* Set up overflow interrupt */
+  tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
+      OMAP3_TISR_TCAR_IT_FLAG;
+  /* Clear interrupt status */
+  mmio_write(timer->base + timer->regs->TISR, tisr);
+  mmio_write(timer->base + timer->regs->TIER, OMAP3_TIER_OVF_IT_ENA);
+
+  /* Start timer */
+  mmio_set(timer->base + timer->regs->TCLR,
+      OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST);
+  /* also initilize the free runnning timer */
+  omap3_frclock_init();
+}
+
+static void beagle_clock_at_tick(void)
+{
+  uint32_t tisr;
+
+  last_tick_nanoseconds = read_frc();
+
+  mmio_write(timer->base + timer->regs->TISR, 
+    OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
+      OMAP3_TISR_TCAR_IT_FLAG);
+}
+
+static rtems_interrupt_handler clock_isr = NULL;
+
+static void beagle_clock_handler_install(rtems_interrupt_handler isr)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  sc = rtems_interrupt_handler_install(
+    timer->irq_nr,
+    "Clock",
+    RTEMS_INTERRUPT_UNIQUE,
+    isr,
+    NULL
+  );
+
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal_error_occurred(0xdeadbeef);
+  }
+  clock_isr = isr;
+}
+
+static void beagle_clock_cleanup(void)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  /* Disable timer */
+  mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST);
+
+  /* Remove interrupt handler */
+  sc = rtems_interrupt_handler_remove(
+    timer->irq_nr,
+    clock_isr,
+    NULL
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal_error_occurred(0xdeadbeef);
+  }
+  clock_isr = NULL;
+
+  /* stop frclock */
+  mmio_clear(fr_timer->base + fr_timer->regs->TCLR, OMAP3_TCLR_ST);
+}
+
+static inline uint32_t beagle_clock_nanoseconds_since_last_tick(void)
+{
+  /* this arithmetic also works if read_frc() wraps around, as long
+   * as the subtraction wraps around too
+   */
+  return (read_frc() - (uint64_t) last_tick_nanoseconds) * 1000000000 / FRCLOCK_HZ;
+}
+
+#define Clock_driver_support_at_tick() beagle_clock_at_tick()
+#define Clock_driver_support_initialize_hardware() beagle_clock_initialize()
+#define Clock_driver_support_install_isr(isr, old_isr) \
+  do {                   \
+    beagle_clock_handler_install(isr);          \
+    old_isr = NULL;              \
+  } while (0)
+
+#define Clock_driver_support_shutdown_hardware() beagle_clock_cleanup()
+#define Clock_driver_nanoseconds_since_last_tick \
+  beagle_clock_nanoseconds_since_last_tick
+
+/* Include shared source clock driver code */
+#include "../../shared/clockdrv_shell.h"
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/c/src/lib/libbsp/arm/beagle/configure.ac b/c/src/lib/libbsp/arm/beagle/configure.ac
new file mode 100644
index 0000000..a7e99eb
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/configure.ac
@@ -0,0 +1,37 @@
+##
+#
+# @file
+#
+# @brief Configure script of LibBSP for the BeagleBoards.
+#
+
+AC_PREREQ([2.68])
+AC_INIT([rtems-c-src-lib-libbsp-arm-beagle],[_RTEMS_VERSION],[rtems-bugs at rtems.com])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_BSPOPTS_SET([IS_DM3730],[beagleboard*],[1])
+RTEMS_BSPOPTS_HELP([IS_DM3730],[true if SOC is DM3730])
+
+RTEMS_BSPOPTS_SET([IS_AM335X],[beaglebone*],[1])
+RTEMS_BSPOPTS_HELP([IS_AM335X],[true if SOC is AM335X])
+
+RTEMS_BSPOPTS_SET([CONSOLE_BAUD],[*],[115200])
+RTEMS_BSPOPTS_HELP([CONSOLE_BAUD],[initial baud for console UART])
+
+RTEMS_BSPOPTS_SET([CONSOLE_POLLED],[*],[0])
+RTEMS_BSPOPTS_HELP([CONSOLE_POLLED],[polled console i/o (e.g. to run testsuite)])
+
+RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
+RTEMS_BSP_LINKCMDS
+
+AC_CONFIG_FILES([Makefile])
+AC_OUTPUT
diff --git a/c/src/lib/libbsp/arm/beagle/console/console-config.c b/c/src/lib/libbsp/arm/beagle/console/console-config.c
new file mode 100644
index 0000000..63c7ba7
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/console/console-config.c
@@ -0,0 +1,153 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Console configuration.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng at shrike-systems.com> to make
+ * interrupt-driven uart i/o work for beagleboards; beaglebone support added.
+ */
+
+#include <libchip/serial.h>
+#include <libchip/ns16550.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/uart-output-char.h>
+
+#define CONSOLE_UART_THR (*(volatile unsigned int *)BSP_CONSOLE_UART_BASE)
+#define CONSOLE_UART_RHR (*(volatile unsigned int *)BSP_CONSOLE_UART_BASE)
+#define CONSOLE_UART_LSR (*(volatile unsigned int *)(BSP_CONSOLE_UART_BASE+0x14))
+#define CONSOLE_SYSC (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x54))
+#define CONSOLE_SYSS (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x58))
+
+#define TX_FIFO_E (1<<5)
+#define RX_FIFO_E (1<<0)
+
+static uint8_t beagle_uart_get_register(uintptr_t addr, uint8_t i)
+{
+  uint8_t v;
+  volatile uint32_t *reg_r = (volatile uint32_t *) addr + i;
+
+  if(reg_r == (uint32_t*) BSP_CONSOLE_UART_BASE /* reading RHR */ ) {
+    /* check there should be anything in the RHR before accessing it */
+    if(!(CONSOLE_UART_LSR & 0x01)) {
+      return 0;
+    }
+  }
+
+  v = (uint8_t) *reg_r;
+
+  return v;
+}
+
+static void beagle_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
+{
+  volatile uint32_t *reg = (volatile uint32_t *) addr;
+
+  reg [i] = val;
+}
+
+console_tbl Console_Configuration_Ports [] = {
+    {
+      .sDeviceName = "/dev/ttyS0",
+      .deviceType = SERIAL_NS16550,
+#if CONSOLE_POLLED	/* option to facilitate running the tests */
+      .pDeviceFns = &ns16550_fns_polled,
+#else
+      .pDeviceFns = &ns16550_fns,
+#endif
+      .ulMargin = 16,
+      .ulHysteresis = 8,
+      .pDeviceParams = (void *) CONSOLE_BAUD,
+      .ulCtrlPort1 = BSP_CONSOLE_UART_BASE,
+      .ulDataPort = BSP_CONSOLE_UART_BASE,
+      .ulIntVector = BSP_CONSOLE_UART_IRQ,
+      .getRegister = beagle_uart_get_register,
+      .setRegister = beagle_uart_set_register,
+      .ulClock = UART_CLOCK,  /* 48MHz base clock */
+    },
+};
+
+unsigned long Console_Configuration_Count = 1;
+
+static int init_needed = 1; // don't rely on bss being 0
+
+static void beagle_console_init(void)
+{
+  if(init_needed) {
+    const uint32_t div = UART_CLOCK / 16 / CONSOLE_BAUD;
+    CONSOLE_SYSC = 2;
+    while ((CONSOLE_SYSS & 1) == 0)
+      ;
+    if ((CONSOLE_LSR & (CONSOLE_LSR_THRE | CONSOLE_LSR_TEMT)) == CONSOLE_LSR_THRE) {
+      CONSOLE_LCR = 0x83;
+      CONSOLE_DLL = div;
+      CONSOLE_DLM = (div >> 8) & 0xff;
+      CONSOLE_LCR = 0x03;
+      CONSOLE_ACR = 0x00;
+    }
+
+    while ((CONSOLE_LSR & CONSOLE_LSR_TEMT) == 0)
+      ;
+
+    CONSOLE_LCR = 0x80 | 0x03;
+    CONSOLE_DLL = 0x00;
+    CONSOLE_DLM = 0x00;
+    CONSOLE_LCR = 0x03;
+    CONSOLE_MCR = 0x03;
+    CONSOLE_FCR = 0x07;
+    CONSOLE_LCR = 0x83;
+    CONSOLE_DLL = div;
+    CONSOLE_DLM = (div >> 8) & 0xff;
+    CONSOLE_LCR = 0x03;
+    CONSOLE_ACR = 0x00;
+    init_needed = 0;
+  }
+}
+
+#define CONSOLE_THR8 (*(volatile uint8_t *) (BSP_CONSOLE_UART_BASE + 0x00))
+
+static void uart_write_polled( char c )
+{
+  if(init_needed) beagle_console_init();
+
+  while( ( CONSOLE_LSR & TX_FIFO_E ) == 0 )
+    ;
+  CONSOLE_THR8 = c;
+}
+
+static void _BSP_put_char( char c ) {
+   uart_write_polled( c );
+   if (c == '\n') {
+       uart_write_polled('\r');
+   }
+}
+
+static int _BSP_get_char(void)
+{
+  if ((CONSOLE_LSR & CONSOLE_LSR_RDR) != 0) {
+    return CONSOLE_RBR;
+  } else {
+    return -1;
+  }
+}
+
+BSP_output_char_function_type BSP_output_char = _BSP_put_char;
+
+BSP_polling_getchar_function_type BSP_poll_char = _BSP_get_char;
diff --git a/c/src/lib/libbsp/arm/beagle/include/bsp.h b/c/src/lib/libbsp/arm/beagle/include/bsp.h
new file mode 100644
index 0000000..fc001dd1
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/include/bsp.h
@@ -0,0 +1,801 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Global BSP definitions.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng at shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BSP_H
+#define LIBBSP_ARM_BEAGLE_BSP_H
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/start.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+/* UART base clock frequency */
+#define UART_CLOCK     48000000
+
+/* Access memory-mapped I/O devices */
+#define mmio_read(a)    (*(volatile uint32_t *)(a))
+#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
+#define mmio_set(a,v)   mmio_write((a), mmio_read((a)) | (v))
+#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
+
+#define REG16(x)(*((volatile uint16_t *)(x)))
+#define REG(x)(*((volatile uint32_t *)(x)))
+#define BIT(x)(0x1 << x)
+
+#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
+
+/* Write a uint32_t value to a memory address. */
+static inline void
+write32(uint32_t address, uint32_t value)
+{
+  REG(address) = value;
+}
+
+/* Read an uint32_t from a memory address */
+static inline uint32_t
+read32(uint32_t address)
+{
+  return REG(address);
+}
+
+/* Set a 32 bits value depending on a mask */
+static inline void
+set32(uint32_t address, uint32_t mask, uint32_t value)
+{
+  uint32_t val;
+  val = read32(address);
+  /* clear the bits */
+  val &= ~(mask);
+  /* apply the value using the mask */
+  val |= (value & mask);
+  write32(address, val);
+}
+
+/* Write a uint16_t value to a memory address. */
+static inline void
+write16(uint32_t address, uint16_t value)
+{
+  REG16(address) = value;
+}
+
+/* Read an uint16_t from a memory address */
+static inline uint16_t
+read16(uint32_t address)
+{
+  return REG16(address);
+}
+
+/* Data synchronization barrier */
+static inline void dsb(void)
+{
+        asm volatile("dsb" : : : "memory");
+}
+
+/* Instruction synchronization barrier */
+static inline void isb(void)
+{
+        asm volatile("isb" : : : "memory");
+}
+
+/* flush data cache */
+static inline void flush_data_cache(void)
+{
+        asm volatile("mov r0, #0; mcr p15, #0, r0, c7, c10, #4" : : : "memory");
+}
+
+/* Interrupt controller memory map */
+#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+
+/* Interrupt controller memory map */
+#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller registers */
+#define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
+#define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
+#define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
+#define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
+#define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
+#define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
+#define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
+#define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
+#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
+#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
+#define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
+#define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
+#define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
+#define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
+#define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
+#define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
+#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
+#define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
+
+/* SYSCONFIG */
+#define OMAP3_SYSCONFIG_AUTOIDLE	0x01	/* SYSCONFIG.AUTOIDLE bit */
+
+#define OMAP3_INTR_ITR(base,n) \
+    (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR(base,n) \
+    (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_CLEAR(base,n)	\
+    (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_SET(base,n) \
+    (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_SET(base,n) \
+    (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_CLEAR(base,n) \
+    (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_IRQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_FIQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
+#define OMAP3_INTR_ILR(base,m) \
+    (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
+
+#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7f /* Active IRQ mask for SIR_IRQ */
+#define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
+
+
+
+
+#define OMAP3_DM337X_NR_IRQ_VECTORS    96
+
+/* Interrupt mappings */
+#define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
+#define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
+#define OMAP3_SYS_NIRQ       7  /* External source (active low) */
+#define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
+#define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
+#define OMAP3_PRCM_IRQ      11  /* PRCM module */
+#define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
+#define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
+#define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
+#define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
+#define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
+#define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
+#define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
+#define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
+#define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
+#define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
+#define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
+#define OMAP3_DSS_IRQ       25  /* Display subsystem module */
+#define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
+#define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
+#define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
+#define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
+#define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
+#define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
+#define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
+#define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
+#define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
+#define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
+#define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
+#define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
+#define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
+#define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
+#define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
+#define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
+#define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
+#define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
+#define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
+#define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
+#define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
+#define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
+#define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
+#define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
+#define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
+#define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
+#define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
+#define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
+#define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
+#define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
+#define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
+#define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
+#define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
+#define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
+#define OMAP3_UART1_IRQ     72  /* UART module 1 */
+#define OMAP3_UART2_IRQ     73  /* UART module 2 */
+#define OMAP3_UART3_IRQ     74  /* UART module 3 */
+#define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
+#define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
+#define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
+#define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
+#define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
+#define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
+#define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
+#define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
+#define OMAP3_ICR_IRQ       87  /* MPU ICR */
+#define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
+#define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
+#define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
+#define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
+#define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
+#define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
+#define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
+
+
+#define AM335X_INT_EMUINT                         0	/* Emulation interrupt (EMUICINTR) */
+#define AM335X_INT_COMMTX                         1	/* CortexA8 COMMTX */
+#define AM335X_INT_COMMRX                         2	/* CortexA8 COMMRX */
+#define AM335X_INT_BENCH                          3	/* CortexA8 NPMUIRQ */
+#define AM335X_INT_ELM_IRQ                        4	/* Sinterrupt (Error location process completion) */
+#define AM335X_INT_NMI                            7	/* nmi_int */
+#define AM335X_INT_L3DEBUG                        9	/* l3_FlagMux_top_FlagOut1 */
+#define AM335X_INT_L3APPINT                       10	/* l3_FlagMux_top_FlagOut0  */
+#define AM335X_INT_PRCMINT                        11	/* irq_mpu */
+#define AM335X_INT_EDMACOMPINT                    12	/* tpcc_int_pend_po0 */
+#define AM335X_INT_EDMAMPERR                      13	/* tpcc_mpint_pend_po */
+#define AM335X_INT_EDMAERRINT                     14	/* tpcc_errint_pend_po */
+#define AM335X_INT_ADC_TSC_GENINT                 16	/* gen_intr_pend */
+#define AM335X_INT_USBSSINT                       17	/* usbss_intr_pend */
+#define AM335X_INT_USB0                           18	/* usb0_intr_pend */
+#define AM335X_INT_USB1                           19	/* usb1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT0                 20	/* pr1_host_intr0_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT1                 21	/* pr1_host_intr1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT2                 22	/* pr1_host_intr2_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT3                 23	/* pr1_host_intr3_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT4                 24	/* pr1_host_intr4_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT5                 25	/* pr1_host_intr5_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT6                 26	/* pr1_host_intr6_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT7                 27	/* pr1_host_intr7_intr_pend */
+#define AM335X_INT_MMCSD1INT                      28	/* MMCSD1  SINTERRUPTN */
+#define AM335X_INT_MMCSD2INT                      29	/* MMCSD2  SINTERRUPT */
+#define AM335X_INT_I2C2INT                        30	/* I2C2  POINTRPEND */
+#define AM335X_INT_eCAP0INT                       31	/* ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT2A                      32	/* GPIO 2  POINTRPEND1 */
+#define AM335X_INT_GPIOINT2B                      33	/* GPIO 2  POINTRPEND2 */
+#define AM335X_INT_USBWAKEUP                      34	/* USBSS  slv0p_Swakeup */
+#define AM335X_INT_LCDCINT                        36	/* LCDC  lcd_irq */
+#define AM335X_INT_GFXINT                         37	/* SGX530  THALIAIRQ */
+#define AM335X_INT_ePWM2INT                       39	/* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_3PGSWRXTHR0                    40	/* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
+#define AM335X_INT_3PGSWRXINT0                    41	/* CPSW (Ethernet)  c0_rx_pend */
+#define AM335X_INT_3PGSWTXINT0                    42	/* CPSW (Ethernet)  c0_tx_pend */
+#define AM335X_INT_3PGSWMISC0                     43	/* CPSW (Ethernet)  c0_misc_pend */
+#define AM335X_INT_UART3INT                       44	/* UART3  niq */
+#define AM335X_INT_UART4INT                       45	/* UART4  niq */
+#define AM335X_INT_UART5INT                       46	/* UART5  niq */
+#define AM335X_INT_eCAP1INT                       47	/* (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_DCAN0_INT0                     52	/* DCAN0  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN0_INT1                     53	/* DCAN0  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN0_PARITY                   54	/* DCAN0  dcan_uerr_intr_pend */
+#define AM335X_INT_DCAN1_INT0                     55	/* DCAN1  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN1_INT1                     56	/* DCAN1  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN1_PARITY                   57	/* DCAN1  dcan_uerr_intr_pend */
+#define AM335X_INT_ePWM0_TZINT                    58	/* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM1_TZINT                    59	/* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM2_TZINT                    60	/* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_eCAP2INT                       61	/* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT3A                      62	/* GPIO 3  POINTRPEND1 */
+#define AM335X_INT_GPIOINT3B                      63	/* GPIO 3  POINTRPEND2 */
+#define AM335X_INT_MMCSD0INT                      64	/* MMCSD0  SINTERRUPTN */
+#define AM335X_INT_SPI0INT                        65	/* McSPI0  SINTERRUPTN */
+#define AM335X_INT_TINT0                          66	/* Timer0  POINTR_PEND */
+#define AM335X_INT_TINT1_1MS                      67	/* DMTIMER_1ms  POINTR_PEND */
+#define AM335X_INT_TINT2                          68	/* DMTIMER2  POINTR_PEND */
+#define AM335X_INT_TINT3                          69	/* DMTIMER3  POINTR_PEND */
+#define AM335X_INT_I2C0INT                        70	/* I2C0  POINTRPEND */
+#define AM335X_INT_I2C1INT                        71	/* I2C1  POINTRPEND */
+#define AM335X_INT_UART0INT                       72	/* UART0  niq */
+#define AM335X_INT_UART1INT                       73	/* UART1  niq */
+#define AM335X_INT_UART2INT                       74	/* UART2  niq */
+#define AM335X_INT_RTCINT                         75	/* RTC  timer_intr_pend */
+#define AM335X_INT_RTCALARMINT                    76	/* RTC  alarm_intr_pend */
+#define AM335X_INT_MBINT0                         77	/* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
+#define AM335X_INT_M3_TXEV                        78	/* Wake M3 Subsystem  TXEV */
+#define AM335X_INT_eQEP0INT                       79	/* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_MCATXINT0                      80	/* McASP0  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT0                      81	/* McASP0  mcasp_r_intr_pend */
+#define AM335X_INT_MCATXINT1                      82	/* McASP1  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT1                      83	/* McASP1  mcasp_r_intr_pend */
+#define AM335X_INT_ePWM0INT                       86	/* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_ePWM1INT                       87	/* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_eQEP1INT                       88	/* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_eQEP2INT                       89	/* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_DMA_INTR_PIN2                  90	/* External DMA/Interrupt Pin2  pi_x_dma_event_intr2 (xdma_event_intr2) */
+#define AM335X_INT_WDT1INT                        91	/* (Public Watchdog)  WDTIMER1  PO_INT_PEND */
+#define AM335X_INT_TINT4                          92	/* DMTIMER4  POINTR_PEN */
+#define AM335X_INT_TINT5                          93	/* DMTIMER5  POINTR_PEN */
+#define AM335X_INT_TINT6                          94	/* DMTIMER6  POINTR_PEND */
+#define AM335X_INT_TINT7                          95	/* DMTIMER7  POINTR_PEND */
+#define AM335X_INT_GPIOINT0A                      96	/* GPIO 0  POINTRPEND1 */
+#define AM335X_INT_GPIOINT0B                      97	/* GPIO 0  POINTRPEND2 */
+#define AM335X_INT_GPIOINT1A                      98	/* GPIO 1  POINTRPEND1 */
+#define AM335X_INT_GPIOINT1B                      99	/* GPIO 1  POINTRPEND2 */
+#define AM335X_INT_GPMCINT                        100	/* GPMC  gpmc_sinterrupt */
+#define AM335X_INT_DDRERR0                        101	/* EMIF  sys_err_intr_pend */
+#define AM335X_INT_TCERRINT0                      112	/* TPTC0  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT1                      113	/* TPTC1  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT2                      114	/* TPTC2  tptc_erint_pend_po */
+#define AM335X_INT_ADC_TSC_PENINT                 115	/* ADC_TSC  pen_intr_pend */
+#define AM335X_INT_SMRFLX_Sabertooth              120	/* Smart Reflex 0  intrpen */
+#define AM335X_INT_SMRFLX_Core                    121	/* Smart Reflex 1  intrpend */
+#define AM335X_INT_DMA_INTR_PIN0                  123	/* pi_x_dma_event_intr0 (xdma_event_intr0) */
+#define AM335X_INT_DMA_INTR_PIN1                  124	/* pi_x_dma_event_intr1 (xdma_event_intr1) */
+#define AM335X_INT_SPI1INT                        125	/* McSPI1  SINTERRUPTN */
+
+#define OMAP3_AM335X_NR_IRQ_VECTORS    125
+
+/* General-purpose timer register map */
+#define OMAP3_GPTIMER1_BASE  0x48318000 /* GPTIMER1 physical address */
+#define OMAP3_GPTIMER2_BASE  0x49032000 /* GPTIMER2 physical address */
+#define OMAP3_GPTIMER3_BASE  0x49034000 /* GPTIMER3 physical address */
+#define OMAP3_GPTIMER4_BASE  0x49036000 /* GPTIMER4 physical address */
+#define OMAP3_GPTIMER5_BASE  0x49038000 /* GPTIMER5 physical address */
+#define OMAP3_GPTIMER6_BASE  0x4903A000 /* GPTIMER6 physical address */
+#define OMAP3_GPTIMER7_BASE  0x4903C000 /* GPTIMER7 physical address */
+#define OMAP3_GPTIMER8_BASE  0x4903E000 /* GPTIMER8 physical address */
+#define OMAP3_GPTIMER9_BASE  0x49040000 /* GPTIMER9 physical address */
+#define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */
+#define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */
+
+
+/* General-purpose timer registers */
+#define OMAP3_TIMER_TIDR      0x000 /* IP revision code */
+#define OMAP3_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */
+#define OMAP3_TIMER_TISTAT    0x014 /* Status (excl. interrupt status) */
+#define OMAP3_TIMER_TISR      0x018 /* Pending interrupt status */
+#define OMAP3_TIMER_TIER      0x01C /* Interrupt enable */
+#define OMAP3_TIMER_TWER      0x020 /* Wakeup enable */
+#define OMAP3_TIMER_TCLR      0x024 /* Controls optional features */
+#define OMAP3_TIMER_TCRR      0x028 /* Internal counter value */
+#define OMAP3_TIMER_TLDR      0x02C /* Timer load value */
+#define OMAP3_TIMER_TTGR      0x030 /* Triggers counter reload */
+#define OMAP3_TIMER_TWPS      0x034 /* Indicates if Write-Posted pending */
+#define OMAP3_TIMER_TMAR      0x038 /* Value to be compared with counter */
+#define OMAP3_TIMER_TCAR1     0x03C /* First captured value of counter register */
+#define OMAP3_TIMER_TSICR     0x040 /* Control posted mode and functional SW reset */
+#define OMAP3_TIMER_TCAR2     0x044 /* Second captured value of counter register */
+#define OMAP3_TIMER_TPIR      0x048 /* Positive increment (1 ms tick) */
+#define OMAP3_TIMER_TNIR      0x04C /* Negative increment (1 ms tick) */
+#define OMAP3_TIMER_TCVR      0x050 /* Defines TCRR is sub/over-period (1 ms tick) */
+#define OMAP3_TIMER_TOCR      0x054 /* Masks tick interrupt */
+#define OMAP3_TIMER_TOWR      0x058 /* Number of masked overflow interrupts */
+
+#define AM335X_DMTIMER0_BASE      0x44E05000  /* DMTimer0 Registers */
+#define AM335X_DMTIMER1_1MS_BASE  0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */
+#define AM335X_DMTIMER2_BASE      0x48040000 /*  DMTimer2 Registers */
+#define AM335X_DMTIMER3_BASE      0x48042000 /*  DMTimer3 Registers */
+#define AM335X_DMTIMER4_BASE      0x48044000 /* DMTimer4 Registers  */
+#define AM335X_DMTIMER5_BASE      0x48046000 /* DMTimer5 Registers  */
+#define AM335X_DMTIMER6_BASE      0x48048000 /*  DMTimer6 Registers */
+#define AM335X_DMTIMER7_BASE      0x4804A000 /*  DMTimer7 Registers */
+
+/* General-purpose timer registers  AM335x non 1MS timers have different offsets */
+#define AM335X_TIMER_TIDR             0x000 /* IP revision code */
+#define AM335X_TIMER_TIOCP_CFG        0x010 /* Controls params for GP timer L4 interface */
+#define AM335X_TIMER_IRQSTATUS_RAW    0x024 /* Timer IRQSTATUS Raw Register */
+#define AM335X_TIMER_IRQSTATUS        0x028 /* Timer IRQSTATUS Register */
+#define AM335X_TIMER_IRQENABLE_SET    0x02C /* Timer IRQENABLE Set Register */
+#define AM335X_TIMER_IRQENABLE_CLR    0x030 /* Timer IRQENABLE Clear Register */
+#define AM335X_TIMER_IRQWAKEEN        0x034 /* Timer IRQ Wakeup Enable Register */
+#define AM335X_TIMER_TCLR      0x038 /* Controls optional features */
+#define AM335X_TIMER_TCRR      0x03C /* Internal counter value */
+#define AM335X_TIMER_TLDR      0x040 /* Timer load value */
+#define AM335X_TIMER_TTGR      0x044 /* Triggers counter reload */
+#define AM335X_TIMER_TWPS      0x048 /* Indicates if Write-Posted pending */
+#define AM335X_TIMER_TMAR      0x04C /* Value to be compared with counter */
+#define AM335X_TIMER_TCAR1     0x050 /* First captured value of counter register */
+#define AM335X_TIMER_TSICR     0x054 /* Control posted mode and functional SW reset */
+#define AM335X_TIMER_TCAR2     0x058 /* Second captured value of counter register */
+
+
+
+/* Interrupt status register fields */
+#define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
+#define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
+#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
+
+/* Interrupt enable register fields */
+#define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
+#define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
+#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
+
+/* Timer control fields */
+#define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
+#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
+#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
+#define OMAP3_TCLR_PTV      2
+#define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
+
+
+#define OMAP3_CM_CLKSEL_GFX		0x48004b40
+#define OMAP3_CM_CLKEN_PLL		0x48004d00
+#define OMAP3_CM_FCLKEN1_CORE	0x48004A00
+#define OMAP3_CM_CLKSEL_CORE	0x48004A40 /* GPT10 src clock sel. */
+#define OMAP3_CM_FCLKEN_PER		0x48005000
+#define OMAP3_CM_CLKSEL_PER		0x48005040
+#define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
+
+
+#define CM_MODULEMODE_MASK (0x3 << 0)
+#define CM_MODULEMODE_ENABLE      (0x2 << 0)
+#define CM_MODULEMODE_DISABLED     (0x0 << 0)
+
+#define CM_CLKCTRL_IDLEST         (0x3 << 16)
+#define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
+#define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
+#define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
+#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
+
+#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
+
+#define CM_WKUP_TIMER1_CLKCTRL	(CM_WKUP_BASE + 0xC4) /* This register manages the TIMER1 clocks. [Memory Mapped] */
+
+
+#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
+#define CM_PER_TIMER7_CLKCTRL	(CM_PER_BASE + 0x7C) /* This register manages the TIMER7 clocks. [Memory Mapped] */
+
+
+
+/* CM_DPLL registers */
+
+
+#define CM_DPLL_BASE 	0x44E00500 /* Clock Module PLL Registers */
+
+#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
+
+
+#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) /* Select TCLKIN clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) /* Select CLK_RC32K clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) /* Selects the CLK_32768 from 32KHz Crystal Osc */
+
+#define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
+#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
+#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
+
+
+
+
+#define OMAP3_CLKSEL_GPT1    (1 << 0)
+#define OMAP3_CLKSEL_GPT10    (1 << 6)
+#define OMAP3_CLKSEL_GPT11    (1 << 7)
+
+
+#define TIMER_FREQ  1000    /* clock frequency for OMAP timer (1ms) */
+#define TIMER_COUNT(freq) (TIMER_FREQ/(freq)) /* initial value for counter*/
+
+#define __arch_getb(a)      (*(volatile unsigned char *)(a))
+#define __arch_getw(a)      (*(volatile unsigned short *)(a))
+#define __arch_getl(a)      (*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
+
+#define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
+#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
+#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
+
+#define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
+#define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
+#define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
+
+#define SYSTEM_CLOCK_12       12000000
+#define SYSTEM_CLOCK_13       13000000
+#define SYSTEM_CLOCK_192      19200000
+#define SYSTEM_CLOCK_96       96000000
+
+#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
+
+#if !defined(IS_DM3730) && !defined(IS_AM335X)
+#error Unrecognized BSP configured.
+#endif
+
+#if IS_DM3730
+#define BSP_DEVICEMEM_START	0x48000000
+#define BSP_DEVICEMEM_END	0x5F000000
+#endif
+
+#if IS_AM335X
+#define BSP_DEVICEMEM_START	0x44000000
+#define BSP_DEVICEMEM_END	0x57000000
+#endif
+
+/* per-target uart config */
+#if IS_AM335X
+#define BSP_CONSOLE_UART	1
+#define BSP_CONSOLE_UART_BASE	BEAGLE_BASE_UART_1
+#define BSP_CONSOLE_UART_IRQ	OMAP3_UART1_IRQ
+#define BEAGLE_BASE_UART_1	0x44E09000
+#define BEAGLE_BASE_UART_2	0x48022000
+#define BEAGLE_BASE_UART_3	0x48024000
+#endif
+
+/* per-target uart config */
+#if IS_DM3730
+#define BSP_CONSOLE_UART	3
+#define BSP_CONSOLE_UART_BASE	BEAGLE_BASE_UART_3
+#define BSP_CONSOLE_UART_IRQ	OMAP3_UART3_IRQ
+#define BEAGLE_BASE_UART_1	0x4806A000
+#define BEAGLE_BASE_UART_2	0x4806C000
+#define BEAGLE_BASE_UART_3	0x49020000
+#endif
+
+/* i2c stuff */
+typedef struct {
+  uint32_t rx_or_tx;
+  uint32_t stat;
+  uint32_t ctrl;
+  uint32_t clk_hi;
+  uint32_t clk_lo;
+  uint32_t adr;
+  uint32_t rxfl;
+  uint32_t txfl;
+  uint32_t rxb;
+  uint32_t txb;
+  uint32_t s_tx;
+  uint32_t s_txfl;
+} beagle_i2c;
+
+/* sctlr */
+/* Read System Control Register */
+static inline uint32_t read_sctlr()
+{
+  uint32_t ctl;
+
+  asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+    : [ctl] "=r" (ctl));
+
+  return ctl;
+}
+
+/* Write System Control Register */
+static inline void write_sctlr(uint32_t ctl)
+{
+  asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+    : : [ctl] "r" (ctl));
+  isb();
+}
+
+/* Read Auxiliary Control Register */
+static inline uint32_t read_actlr()
+{
+  uint32_t ctl;
+
+       	asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+       		: [ctl] "=r" (ctl));
+
+       	return ctl;
+}
+
+/* Write Auxiliary Control Register */
+static inline void write_actlr(uint32_t ctl)
+{
+  asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+    : : [ctl] "r" (ctl));
+
+       	isb();
+}
+
+/* Write Translation Table Base Control Register */
+static inline void write_ttbcr(uint32_t bcr)
+{
+        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
+                        : : [bcr] "r" (bcr));
+
+        isb();
+}
+
+/* Read Domain Access Control Register */
+static inline uint32_t read_dacr()
+{
+        uint32_t dacr;
+
+        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
+                        : [dacr] "=r" (dacr));
+
+        return dacr;
+}
+
+
+/* Write Domain Access Control Register */
+static inline void write_dacr(uint32_t dacr)
+{
+        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
+                        : : [dacr] "r" (dacr));
+
+        isb();
+}
+
+#define ARM_TTBR_ADDR_MASK (0xffffc000)
+#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
+#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
+#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
+#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
+#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
+
+static inline void refresh_tlb(void)
+{
+        dsb();
+
+        /* Invalidate entire unified TLB */
+        asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" : : [zero] "r" (0));
+
+#if 0
+        /* Invalidate entire data TLB */
+        asm volatile("mcr p15, 0, %[zero], c8, c6, 0" : : [zero] "r" (0));
+
+        /* Invalidate entire instruction TLB */
+        asm volatile("mcr p15, 0, %[zero], c8, c5, 0" : : [zero] "r" (0));
+#endif
+
+        /*
+         * Invalidate all instruction caches to PoU.
+         * Also flushes branch target cache.
+         */
+        asm volatile("mcr p15, 0, %[zero], c7, c5, 0" : : [zero] "r" (0));
+
+        /* Invalidate entire branch predictor array */
+        asm volatile("mcr p15, 0, %[zero], c7, c5, 6" : : [zero] "r" (0)); /* flush BTB */
+
+        dsb();
+        isb();
+}
+
+/* Read Translation Table Base Register 0 */
+static inline uint32_t read_ttbr0()
+{
+        uint32_t bar;
+
+        asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+                        : [bar] "=r" (bar));
+
+        return bar & ARM_TTBR_ADDR_MASK;
+}
+
+
+/* Read Translation Table Base Register 0 */
+static inline uint32_t read_ttbr0_unmasked()
+{
+        uint32_t bar;
+
+        asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+                        : [bar] "=r" (bar));
+
+        return bar;
+}
+
+/* Write Translation Table Base Register 0 */
+static inline void write_ttbr0(uint32_t bar)
+{
+        dsb();
+        isb();
+        /* In our setup TTBR contains the base address *and* the flags
+           but other pieces of the kernel code expect ttbr to be the
+           base address of the l1 page table. We therefore add the
+           flags here and remove them in the read_ttbr0 */
+        uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
+        asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+                        : : [bar] "r" (v));
+
+        refresh_tlb();
+}
+
+/* cpu control flags */
+/* CPU control register (CP15 register 1) */
+#define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
+#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
+#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
+#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
+#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
+#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
+#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
+#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
+#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
+#define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
+#define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
+#define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
+#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
+#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
+#define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
+#define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
+#define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
+#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
+#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
+#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
+#define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
+#define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
+#define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
+#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
+#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
+#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
+
+#define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
+
+/* VM bits */
+/* Big page (1MB section) specific flags. */
+#define ARM_VM_SECTION                  (1 << 1)  /* 1MB section */
+#define ARM_VM_SECTION_PRESENT          (1 << 1)  /* Section is present */
+#define ARM_VM_SECTION_B                (1 << 2)  /* B Bit */
+#define ARM_VM_SECTION_C                (1 << 3)  /* C Bit */
+#define ARM_VM_SECTION_DOMAIN           (0xF << 5) /* Domain Number */
+#define ARM_VM_SECTION_SUPER            (0x1 << 10) /* Super access only AP[1:0] */
+#define ARM_VM_SECTION_USER             (0x3 << 10) /* Super/User access AP[1:0] */
+#define ARM_VM_SECTION_TEX0             (1 << 12) /* TEX[0] */
+#define ARM_VM_SECTION_TEX1             (1 << 13) /* TEX[1] */
+#define ARM_VM_SECTION_TEX2             (1 << 14) /* TEX[2] */
+#define ARM_VM_SECTION_RO               (1 << 15)   /* Read only access AP[2] */
+#define ARM_VM_SECTION_SHAREABLE        (1 << 16)  /* Shareable */
+#define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)  /* Not Global */
+
+/* inner and outer write-back, write-allocate */
+#define ARM_VM_SECTION_WB       (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
+/* inner and outer write-through, no write-allocate */
+#define ARM_VM_SECTION_WT       (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
+/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
+#define ARM_VM_SECTION_WTWB     (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
+/* shareable device */
+
+#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB
+
+#define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)
+
+/* Behaviour on fatal error; default: test-friendly.
+ * set breakpoint to bsp_fatal_extension.
+ */
+/* don't do this to allow tests to fail noninteractively */
+/* #define BSP_PRESS_KEY_FOR_RESET	1 */ 
+#define BSP_PRINT_EXCEPTION_CONTEXT 1	/* human-readable exception info */
+#define BSP_RESET_BOARD_AT_EXIT 1	/* causes qemu to exit, signaling end of test */
+
+
+/**
+ * @defgroup arm_beagle Beaglebone, Beagleboard Support
+ *
+ * @ingroup bsp_arm
+ *
+ * @brief Beaglebones and beagleboards support package
+ *
+ */
+
+/**
+ * @brief Beagleboard specific set up of the MMU.
+ *
+ * Provide in the application to override.
+ */
+BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
+
+#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
diff --git a/c/src/lib/libbsp/arm/beagle/include/i2c.h b/c/src/lib/libbsp/arm/beagle/include/i2c.h
new file mode 100644
index 0000000..dbd066a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/include/i2c.h
@@ -0,0 +1,368 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief I2C support API.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_I2C_H
+#define LIBBSP_ARM_BEAGLE_I2C_H
+
+#include <rtems.h>
+
+#include <bsp.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN  (1 << 15)  /* I2C module enable */
+#define I2C_CON_BE  (1 << 14)  /* Big endian mode */
+#define I2C_CON_STB (1 << 11)  /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10)  /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9)   /* Transmitter/receiver mode */
+           /* (master mode only) */
+#define I2C_CON_XA  (1 << 8)   /* Expand address */
+#define I2C_CON_STP (1 << 1)   /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0)   /* Start condition (master mode only) */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD  (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS  (1 << 9)  /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4)  /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3)  /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2)  /* Register access ready */
+#define I2C_STAT_NACK (1 << 1)  /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0)  /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE  (1 << 5)
+#define I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE  (1 << 0) /* Arbitration lost interrupt enable */
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM   6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM   6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE  400000
+#define OMAP_I2C_HIGH_SPEED 3400000
+
+
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK    SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+#define I2C_PSC_MAX   0x0f
+#define I2C_PSC_MIN   0x00
+
+
+#define DISP_LINE_LEN 128
+#define I2C_TIMEOUT 1000
+
+#define I2C_BUS_MAX 3
+
+#define I2C_BASE1         (OMAP34XX_CORE_L4_IO_BASE + 0x070000)
+
+#define I2C_DEFAULT_BASE      I2C_BASE1
+
+#define I2C_SYSS_RDONE            (1 << 0)  /* Internel reset monitoring */
+
+#define CONFIG_SYS_I2C_SPEED    100000
+#define CONFIG_SYS_I2C_SLAVE    1
+
+struct i2c {
+  unsigned short rev;   /* 0x00 */
+  unsigned short res1;
+  unsigned short ie;    /* 0x04 */
+  unsigned short res2;
+  unsigned short stat;  /* 0x08 */
+  unsigned short res3;
+  unsigned short iv;    /* 0x0C */
+  unsigned short res4;
+  unsigned short syss;  /* 0x10 */
+  unsigned short res4a;
+  unsigned short buf;   /* 0x14 */
+  unsigned short res5;
+  unsigned short cnt;   /* 0x18 */
+  unsigned short res6;
+  unsigned short data;  /* 0x1C */
+  unsigned short res7;
+  unsigned short sysc;  /* 0x20 */
+  unsigned short res8;
+  unsigned short con;   /* 0x24 */
+  unsigned short res9;
+  unsigned short oa;    /* 0x28 */
+  unsigned short res10;
+  unsigned short sa;    /* 0x2C */
+  unsigned short res11;
+  unsigned short psc;   /* 0x30 */
+  unsigned short res12;
+  unsigned short scll;  /* 0x34 */
+  unsigned short res13;
+  unsigned short sclh;  /* 0x38 */
+  unsigned short res14;
+  unsigned short systest; /* 0x3c */
+  unsigned short res15;
+};
+
+static unsigned short wait_for_pin( void );
+
+static void wait_for_bb( void );
+
+static void flush_fifo( void );
+
+void i2c_init( int speed, int slaveadd );
+
+static int i2c_read_byte(
+  unsigned char devaddr,
+  unsigned char regoffset,
+  unsigned char *value
+);
+
+int i2c_write(
+  unsigned char chip,
+  unsigned int addr,
+  int alen,
+  unsigned char *buffer,
+  int len
+);
+
+int i2c_read(
+  unsigned char chip,
+  uint addr,
+  int alen,
+  unsigned char *buffer,
+  int len
+);
+
+static int imw ( unsigned char  chip, unsigned long addr, unsigned char byte );
+
+static int imd( unsigned char chip, unsigned int addr, unsigned int length );
+
+/**
+ * @brief Initializes the I2C module @a i2c.
+ *
+ * Valid @a clock_in_hz values are 100000 and 400000.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_INVALID_ID Invalid @a i2c value.
+ * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value.
+ */
+rtems_status_code beagle_i2c_init(
+  volatile beagle_i2c *i2c,
+  unsigned clock_in_hz
+);
+
+/**
+ * @brief Resets the I2C module @a i2c.
+ */
+void beagle_i2c_reset(volatile beagle_i2c *i2c);
+
+/**
+ * @brief Sets the I2C module @a i2c clock.
+ *
+ * Valid @a clock_in_hz values are 100000 and 400000.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value.
+ */
+rtems_status_code beagle_i2c_clock(
+  volatile beagle_i2c *i2c,
+  unsigned clock_in_hz
+);
+
+/**
+ * @brief Starts a write transaction on the I2C module @a i2c.
+ *
+ * The address parameter @a addr must not contain the read/write bit.
+ *
+ * The error status may be delayed to the next
+ * beagle_i2c_write_with_optional_stop() due to controller flaws.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+rtems_status_code beagle_i2c_write_start(
+  volatile beagle_i2c *i2c,
+  unsigned addr
+);
+
+/**
+ * @brief Writes data via the I2C module @a i2c with optional stop.
+ *
+ * The error status may be delayed to the next
+ * beagle_i2c_write_with_optional_stop() due to controller flaws.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+rtems_status_code beagle_i2c_write_with_optional_stop(
+  volatile beagle_i2c *i2c,
+  const uint8_t *out,
+  size_t n,
+  bool stop
+);
+
+/**
+ * @brief Starts a read transaction on the I2C module @a i2c.
+ *
+ * The address parameter @a addr must not contain the read/write bit.
+ *
+ * The error status may be delayed to the next
+ * beagle_i2c_read_with_optional_stop() due to controller flaws.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+rtems_status_code beagle_i2c_read_start(
+  volatile beagle_i2c *i2c,
+  unsigned addr
+);
+
+/**
+ * @brief Reads data via the I2C module @a i2c with optional stop.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false.
+ */
+rtems_status_code beagle_i2c_read_with_optional_stop(
+  volatile beagle_i2c *i2c,
+  uint8_t *in,
+  size_t n,
+  bool stop
+);
+
+/**
+ * @brief Writes and reads data via the I2C module @a i2c.
+ *
+ * This will be one bus transaction.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+rtems_status_code beagle_i2c_write_and_read(
+  volatile beagle_i2c *i2c,
+  unsigned addr,
+  const uint8_t *out,
+  size_t out_size,
+  uint8_t *in,
+  size_t in_size
+);
+
+/**
+ * @brief Writes data via the I2C module @a i2c.
+ *
+ * This will be one bus transaction.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+static inline rtems_status_code beagle_i2c_write(
+  volatile beagle_i2c *i2c,
+  unsigned addr,
+  const uint8_t *out,
+  size_t out_size
+)
+{
+  return beagle_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0);
+}
+
+/**
+ * @brief Reads data via the I2C module @a i2c.
+ *
+ * This will be one bus transaction.
+ *
+ * @retval RTEMS_SUCCESSFUL Successful operation.
+ * @retval RTEMS_IO_ERROR Received a NACK from the slave.
+ */
+static inline rtems_status_code beagle_i2c_read(
+  volatile beagle_i2c *i2c,
+  unsigned addr,
+  uint8_t *in,
+  size_t in_size
+)
+{
+  return beagle_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size);
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_I2C_H */
diff --git a/c/src/lib/libbsp/arm/beagle/include/irq.h b/c/src/lib/libbsp/arm/beagle/include/irq.h
new file mode 100644
index 0000000..4cbf3a2
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/include/irq.h
@@ -0,0 +1,23 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Basic BSP IRQ info.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_IRQ_H
+#define LIBBSP_ARM_BEAGLE_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 127
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/beagle/irq.c b/c/src/lib/libbsp/arm/beagle/irq.c
new file mode 100644
index 0000000..6055eb8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/irq.c
@@ -0,0 +1,145 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ * @ingroup arm_beagle
+ *
+ * @brief Interrupt support.
+ */
+
+/*
+ * Copyright (c) 2014 Ben Gras <beng at shrike-systems.com>. All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/irq-generic.h>
+#include <bsp/linker-symbols.h>
+
+#include <rtems/score/armv4.h>
+
+#include <libcpu/arm-cp15.h>
+
+struct omap_intr
+{
+  uint32_t base;
+  int size;
+};
+
+#if IS_DM3730
+static struct omap_intr omap_intr = {
+  .base = OMAP3_DM37XX_INTR_BASE,
+  .size = 0x1000,
+};
+#endif
+
+#if IS_AM335X
+static struct omap_intr omap_intr = {
+  .base = OMAP3_AM335X_INTR_BASE,
+  .size = 0x1000,
+};
+#endif
+
+static int irqs_enabled[BSP_INTERRUPT_VECTOR_MAX+1];
+
+volatile static int level = 0;
+
+void bsp_interrupt_dispatch(void)
+{
+  /* get irq */
+  uint32_t reg = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ);
+  int irq;
+  irq = reg & OMAP3_INTR_ACTIVEIRQ_MASK;
+
+  if(!irqs_enabled[irq]) {
+	/* Ignore spurious interrupt */
+  } else {
+    bsp_interrupt_vector_disable(irq);
+
+    /* enable new interrupts, and flush data cache to make sure
+     * it hits the intc
+     */
+    mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL, OMAP3_INTR_NEWIRQAGR);
+    flush_data_cache();
+    mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ);
+    flush_data_cache();
+
+    /* keep current irq masked but enable unmasked ones */
+    uint32_t psr = _ARMV4_Status_irq_enable();
+    bsp_interrupt_handler_dispatch(irq);
+
+    _ARMV4_Status_restore(psr);
+
+    bsp_interrupt_vector_enable(irq);
+  }
+}
+
+static uint32_t get_mir_reg(int vector, uint32_t *mask)
+{
+  *mask = 1UL << (vector % 32);
+
+  if(vector <   0) while(1) ;
+  if(vector <  32) return OMAP3_INTCPS_MIR0;
+  if(vector <  32) return OMAP3_INTCPS_MIR0;
+  if(vector <  64) return OMAP3_INTCPS_MIR1;
+  if(vector <  96) return OMAP3_INTCPS_MIR2;
+  if(vector < 128) return OMAP3_INTCPS_MIR3;
+  while(1) ;
+}
+
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  uint32_t mask, cur;
+  uint32_t mir_reg = get_mir_reg(vector, &mask);
+
+  cur = mmio_read(omap_intr.base + mir_reg);
+  mmio_write(omap_intr.base + mir_reg, cur & ~mask);
+  flush_data_cache();
+
+  irqs_enabled[vector] = 1;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  uint32_t mask, cur;
+  uint32_t mir_reg = get_mir_reg(vector, &mask);
+
+  cur = mmio_read(omap_intr.base + mir_reg);
+  mmio_write(omap_intr.base + mir_reg, cur | mask);
+  flush_data_cache();
+
+  irqs_enabled[vector] = 0;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+  int i;
+  uint32_t intc_ilrx;
+
+  /* AM335X TRM 6.2.1 Initialization Sequence */
+  mmio_write(omap_intr.base + OMAP3_INTCPS_SYSCONFIG, OMAP3_SYSCONFIG_AUTOIDLE);
+  mmio_write(omap_intr.base + OMAP3_INTCPS_IDLE, 0);
+  /* priority 0 to all IRQs */
+  for(intc_ilrx = 0x100; intc_ilrx <= 0x2fc; intc_ilrx += 4) {
+    mmio_write(omap_intr.base + intc_ilrx, 0);
+  }
+
+  /* Mask all interrupts */
+  for(i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; i++)
+    bsp_interrupt_vector_disable(i);
+
+  /* Install generic interrupt handler */
+  arm_cp15_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt);
+  arm_cp15_set_vector_base_address((uint32_t) bsp_vector_table_begin);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg
new file mode 100644
index 0000000..06c13ee
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg
@@ -0,0 +1,5 @@
+#
+#  Config file for BeagleBoard
+#
+
+include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagle.inc b/c/src/lib/libbsp/arm/beagle/make/custom/beagle.inc
new file mode 100644
index 0000000..3610016
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagle.inc
@@ -0,0 +1,11 @@
+#
+#  Config file for BeagleBoard.
+#
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = arm
+
+CPU_CFLAGS = -mcpu=cortex-a8
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardorig.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardorig.cfg
new file mode 100644
index 0000000..447a51e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardorig.cfg
@@ -0,0 +1,2 @@
+#  Config file for Original BeagleBoard
+include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
new file mode 100644
index 0000000..447a51e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
@@ -0,0 +1,2 @@
+#  Config file for Original BeagleBoard
+include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
new file mode 100644
index 0000000..447a51e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
@@ -0,0 +1,2 @@
+#  Config file for Original BeagleBoard
+include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
new file mode 100644
index 0000000..447a51e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
@@ -0,0 +1,2 @@
+#  Config file for Original BeagleBoard
+include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/misc/i2c.c b/c/src/lib/libbsp/arm/beagle/misc/i2c.c
new file mode 100644
index 0000000..ad23f3a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/misc/i2c.c
@@ -0,0 +1,450 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief I2C support implementation.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+#include <bsp.h>
+#include <bsp/i2c.h>
+
+static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
+
+static unsigned short wait_for_pin( void ) {
+
+  unsigned short status;
+  int timeout = I2C_TIMEOUT;
+
+  do {
+    udelay( 1000 );
+    status = readw( &i2c_base->stat );
+  } while( !( status &
+        ( I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
+        I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
+        I2C_STAT_AL ) ) && timeout-- );
+
+  if( timeout <= 0 ) {
+    printk( "timed out in wait_for_pin: I2C_STAT = %x\n",
+      readw( &i2c_base->stat ) );
+    writew( 0xFFFF, &i2c_base->stat );  /* clear current interrupts...*/
+    status = 0;
+  }
+
+  return status;
+}
+
+static void wait_for_bb( void ) {
+
+  int timeout = I2C_TIMEOUT;
+  unsigned short status;
+
+  writew( 0xFFFF, &i2c_base->stat );  /* clear current interrupts...*/
+  while( ( status = readw( &i2c_base->stat ) & I2C_STAT_BB ) && timeout-- ) {
+    writew( status, &i2c_base->stat );
+    udelay( 1000 );
+  }
+
+  if( timeout <= 0 ) {
+    printk( "timed out in wait_for_bb: I2C_STAT = %x\n",
+      readw( &i2c_base->stat ) );
+  }
+  writew( 0xFFFF, &i2c_base->stat );   /* clear delayed stuff*/
+}
+
+static void flush_fifo( void ) {
+
+  unsigned short status;
+
+  /* note: if you try and read data when its not there or ready
+   * you get a bus error
+   */
+  while( 1 ) {
+    status = readw( &i2c_base->stat );
+    if( status == I2C_STAT_RRDY ) {
+      readw( &i2c_base->data );
+      writew( I2C_STAT_RRDY, &i2c_base->stat );
+      udelay( 1000 );
+    } else {
+      break;
+    }
+  }
+}
+
+void i2c_init( int speed, int slaveadd ) {
+
+  int psc, fsscll, fssclh;
+  int hsscll = 0, hssclh = 0;
+  unsigned int scll, sclh;
+  int timeout = I2C_TIMEOUT;
+
+  // Only handle standard, fast and high speeds
+  if( ( speed != OMAP_I2C_STANDARD   ) &&
+      ( speed != OMAP_I2C_FAST_MODE  ) &&
+      ( speed != OMAP_I2C_HIGH_SPEED ) ) {
+    printk( "Error : I2C unsupported speed %d\n", speed );
+    return;
+  }
+
+  psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
+  psc -= 1;
+  if( psc < I2C_PSC_MIN ) {
+    printk( "Error : I2C unsupported prescalar %d\n", psc );
+    return;
+  }
+
+  if( speed == OMAP_I2C_HIGH_SPEED ) {
+    // High speed
+
+    // For first phase of HS mode
+    fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / ( 2 * OMAP_I2C_FAST_MODE );
+
+    fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
+    fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
+    if( ( ( fsscll < 0 ) || ( fssclh < 0 ) ) || ( ( fsscll > 255 ) ||
+      ( fssclh > 255 ) ) ) {
+      printk( "Error : I2C initializing first phase clock\n" );
+      return;
+    }
+
+    // For second phase of HS mode
+    hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / ( 2 * speed );
+
+    hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
+    hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
+    if( ( ( fsscll < 0 ) || ( fssclh < 0 ) ) || ( ( fsscll > 255 ) ||
+      ( fssclh > 255 ) ) ) {
+      printk( "Error : I2C initializing second phase clock\n" );
+      return;
+    }
+
+    scll = ( unsigned int ) hsscll << 8 | ( unsigned int ) fsscll;
+    sclh = ( unsigned int ) hssclh << 8 | ( unsigned int ) fssclh;
+
+  } else {
+    // Standard and fast speed
+    fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / ( 2 * speed );
+
+    fsscll -= I2C_FASTSPEED_SCLL_TRIM;
+    fssclh -= I2C_FASTSPEED_SCLH_TRIM;
+    if( ( ( fsscll < 0 ) || ( fssclh < 0 ) ) || ( ( fsscll > 255 ) ||
+      ( fssclh > 255 ) ) ) {
+      printk( "Error : I2C initializing clock\n" );
+      return;
+    }
+
+    scll = ( unsigned int ) fsscll;
+    sclh = ( unsigned int ) fssclh;
+  }
+
+  if( readw( &i2c_base->con ) & I2C_CON_EN ) {
+    writew( 0, &i2c_base->con );
+    udelay( 50000  );
+  }
+
+  writew( 0x2, &i2c_base->sysc ); /* for ES2 after soft reset */
+  udelay( 1000 );
+
+  writew( I2C_CON_EN, &i2c_base->con );
+  while( !( readw( &i2c_base->syss ) & I2C_SYSS_RDONE ) && timeout-- ) {
+    if (timeout <= 0) {
+      printk( "ERROR: Timeout in soft-reset\n" );
+      return;
+    }
+    udelay( 1000 );
+  }
+
+  writew( 0, &i2c_base->con );
+  writew( psc, &i2c_base->psc );
+  writew( scll, &i2c_base->scll );
+  writew( sclh, &i2c_base->sclh );
+
+  /* own address */
+  writew( slaveadd, &i2c_base->oa );
+  writew( I2C_CON_EN, &i2c_base->con );
+
+  /* have to enable intrrupts or OMAP i2c module doesn't work */
+  writew( I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE |
+          I2C_IE_AL_IE, &i2c_base->ie );
+  udelay( 1000 );
+  flush_fifo();
+  writew( 0xFFFF, &i2c_base->stat );
+  writew( 0, &i2c_base->cnt );
+
+  //if( gd->flags & GD_FLG_RELOC ) bus_initialized[ current_bus ] = 1;
+}
+
+static int i2c_read_byte(
+  unsigned char devaddr,
+  unsigned char regoffset,
+  unsigned char *value
+)
+{
+  int i2c_error = 0;
+  unsigned short status;
+
+  /* wait until bus not busy */
+  wait_for_bb();
+
+  /* one byte only */
+  writew(1, &i2c_base->cnt);
+  /* set slave address */
+  writew(devaddr, &i2c_base->sa);
+  /* no stop bit needed here */
+  writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+        I2C_CON_TRX, &i2c_base->con);
+
+  /* send register offset */
+  while (1) {
+    status = wait_for_pin();
+    if (status == 0 || status & I2C_STAT_NACK) {
+      i2c_error = 1;
+      goto read_exit;
+    }
+    if (status & I2C_STAT_XRDY) {
+      /* Important: have to use byte access */
+      writeb(regoffset, &i2c_base->data);
+      writew(I2C_STAT_XRDY, &i2c_base->stat);
+    }
+    if (status & I2C_STAT_ARDY) {
+      writew(I2C_STAT_ARDY, &i2c_base->stat);
+      break;
+    }
+  }
+
+  /* set slave address */
+  writew(devaddr, &i2c_base->sa);
+  /* read one byte from slave */
+  writew(1, &i2c_base->cnt);
+  /* need stop bit here */
+  writew(I2C_CON_EN | I2C_CON_MST |
+    I2C_CON_STT | I2C_CON_STP,
+    &i2c_base->con);
+
+  /* receive data */
+  while (1) {
+    status = wait_for_pin();
+    if (status == 0 || status & I2C_STAT_NACK) {
+      i2c_error = 1;
+      goto read_exit;
+    }
+    if (status & I2C_STAT_RRDY) {
+      *value = readw(&i2c_base->data);
+      writew(I2C_STAT_RRDY, &i2c_base->stat);
+    }
+    if (status & I2C_STAT_ARDY) {
+      writew(I2C_STAT_ARDY, &i2c_base->stat);
+      break;
+    }
+  }
+
+read_exit:
+  flush_fifo();
+  writew(0xFFFF, &i2c_base->stat);
+  writew(0, &i2c_base->cnt);
+  return i2c_error;
+}
+
+int i2c_write(
+  unsigned char chip,
+  unsigned int addr,
+  int alen,
+  unsigned char *buffer,
+  int len
+)
+{
+  int i;
+  unsigned short status;
+  int i2c_error = 0;
+
+  if (alen > 1) {
+    printk("I2C write: addr len %d not supported\n", alen);
+    return 1;
+  }
+
+  if (addr + len > 256) {
+    printk("I2C write: address 0x%x + 0x%x out of range\n",
+        addr, len);
+    return 1;
+  }
+
+  /* wait until bus not busy */
+  wait_for_bb();
+
+  /* start address phase - will write regoffset + len bytes data */
+  writew(alen + len, &i2c_base->cnt);
+  /* set slave address */
+  writew(chip, &i2c_base->sa);
+  /* stop bit needed here */
+  writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+    I2C_CON_STP, &i2c_base->con);
+
+  /* Send address byte */
+  status = wait_for_pin();
+
+  if (status == 0 || status & I2C_STAT_NACK) {
+    i2c_error = 1;
+    printk("error waiting for i2c address ACK (status=0x%x)\n",
+          status);
+    goto write_exit;
+  }
+
+  if (status & I2C_STAT_XRDY) {
+    writeb(addr & 0xFF, &i2c_base->data);
+    writew(I2C_STAT_XRDY, &i2c_base->stat);
+  } else {
+    i2c_error = 1;
+    printk("i2c bus not ready for transmit (status=0x%x)\n",
+          status);
+    goto write_exit;
+  }
+
+  /* address phase is over, now write data */
+  for (i = 0; i < len; i++) {
+    status = wait_for_pin();
+
+    if (status == 0 || status & I2C_STAT_NACK) {
+      i2c_error = 1;
+      printk("i2c error waiting for data ACK (status=0x%x)\n",
+          status);
+      goto write_exit;
+    }
+
+    if (status & I2C_STAT_XRDY) {
+      writeb(buffer[i], &i2c_base->data);
+      writew(I2C_STAT_XRDY, &i2c_base->stat);
+    } else {
+      i2c_error = 1;
+      printk("i2c bus not ready for Tx (i=%d)\n", i);
+      goto write_exit;
+    }
+  }
+
+write_exit:
+  flush_fifo();
+  writew(0xFFFF, &i2c_base->stat);
+  return i2c_error;
+}
+
+int i2c_read(
+  unsigned char chip,
+  uint addr,
+  int alen,
+  unsigned char *buffer,
+  int len
+)
+{
+  int i;
+
+  if (alen > 1) {
+    printk("I2C read: addr len %d not supported\n", alen);
+    return 1;
+  }
+
+  if (addr + len > 256) {
+    printk("I2C read: address out of range\n");
+    return 1;
+  }
+
+  for (i = 0; i < len; i++) {
+    if (i2c_read_byte(chip, addr + i, &buffer[i])) {
+      printk("I2C read: I/O error\n");
+      i2c_init( CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE );
+      return 1;
+    }
+  }
+
+  return 0;
+}
+
+/* Write (fill) memory
+ *
+ * Syntax:
+ *  i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
+ */
+static int imw ( unsigned char  chip, unsigned long addr, unsigned char byte )
+{
+
+  unsigned int  alen;
+  int count;
+
+  alen = 1;
+  count = 1;
+
+  while (count-- > 0) {
+    if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
+      printk("Error writing the chip.\n");
+    /*
+     * Wait for the write to complete.  The write can take
+     * up to 10mSec (we allow a little more time).
+     */
+  }
+
+  return (0);
+}
+
+/*
+ * Syntax:
+ *  i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
+ */
+static int imd( unsigned char chip, unsigned int addr, unsigned int length )
+{
+  int j, nbytes, linebytes;
+
+  unsigned int alen = 0;
+  if (alen > 3) return 0;
+
+  /*
+   * Print the lines.
+   *
+   * We buffer all read data, so we can make sure data is read only
+   * once.
+   */
+  nbytes = length;
+  do {
+    unsigned char linebuf[DISP_LINE_LEN];
+    unsigned char *cp;
+
+    linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+
+    if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
+      printk ("Error reading the chip.\n");
+    else {
+      printk("%04x:", addr);
+      cp = linebuf;
+      for (j=0; j<linebytes; j++) {
+        printk(" %02x", *cp++);
+        addr++;
+      }
+      printk ("    ");
+      cp = linebuf;
+      for (j=0; j<linebytes; j++) {
+        if ((*cp < 0x20) || (*cp > 0x7e))
+          printk (".");
+        else
+          printk("%c", *cp);
+        cp++;
+      }
+      printk ("\n");
+    }
+    nbytes -= linebytes;
+  } while (nbytes > 0);
+
+  return 0;
+}
diff --git a/c/src/lib/libbsp/arm/beagle/preinstall.am b/c/src/lib/libbsp/arm/beagle/preinstall.am
new file mode 100644
index 0000000..50957d8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/preinstall.am
@@ -0,0 +1,132 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+all-local: $(TMPINSTALL_FILES)
+
+TMPINSTALL_FILES =
+CLEANFILES = $(TMPINSTALL_FILES)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES += $(PREINSTALL_FILES)
+
+$(PROJECT_LIB)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_LIB)
+	@: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)
+	@: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/bsp/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
+	@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
+	@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
+$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
+
+$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
+
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
+
+$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h
+
+$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
+
+$(PROJECT_INCLUDE)/bsp/arm-a8core-start.h: ../shared/include/arm-a8core-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a8core-start.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a8core-start.h
+
+$(PROJECT_INCLUDE)/bsp/arm-cp15-start.h: ../shared/include/arm-cp15-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
+
+$(PROJECT_INCLUDE)/bsp/arm-errata.h: ../shared/include/arm-errata.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-errata.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-errata.h
+
+$(PROJECT_INCLUDE)/bsp/arm-release-id.h: ../shared/include/arm-release-id.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-release-id.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-release-id.h
+
+$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
+$(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
+
+$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
+
+$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
+
+$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
+TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+
+$(PROJECT_LIB)/linkcmds.beagle: startup/linkcmds.beagle $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.beagle
+TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.beagle
+
diff --git a/c/src/lib/libbsp/arm/beagle/simscripts/bbxm.cfg b/c/src/lib/libbsp/arm/beagle/simscripts/bbxm.cfg
new file mode 100644
index 0000000..a5fe36c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/simscripts/bbxm.cfg
@@ -0,0 +1,174 @@
+# Start with: openocd -f interface/ftdi/flyswatter.cfg -f bbxm.cfg -c 'reset init'
+#   or  with: openocd -f interface/ftdi/flyswatter2.cfg -f bbxm.cfg -c 'reset init'
+source [find board/ti_beagleboard_xm.cfg]
+
+#
+# Use the MLO file from uboot to initialise the board.
+#
+proc beagleboard_xm_mlo { file } {
+  global _CHIPNAME
+  adapter_khz 10
+  catch { mww phys 0x48307250 0x00000004 }
+  reset init
+  icepick_c_wreset $_CHIPNAME.jrc
+  halt
+  dm37x.cpu arm core_state arm
+  puts "Beagleboard xM MLO: $file"
+  load_image $file 0x402005f8 bin
+  resume 0x40200800
+  sleep 500
+  halt
+}
+
+proc beagleboard_xm_init {} {
+  global _CHIPNAME
+  adapter_khz 10
+  catch { mww phys 0x48307250 0x00000004 }
+  reset init
+  icepick_c_wreset $_CHIPNAME.jrc
+  halt
+  dm37x.cpu arm core_state arm
+
+  mwh 0x6e00007c 0x000000ff ;# omap-gpmc
+  mwh 0x6e00007c 0x00000090 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e00007c 0x00000000 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e000080 0x00000000 ;# omap-gpmc
+  mwh 0x6e00007c 0x00000030 ;# omap-gpmc
+  mww 0x48004c00 0x00000020 ;# omap3_cm
+  mww 0x48004c10 0x00000020 ;# omap3_cm
+  mww 0x48314048 0x0000aaaa ;# omap3_mpu_wdt
+  mww 0x48314048 0x00005555 ;# omap3_mpu_wdt
+  mww 0x6c000048 0xffffffff ;# omap3_sms
+  mww 0x48004c40 0x00000013 ;# omap3_cm
+  mww 0x48004c10 0x00000025 ;# omap3_cm
+  mww 0x48004c00 0x00000021 ;# omap3_cm
+  mww 0x48306d40 0x00000003 ;# omap3_prm
+  mww 0x48307270 0x00000083 ;# omap3_prm
+  mww 0x48307270 0x00000080 ;# omap3_prm
+  mww 0x48004904 0x00000015 ;# omap3_cm
+  mww 0x48004d00 0x00110016 ;# omap3_cm
+  mww 0x48005140 0x10020a50 ;# omap3_cm
+  mww 0x48004d40 0x08000040 ;# omap3_cm
+  mww 0x48004d40 0x09900040 ;# omap3_cm
+  mww 0x48004d40 0x09900c40 ;# omap3_cm
+  mww 0x48004d40 0x09900c00 ;# omap3_cm
+  mww 0x48004a40 0x00001305 ;# omap3_cm
+  mww 0x48004a40 0x00001125 ;# omap3_cm
+  mww 0x48004a40 0x00001109 ;# omap3_cm
+  mww 0x48004a40 0x0000110a ;# omap3_cm
+  mww 0x48004b40 0x00000005 ;# omap3_cm
+  mww 0x48004c40 0x00000015 ;# omap3_cm
+  mww 0x48004d00 0x00110006 ;# omap3_cm
+  mww 0x48004d00 0x00110007 ;# omap3_cm
+  mww 0x48004d00 0x00110007 ;# omap3_cm
+  mww 0x48005140 0x03020a50 ;# omap3_cm
+  mww 0x48004f40 0x00000004 ;# omap3_cm
+  mww 0x48004e40 0x00000409 ;# omap3_cm
+  mww 0x48004e40 0x00001009 ;# omap3_cm
+  mww 0x48004d48 0x00000009 ;# omap3_cm
+  mww 0x48004d44 0x02436000 ;# omap3_cm
+  mww 0x48004d44 0x0243600c ;# omap3_cm
+  mww 0x48004a40 0x0000110a ;# omap3_cm
+  mww 0x48004d00 0x00170007 ;# omap3_cm
+  mww 0x48004d04 0x00000011 ;# omap3_cm
+  mww 0x48004d50 0x00000001 ;# omap3_cm
+  mww 0x48004d4c 0x00007800 ;# omap3_cm
+  mww 0x48004d4c 0x0000780c ;# omap3_cm
+  mww 0x48004d00 0x00170037 ;# omap3_cm
+  mww 0x48004d04 0x00000017 ;# omap3_cm
+  mww 0x48004004 0x00000011 ;# omap3_cm
+  mww 0x48004044 0x00000001 ;# omap3_cm
+  mww 0x48004040 0x00081400 ;# omap3_cm
+  mww 0x48004040 0x00081400 ;# omap3_cm
+  mww 0x48004004 0x00000017 ;# omap3_cm
+  mww 0x48004944 0x00000001 ;# omap3_cm
+  mww 0x48004940 0x000a5800 ;# omap3_cm
+  mww 0x48004940 0x000a580c ;# omap3_cm
+  mww 0x48004904 0x00000017 ;# omap3_cm
+  mww 0x48005040 0x000000ff ;# omap3_cm
+  mww 0x48004c40 0x00000015 ;# omap3_cm
+  mww 0x48005040 0x000000ff ;# omap3_cm
+  mww 0x48005010 0x00000008 ;# omap3_cm
+  mww 0x48005000 0x00000008 ;# omap3_cm
+  mww 0x48004a00 0x00002000 ;# omap3_cm
+  mww 0x48004a10 0x00002042 ;# omap3_cm
+  mww 0x48005000 0x00000808 ;# omap3_cm
+  mww 0x48005010 0x00000808 ;# omap3_cm
+  mww 0x48004a00 0x0003a000 ;# omap3_cm
+  mww 0x48004a10 0x0003a042 ;# omap3_cm
+  mww 0x48004c10 0x00000025 ;# omap3_cm
+  mww 0x48004000 0x00000001 ;# omap3_cm
+  mww 0x48004a00 0x03fffe29 ;# omap3_cm
+  mww 0x48004a10 0x3ffffffb ;# omap3_cm
+  mww 0x48004a14 0x0000001f ;# omap3_cm
+  mww 0x48004c00 0x000000e9 ;# omap3_cm
+  mww 0x48004c10 0x0000003f ;# omap3_cm
+  mww 0x48004e00 0x00000005 ;# omap3_cm
+  mww 0x48004e10 0x00000001 ;# omap3_cm
+  mww 0x48004f00 0x00000001 ;# omap3_cm
+  mww 0x48004f10 0x00000001 ;# omap3_cm
+  mww 0x48005000 0x0003ffff ;# omap3_cm
+  mww 0x48005010 0x0003ffff ;# omap3_cm
+  mww 0x48005410 0x00000001 ;# omap3_cm
+  mww 0x48005400 0x00000003 ;# omap3_cm
+  mww 0x48004a18 0x00000004 ;# omap3_cm
+  mww 0x48004a08 0x00000004 ;# omap3_cm
+  mww 0x6e000060 0x00001800 ;# omap-gpmc
+  mww 0x6e000064 0x00141400 ;# omap-gpmc
+  mww 0x6e000068 0x00141400 ;# omap-gpmc
+  mww 0x6e00006c 0x0f010f01 ;# omap-gpmc
+  mww 0x6e000070 0x010c1414 ;# omap-gpmc
+  mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc
+  mww 0x6e000078 0x00000870 ;# omap-gpmc
+  mwb 0x6e00007c 0x000000ff ;# omap-gpmc
+  mwb 0x6e00007c 0x00000070 ;# omap-gpmc
+  mwb 0x6e00007c 0x00000090 ;# omap-gpmc
+  mwb 0x6e000080 0x00000000 ;# omap-gpmc
+  mww 0x6d000010 0x00000002 ;# omap.sdrc
+  mww 0x6d000010 0x00000000 ;# omap.sdrc
+  mww 0x6d000044 0x00000100 ;# omap.sdrc
+  mww 0x6d000070 0x04000081 ;# omap.sdrc
+  mww 0x6d000060 0x0000000a ;# omap.sdrc
+  mww 0x6d000080 0x04590099 ;# omap.sdrc
+  mww 0x6d00009c 0xc29dc4c6 ;# omap.sdrc
+  mww 0x6d0000a0 0x00022322 ;# omap.sdrc
+  mww 0x6d0000a4 0x0004e201 ;# omap.sdrc
+  mww 0x6d0000a8 0x00000000 ;# omap.sdrc
+  mww 0x6d0000a8 0x00000001 ;# omap.sdrc
+  mww 0x6d0000a8 0x00000002 ;# omap.sdrc
+  mww 0x6d0000a8 0x00000002 ;# omap.sdrc
+  mww 0x6d000084 0x00000032 ;# omap.sdrc
+  mww 0x6d000040 0x00000004 ;# omap.sdrc
+  mww 0x6d0000b0 0x04590099 ;# omap.sdrc
+  mww 0x6d0000c4 0xc29dc4c6 ;# omap.sdrc
+  mww 0x6d0000c8 0x00022322 ;# omap.sdrc
+  mww 0x6d0000d4 0x0004e201 ;# omap.sdrc
+  mww 0x6d0000d8 0x00000000 ;# omap.sdrc
+  mww 0x6d0000d8 0x00000001 ;# omap.sdrc
+  mww 0x6d0000d8 0x00000002 ;# omap.sdrc
+  mww 0x6d0000d8 0x00000002 ;# omap.sdrc
+  mww 0x6d0000b4 0x00000032 ;# omap.sdrc
+  mww 0x6d0000b0 0x00000000 ;# omap.sdrc
+  mww 0x6e00001c 0x00000000 ;# omap-gpmc
+  mww 0x6e000040 0x00000000 ;# omap-gpmc
+  mww 0x6e000050 0x00000000 ;# omap-gpmc
+  mww 0x6e000078 0x00000000 ;# omap-gpmc
+  mww 0x6e000078 0x00000000 ;# omap-gpmc
+  mww 0x6e000060 0x00001800 ;# omap-gpmc
+  mww 0x6e000064 0x00141400 ;# omap-gpmc
+  mww 0x6e000068 0x00141400 ;# omap-gpmc
+  mww 0x6e00006c 0x0f010f01 ;# omap-gpmc
+  mww 0x6e000070 0x010c1414 ;# omap-gpmc
+  mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc
+  mww 0x6e000078 0x00000870 ;# omap-gpmc
+  mww 0x48004a00 0x437ffe00 ;# omap3_cm
+  mww 0x48004a10 0x637ffed2 ;# omap3_cm
+  puts "Beagleboard xM initialised"
+}
+
+init
diff --git a/c/src/lib/libbsp/arm/beagle/simscripts/gdbinit.bbxm b/c/src/lib/libbsp/arm/beagle/simscripts/gdbinit.bbxm
new file mode 100644
index 0000000..32ae9dd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/simscripts/gdbinit.bbxm
@@ -0,0 +1,16 @@
+target remote localhost:3333
+mon reset halt
+mon beagleboard_xm_init
+load
+
+b _ARMV4_Exception_undef_default
+b _ARMV4_Exception_swi_default
+b _ARMV4_Exception_pref_abort_default
+b _ARMV4_Exception_data_abort_default
+b _ARMV4_Exception_reserved_default
+b _ARMV4_Exception_irq_default
+b _ARMV4_Exception_fiq_default
+
+b rtems_fatal
+b rtems_fatal_error_occurred
+b _exit
diff --git a/c/src/lib/libbsp/arm/beagle/simscripts/qemu-beagleboard.in b/c/src/lib/libbsp/arm/beagle/simscripts/qemu-beagleboard.in
new file mode 100644
index 0000000..949389f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/simscripts/qemu-beagleboard.in
@@ -0,0 +1,64 @@
+#
+#  ARM/BeagleBoard Qemu Support 
+#
+
+bspUsesGDBSimulator="no"
+# bspGeneratesGDBCommands="yes"
+# bspSupportsGDBServerMode="yes"
+runBSP=NOT_OVERRIDDEN
+if [ ! -r ${runBSP} ] ; then
+  runBSP=qemu-system-arm
+fi
+bspNeedsDos2Unix="yes"
+bspGeneratesDeviceTree="yes"
+bspInputDevice=qemu-gumstix.cmds
+bspTreeFile=qemu-gumstix.cmds
+bspRedirectInput=yes
+
+runARGS()
+{
+# qemu-system-arm -M connex -m 289 -nographic -monitor null -pflash connex-flash.img <cmds >log
+
+  UBOOT=${HOME}/qemu/u-boot-connex-400-r1604.bin
+  FLASH=connex-flash.img
+  ( dd of=${FLASH} bs=128k count=128 if=/dev/zero ;
+    dd of=${FLASH} bs=128k conv=notrunc if=${UBOOT} ;
+    dd of=${FLASH} bs=1k conv=notrunc seek=4096 if=${1} ) >/dev/null 2>&1
+
+  if [ ${coverage} = yes ] ; then
+     rm -f trace ${1}.tra
+     COVERAGE_ARG="-trace ${1}.tra"
+  fi
+
+  echo "-M connex -m 289 -nographic -monitor null \
+         -pflash ${FLASH} ${COVERAGE_ARG}"
+}
+
+checkBSPFaults()
+{
+  return 0
+}
+
+bspLimit()
+{
+  testname=$1
+  case ${testname} in
+    *stackchk*)limit=5 ;;
+    *fatal*)   limit=1 ;;
+    *minimum*) limit=1 ;;
+    *psxtime*) limit=180 ;;
+    *)         limit=60 ;;
+  esac
+  echo ${limit}
+}
+
+### Generate the commands we boot with
+bspGenerateDeviceTree()
+{
+cat >qemu-gumstix.cmds <<EOF
+
+bootelf 0x400000
+
+EOF
+}
+
diff --git a/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh b/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
new file mode 100644
index 0000000..58ac911
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
@@ -0,0 +1,89 @@
+# we store all generated files here.
+TMPDIR=tmp_sdcard_dir.$$
+
+FATIMG=$TMPDIR/bbxm_boot_fat.img
+OFFSET=2048
+FATSIZE_KB=2880
+FATSIZE=`expr $FATSIZE_KB \* 2`
+SIZE=`expr $FATSIZE + $OFFSET`
+UENV=uEnv.txt
+
+rm -rf $TMPDIR
+mkdir -p $TMPDIR
+
+if [ $# -ne 2 ]
+then	echo "Usage: $0 <RTEMS prefix> <RTEMS executable>"
+	exit 1
+fi
+
+PREFIX=$1
+
+if [ ! -d "$PREFIX" ]
+then	echo "This script needs the RTEMS tools bindir as the first argument."
+	exit 1
+fi
+
+executable=$2
+
+case "$2" in
+	*beagleboard*)
+		ubootcfg=omap3_beagle
+		imgtype=bb
+		;;
+	*beaglebone*)
+		ubootcfg=am335x_evm
+		imgtype=bone
+		;;
+	*)
+		echo "Can't guess which uboot to use - please specify full path to executable."
+		exit 1
+		;;
+esac
+
+app=rtems-app.img
+
+if [ ! -f "$executable" ]
+then	echo "Expecting RTEMS executable as arg; $executable not found."
+	exit 1
+fi
+
+set -e
+
+IMG=${imgtype}_`basename $2`-sdcard.img
+
+# Make an empty image
+dd if=/dev/zero of=$IMG bs=512 seek=$SIZE count=1
+# Make an ms-dos FS image
+rm -f $FATIMG
+export MTOOLSRC=$TMPDIR/mtools-conf
+echo "drive a:
+       file=\"$FATIMG\"
+       fat_bits=16
+" >$MTOOLSRC
+$PREFIX/bin/mformat -C -f $FATSIZE_KB a:
+
+# Prepare the executable.
+base=`basename $executable`
+$PREFIX/bin/arm-rtems4.11-objcopy $executable -O binary $TMPDIR/$base.bin
+gzip -9 $TMPDIR/$base.bin
+$PREFIX/bin/mkimage -A arm -O rtems -T kernel -a 0x80000000 -e 0x80000000 -n RTEMS -d $TMPDIR/$base.bin.gz $TMPDIR/$app
+echo "setenv bootdelay 5
+uenvcmd=run boot
+boot=fatload mmc 0 0x80800000 $app ; bootm 0x80800000" >$TMPDIR/$UENV
+
+# Copy the uboot and app image onto the FAT image
+$PREFIX/bin/mcopy -bsp -i $FATIMG $PREFIX/uboot/$ubootcfg/MLO ::MLO
+$PREFIX/bin/mcopy -bsp -i $FATIMG $PREFIX/uboot/$ubootcfg/u-boot.img ::u-boot.img
+$PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$app ::$app
+$PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$UENV ::$UENV
+
+# Just a single FAT partition (type C) that uses all of the image
+$PREFIX/bin/partition $IMG $OFFSET 'c:0*+'
+
+# Put the FAT image into the SD image
+dd if=$FATIMG of=$IMG seek=$OFFSET
+
+# cleanup
+rm -rf $TMPDIR
+
+echo "Result is in $IMG."
diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspreset.c b/c/src/lib/libbsp/arm/beagle/startup/bspreset.c
new file mode 100644
index 0000000..5865b7b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/startup/bspreset.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Ben Gras <beng at shrike-systems.com>. All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+
+#define AM335X_CM_BASE 0x44E00000
+#define AM335X_CM_SIZE 0x1000
+
+#define AM335X_PRM_DEVICE_OFFSET 0xf00
+#define AM335X_PRM_RSTCTRL_REG 0x00
+#define AM335X_RST_GLOBAL_WARM_SW_BIT 0
+
+#define DM37XX_CM_BASE 0x48307000
+#define DM37XX_CM_SIZE 0x1000
+#define DM37XX_PRM_RSTCTRL_REG 0x250
+#define DM37XX_RST_DPLL3_BIT 2
+
+void bsp_reset(void)
+{
+#if IS_DM3730
+  static uint32_t reset_base = DM37XX_CM_BASE;
+  while (true) {
+    mmio_set((reset_base + DM37XX_PRM_RSTCTRL_REG),
+             (1 << DM37XX_RST_DPLL3_BIT));
+  }
+#endif
+
+#if IS_AM335X
+  static uint32_t reset_base = AM335X_CM_BASE;
+  while (true) {
+    mmio_set((reset_base + AM335X_PRM_DEVICE_OFFSET +
+              AM335X_PRM_RSTCTRL_REG),
+             (1 << AM335X_RST_GLOBAL_WARM_SW_BIT));
+  }
+#endif
+}
diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspstart.c b/c/src/lib/libbsp/arm/beagle/startup/bspstart.c
new file mode 100644
index 0000000..b156564
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/startup/bspstart.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start(void)
+{
+#if IS_DM3730
+  const char* type = "dm3730-based";
+#endif
+#if IS_AM335X
+  const char* type = "am335x-based";
+#endif
+  bsp_interrupt_initialize();
+  printk("\nRTEMS Beagleboard: %s\n", type);
+}
diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/beagle/startup/bspstarthooks.c
new file mode 100644
index 0000000..2efa304
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/startup/bspstarthooks.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-cp15-start.h>
+#include <bsp/arm-a8core-start.h>
+
+#include <bsp/uart-output-char.h>
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+  arm_a8core_start_hook_1();
+  bsp_start_copy_sections();
+  beagle_setup_mmu_and_cache();
+  bsp_start_clear_bss();
+}
diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c b/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
new file mode 100644
index 0000000..157edfa
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info at embedded-brains.de>
+ *
+ * Copyright (c) 2014 Chris Johns.  All rights reserved.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-cp15-start.h>
+
+#define ARM_SECTIONS       4096          /* all sections needed to describe the
+                                            virtual address space */
+#define ARM_SECTION_SIZE   (1024 * 1024) /* how much virtual memory is described
+                                            by one section */
+
+//static uint32_t pagetable[ARM_SECTIONS] __attribute__((aligned (1024*16)));
+
+BSP_START_DATA_SECTION static const arm_cp15_start_section_config
+beagle_mmu_config_table[] = {
+  ARMV7_CP15_START_DEFAULT_SECTIONS,
+  {
+    .begin = 0x40000000U,
+    .end = 0x4FFFFFFFU,
+    .flags = ARMV7_MMU_DEVICE
+  }
+};
+
+/*
+ * Make weak and let the user override.
+ */
+BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void) __attribute__ ((weak));
+
+BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void)
+{
+  /* turn mmu off first in case it's on */
+  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
+    ARM_CP15_CTRL_M | ARM_CP15_CTRL_A,	/* clear - mmu off */
+    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
+  );
+
+  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
+    ctrl,
+    (uint32_t *) bsp_translation_table_base,
+    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
+    &beagle_mmu_config_table[0],
+    RTEMS_ARRAY_SIZE(beagle_mmu_config_table)
+  );
+}
diff --git a/c/src/lib/libbsp/arm/beagle/startup/linkcmds.beagle b/c/src/lib/libbsp/arm/beagle/startup/linkcmds.beagle
new file mode 100644
index 0000000..93f1a49
--- /dev/null
+++ b/c/src/lib/libbsp/arm/beagle/startup/linkcmds.beagle
@@ -0,0 +1,46 @@
+/**
+ * @file
+ *
+ * @ingroup  arm_beagle
+ *
+ * @brief Linker script for beagles.
+ */
+
+MEMORY {
+  /* Beagleboards and beaglebones all
+   * have either 256M or 512M memory. We just
+   * use 256M for all.
+   */
+  RAM      : ORIGIN = 0x80000000, LENGTH = 256M - 4M
+  RAM_MMU  : ORIGIN = 0x80000000 + 256M - 4M, LENGTH = 16k
+}
+
+REGION_ALIAS ("REGION_START",          RAM);
+REGION_ALIAS ("REGION_VECTOR",         RAM);
+REGION_ALIAS ("REGION_TEXT",           RAM);
+REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
+REGION_ALIAS ("REGION_RODATA",         RAM);
+REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
+REGION_ALIAS ("REGION_DATA",           RAM);
+REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
+REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+REGION_ALIAS ("REGION_FAST_DATA",      RAM);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+REGION_ALIAS ("REGION_BSS",            RAM);
+REGION_ALIAS ("REGION_WORK",           RAM);
+REGION_ALIAS ("REGION_STACK",          RAM);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+bsp_vector_table_in_start_section = 1;
+
+bsp_translation_table_base = ORIGIN (RAM_MMU);
+bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
+
+INCLUDE linkcmds.armv4
+
+HeapSize = 1024 * 1024;
diff --git a/c/src/lib/libbsp/bfin/acinclude.m4 b/c/src/lib/libbsp/bfin/acinclude.m4
index ab6082e..828fd89 100644
--- a/c/src/lib/libbsp/bfin/acinclude.m4
+++ b/c/src/lib/libbsp/bfin/acinclude.m4
@@ -2,12 +2,12 @@
 AC_DEFUN([RTEMS_CHECK_BSPDIR],
 [
   case "$1" in
-  TLL6527M )
-    AC_CONFIG_SUBDIRS([TLL6527M]);;
   bf537Stamp )
     AC_CONFIG_SUBDIRS([bf537Stamp]);;
   eZKit533 )
     AC_CONFIG_SUBDIRS([eZKit533]);;
+  TLL6527M )
+    AC_CONFIG_SUBDIRS([TLL6527M]);;
   *)
     AC_MSG_ERROR([Invalid BSP]);;
   esac
diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4 b/c/src/lib/libbsp/powerpc/acinclude.m4
index 6442399..e46fa2b 100644
--- a/c/src/lib/libbsp/powerpc/acinclude.m4
+++ b/c/src/lib/libbsp/powerpc/acinclude.m4
@@ -38,12 +38,12 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
     AC_CONFIG_SUBDIRS([t32mppc]);;
   tqm8xx )
     AC_CONFIG_SUBDIRS([tqm8xx]);;
-  virtex )
-    AC_CONFIG_SUBDIRS([virtex]);;
   virtex4 )
     AC_CONFIG_SUBDIRS([virtex4]);;
   virtex5 )
     AC_CONFIG_SUBDIRS([virtex5]);;
+  virtex )
+    AC_CONFIG_SUBDIRS([virtex]);;
   *)
     AC_MSG_ERROR([Invalid BSP]);;
   esac
-- 
1.8.3.4



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