[PATCH 2/2] score/sparc: Flush all cores icache after trap table update

[Joel Sherrill]

Seems reasonable. My only concern is creeping sysstate.h
into cpu.c but I think that's OK.

--joel
On 7/3/2014 4:39 AM, Daniel Cederman wrote:
> Changes to the trap table might be missed by other cores.
> If the system state is up, the other cores can be notified
> using SMP messages that they need to flush their icache.
> If the up state has not been reached there is no need to
> notify other cores. They will do an automatic flush of the
> icache just after entering the up state, but before enabling
> interrupts.
> ---
>  cpukit/score/cpu/sparc/cpu.c |   23 +++++++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
> index c616de4..69e50f2 100644
> --- a/cpukit/score/cpu/sparc/cpu.c
> +++ b/cpukit/score/cpu/sparc/cpu.c
> @@ -22,6 +22,7 @@
>  #include <rtems/score/percpu.h>
>  #include <rtems/score/tls.h>
>  #include <rtems/rtems/cache.h>
> +#include <rtems/score/sysstate.h>
>  
>  RTEMS_STATIC_ASSERT(
>    offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable)
> @@ -157,6 +158,9 @@ void _CPU_ISR_install_raw_handler(
>    CPU_Trap_table_entry  *slot;
>    uint32_t               u32_tbr;
>    uint32_t               u32_handler;
> +#ifdef RTEMS_SMP
> +  cpu_set_t              all_cpus;
> +#endif
>  
>    /*
>     *  Get the "real" trap number for this vector ignoring the synchronous
> @@ -210,9 +214,24 @@ void _CPU_ISR_install_raw_handler(
>      (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
>    slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
>  
> -  /* need to flush icache after this !!! */
> -
> +  /* 
> +   * Changes to the trap table might be missed by other cores.
> +   * If the system state is up, the other cores can be notified
> +   * using SMP messages that they need to flush their icache.
> +   * If the up state has not been reached there is no need to
> +   * notify other cores. They will do an automatic flush of the
> +   * icache just after entering the up state, but before enabling
> +   * interrupts.
> +   */
> +#ifdef RTEMS_SMP
> +  if( _System_state_Is_up( _System_state_Get() ) ) {
> +    CPU_FILL( &all_cpus );
> +    rtems_cache_invalidate_entire_instruction_cpu_set( &all_cpus );
> +  } else
> +    rtems_cache_invalidate_entire_instruction();
> +#else
>    rtems_cache_invalidate_entire_instruction();
> +#endif
>  
>  }
>  

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
Support Available                (256) 722-9985