[PATCH 3/3] score: Add SMP support to the cache manager

[Sebastian Huber]

I think instruction cache operations scoped by processors make no sense on SMP. 
  Every processor should have the same view to the instruction memory.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

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