SPARC Floating Point Context

[Sebastian Huber]

Hello,

I just noticed that the SPARC floating point unit (FPU) support is a bit odd:

1. the context switch saves and restores all 32 floating point registers (%f0 
up to %f31) and the FSR

http://git.rtems.org/rtems/tree/cpukit/score/cpu/sparc/rtems/score/cpu.h#n551

2. the interrupt entry/exit doesn't save/restore the floating point registers.

Since we use the System V ABI, this makes no sense.  Here all floating point 
registers are volatile.

The SPARC V8 trap entry sequence doesn't disable the FPU via the PSR_EF bit. 
So it seems that interrupt handler using the FPU can destroy the FPU context of 
the interrupted thread?

For a System V ABI conforming implementation it should be:

1. the interrupt entry/exit must save/restore the floating point registers 
to/from the stack of the interrupted thread

2. nothing more

What was the reason for the existing implementation?

-- 
Sebastian Huber, embedded brains GmbH

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