ERC32 with FPU rev.B or rev.C

[Joel Sherrill]

Then we finally have clearance to remove this code. :)

Nice to see you again last week Jiri.

On 3/5/2014 3:15 AM, Jiri Gaisler wrote:
> These fixes are no longer necessary, the silicon has been fixed
> long time ago. The only real use of these early chip revisions
> were in the GNC computers of the Space Station (!), where they
> run a modified version of VxWorks 5.1 ... :-)
>
> Jiri.
>
> On 03/05/2014 09:25 AM, Sebastian Huber wrote:
>> Hello,
>>
>> there is a fix for the ERC32 with FPU rev.B or rev.C in the SPARC interrupt entry code:
>>
>> http://git.rtems.org/rtems/tree/c/src/lib/libbsp/sparc/shared/irq_asm.S#n426
>>
>> Exists there systems with such a processor?  Is it reasonable to ship RTEMS 4.11 or later on such a system?
>>
>> I would like to remove this code block.
>>
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-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
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