[PATCH 16/18] bsp/altera-cyclone-v: Add Alteras hwlib

Ralf Kirchner ralf.kirchner at embedded-brains.de
Fri Mar 7 13:59:20 UTC 2014


Add hwlib as copied from Altera
---
 .../hwlib/include/alt_16550_uart.h                 | 1555 +
 .../hwlib/include/alt_address_space.h              |  390 +
 .../hwlib/include/alt_bridge_manager.h             |  269 +
 .../hwlib/include/alt_clock_group.h                |   95 +
 .../hwlib/include/alt_clock_manager.h              | 1431 +
 .../arm/altera-cyclone-v/hwlib/include/alt_dma.h   |  940 +
 .../hwlib/include/alt_dma_common.h                 |  162 +
 .../hwlib/include/alt_dma_program.h                |  949 +
 .../hwlib/include/alt_fpga_manager.h               | 1052 +
 .../hwlib/include/alt_generalpurpose_io.h          | 1236 +
 .../altera-cyclone-v/hwlib/include/alt_globaltmr.h |  458 +
 .../hwlib/include/alt_hwlibs_ver.h                 |   52 +
 .../hwlib/include/alt_interrupt_common.h           |  531 +
 .../hwlib/include/alt_mpu_registers.h              |  156 +
 .../hwlib/include/alt_reset_manager.h              |  249 +
 .../hwlib/include/alt_system_manager.h             |  209 +
 .../altera-cyclone-v/hwlib/include/alt_timers.h    |  677 +
 .../altera-cyclone-v/hwlib/include/alt_watchdog.h  |  779 +
 .../arm/altera-cyclone-v/hwlib/include/hwlib.h     |  190 +
 .../hwlib/include/socal/alt_acpidmap.h             | 3569 +
 .../altera-cyclone-v/hwlib/include/socal/alt_can.h |36873 +++++++
 .../hwlib/include/socal/alt_clkmgr.h               | 6464 ++
 .../altera-cyclone-v/hwlib/include/socal/alt_dap.h |  144 +
 .../hwlib/include/socal/alt_dmanonsecure.h         |  144 +
 .../hwlib/include/socal/alt_dmasecure.h            |  144 +
 .../hwlib/include/socal/alt_emac.h                 |103305 ++++++++++++++++++
 .../altera-cyclone-v/hwlib/include/socal/alt_f2h.h | 1075 +
 .../hwlib/include/socal/alt_fpgamgr.h              | 7090 ++
 .../hwlib/include/socal/alt_fpgamgrdata.h          |  158 +
 .../hwlib/include/socal/alt_gpio.h                 | 1991 +
 .../altera-cyclone-v/hwlib/include/socal/alt_h2f.h | 1073 +
 .../altera-cyclone-v/hwlib/include/socal/alt_i2c.h | 5940 +
 .../altera-cyclone-v/hwlib/include/socal/alt_l3.h  | 6299 ++
 .../hwlib/include/socal/alt_l4wd.h                 | 1801 +
 .../hwlib/include/socal/alt_lwfpgaslvs.h           |   52 +
 .../hwlib/include/socal/alt_lwh2f.h                | 1450 +
 .../hwlib/include/socal/alt_mpul2.h                |  144 +
 .../hwlib/include/socal/alt_mpuscu.h               |  144 +
 .../hwlib/include/socal/alt_nand.h                 |10617 ++
 .../hwlib/include/socal/alt_nanddata.h             |   52 +
 .../hwlib/include/socal/alt_ocram.h                |   52 +
 .../hwlib/include/socal/alt_qspi.h                 | 5951 +
 .../hwlib/include/socal/alt_qspidata.h             |   52 +
 .../altera-cyclone-v/hwlib/include/socal/alt_rom.h |   52 +
 .../hwlib/include/socal/alt_rstmgr.h               | 3382 +
 .../hwlib/include/socal/alt_scanmgr.h              |  927 +
 .../hwlib/include/socal/alt_sdmmc.h                | 9115 ++
 .../altera-cyclone-v/hwlib/include/socal/alt_sdr.h | 4149 +
 .../hwlib/include/socal/alt_spim.h                 | 3293 +
 .../hwlib/include/socal/alt_spis.h                 | 2958 +
 .../altera-cyclone-v/hwlib/include/socal/alt_stm.h |  144 +
 .../hwlib/include/socal/alt_sysmgr.h               |24810 +++++
 .../altera-cyclone-v/hwlib/include/socal/alt_tmr.h |  864 +
 .../hwlib/include/socal/alt_uart.h                 | 5158 +
 .../altera-cyclone-v/hwlib/include/socal/alt_usb.h |114043 ++++++++++++++++++++
 .../arm/altera-cyclone-v/hwlib/include/socal/hps.h | 8026 ++
 .../altera-cyclone-v/hwlib/include/socal/socal.h   |  356 +
 .../hwlib/src/hwmgr/alt_16550_uart.c               | 1179 +
 .../hwlib/src/hwmgr/alt_address_space.c            |  184 +
 .../hwlib/src/hwmgr/alt_bridge_manager.c           |  189 +
 .../hwlib/src/hwmgr/alt_clock_manager.c            | 5208 +
 .../arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c | 2806 +
 .../hwlib/src/hwmgr/alt_dma_program.c              | 1043 +
 .../hwlib/src/hwmgr/alt_fpga_manager.c             |  999 +
 .../hwlib/src/hwmgr/alt_generalpurpose_io.c        |  745 +
 .../hwlib/src/hwmgr/alt_globaltmr.c                |  529 +
 .../hwlib/src/hwmgr/alt_reset_manager.c            |  135 +
 .../hwlib/src/hwmgr/alt_system_manager.c           |  265 +
 .../altera-cyclone-v/hwlib/src/hwmgr/alt_timers.c  | 1292 +
 .../hwlib/src/hwmgr/alt_watchdog.c                 | 1026 +
 70 Dateien geändert, 398841 Zeilen hinzugefügt(+)
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_bridge_manager.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_fpga_manager.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_globaltmr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_system_manager.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_timers.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_watchdog.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_can.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dap.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_emac.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_f2h.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_fpgamgr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_fpgamgrdata.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_h2f.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l4wd.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_lwfpgaslvs.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_lwh2f.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_mpul2.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_mpuscu.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_nand.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_nanddata.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_ocram.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rom.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_scanmgr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sdmmc.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sdr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_spim.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_spis.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_stm.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sysmgr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_tmr.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_uart.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_usb.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/hps.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_16550_uart.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_bridge_manager.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_dma_program.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_fpga_manager.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_generalpurpose_io.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_globaltmr.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_reset_manager.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_system_manager.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_timers.c
 create mode 100644 c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_watchdog.c

diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h
new file mode 100644
index 0000000..bca6f63
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h
@@ -0,0 +1,1555 @@
+/*
+ * Altera - SoC UART Manager
+ */
+
+/*****************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *****************************************************************************/
+
+#ifndef __ALT_16550_UART_H__
+#define __ALT_16550_UART_H__
+
+#include "hwlib.h"
+#include "alt_clock_manager.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup UART UART Driver API
+ *
+ * This module defines the Universal Asynchronous Receiver/Transmitter (UART)
+ * API for accessing and using the UART resources. The API allows for general
+ * control of a 16550 compatible UART controller.
+ *
+ * This implementation can control the following UARTs:
+ *  * SoCFPGA On-board UARTs
+ *  * Altera 16550 Compatible Soft IP UART
+ *
+ * The following reference materials were used in the design of this API:
+ *  * Synopsys® DesignWare DW_apb_uart Databook v3.10a
+ *
+ * @{
+ */
+
+/*!
+ * \addtogroup UART_BASIC UART Basic
+ *
+ * This group of APIs provides basic access to the UART to initialize,
+ * uninitialize, read, write, and reset the UART.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the list of UARTs available on the system.
+ */
+typedef enum ALT_16550_DEVICE_e
+{
+    /*!
+     * This option selects UART0 in the SoC FPGA.
+     */
+    ALT_16550_DEVICE_SOCFPGA_UART0 = 0,
+
+    /*!
+     * This option selects UART1 in the SoC FPGA.
+     */
+    ALT_16550_DEVICE_SOCFPGA_UART1 = 1,
+
+    /*!
+     * This option selects an Altera 16550 Compatible soft IP UART. The memory
+     * location of the device must be provided as part of the initialization.
+     */
+    ALT_16550_DEVICE_ALTERA_16550_UART = 0x100
+}
+ALT_16550_DEVICE_t;
+
+/*!
+ * This structure is used to represent a handle to a specific UART on the
+ * system. The internal members are undocumented and should be not altered
+ * outside of this API.
+ */
+typedef struct ALT_16550_HANDLE_s
+{
+    ALT_16550_DEVICE_t device;
+    void *             location;
+    alt_freq_t         clock_freq;
+    uint32_t           data;
+    uint32_t           fcr;
+}
+ALT_16550_HANDLE_t;
+
+/*!
+ * Performs the initialization steps needed by the UART. This should be the
+ * first API call made when accessing a particular UART
+ *
+ * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600
+ * baud.
+ *
+ * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before
+ * initialization.
+ *
+ * \param       device
+ *              The UART device identifier.
+ *
+ * \param       location
+ *              The memory of the location for the given UART. For SoCFPGA
+ *              UARTs, this parameter is ignored.
+ *
+ * \param       clock_freq
+ *              The clock frequency of the serial clock for the given UART.
+ *              For SoCFPGA UARTs, this paramter is ignored.
+ *
+ * \param       handle
+ *              [out] A pointer to a handle that will represent the UART. This
+ *              handle should subsequently be used when calling other UART
+ *              APIs.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device identifier is invalid.
+ * \retval      ALT_E_BAD_CLK   The required clock is not yet setup.
+ */
+ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device,
+                               void * location,
+                               alt_freq_t clock_freq,
+                               ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Performs the uninitialization steps for the UART. This should be the last
+ * API call made to cleanup the UART.
+ *
+ * After calling this function, the handle will need to be initialized again
+ * before being used by calling alt_16550_init().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Resets the UART to the default configuration. The UART will be reset and
+ * reinitialized.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Starts the UART after all configuration has been completed.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Stops the UART. While UART configuration can be done while enabled, it is
+ * not recommended.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads a single character from the UART receiver buffer. This API should
+ * only be used when FIFOs are disabled.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       item
+ *              [out] Pointer to an output parameter that contains the in
+ *              receiver buffer of the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle,
+                               char * item);
+
+/*!
+ * Writes a single character to the UART transmitter buffer. This API should
+ * only be used when FIFOs are disabled.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       item
+ *              The character to write to the transmitter buffer of the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle,
+                                char item);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_FIFO UART FIFO Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * FIFO. The FIFO allows the UART to buffer received data and data to be
+ * transmitted.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the receiver FIFO level conditions that
+ * will trigger the receiver FIFO to issue a receiver FIFO full event.
+ */
+typedef enum ALT_16550_FIFO_TRIGGER_RX_e
+{
+    /*!
+     * 1 or more character(s) in the receiver FIFO will trigger an event.
+     */
+    ALT_16550_FIFO_TRIGGER_RX_ANY = 0,
+
+    /*!
+     * 25% or higher capacity usage in the receiver FIFO will trigger an
+     * event.
+     */
+    ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1,
+
+    /*!
+     * 50% or higher capacity usage in the receiver FIFO will trigger an
+     * event.
+     */
+    ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2,
+
+    /*!
+     * 2 characters less than the receiver FIFO capacity will trigger an
+     * event.
+     */
+    ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3
+}
+ALT_16550_FIFO_TRIGGER_RX_t;
+
+/*!
+ * This type definition enumerates the transmitter FIFO level conditions that
+ * will trigger the transmitter FIFO to issue a transmitter FIFO empty event.
+ */
+typedef enum ALT_16550_FIFO_TRIGGER_TX_e
+{
+    /*!
+     * Transmitter FIFO being completely empty will trigger an event.
+     */
+    ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0,
+
+    /*!
+     * 2 or less character(s) in the transmitter FIFO will trigger an event.
+     */
+    ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1,
+
+    /*!
+     * 25% or less capacity usage in the transmitter FIFO will trigger an
+     * event.
+     */
+    ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2,
+
+    /*!
+     * 50% or less capacity usage in the transmitter FIFO will trigger an
+     * event.
+     */
+    ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3
+}
+ALT_16550_FIFO_TRIGGER_TX_t;
+
+/*!
+ * Enables FIFO on the UART. This will enable both the receiver FIFO and
+ * transmitter FIFO. Both FIFOs will be cleared.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables FIFOs on the UART. This will disable both the receiver FIFO and
+ * transmitter FIFO. Any data left in the FIFOs will be lost.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the given buffer from the receiver FIFO in the UART.
+ *
+ * The available characters in the FIFO can be determined by a few ways. Users
+ * can determine the number of items by calling alt_16550_fifo_level_get_rx().
+ *
+ * Another way is by using the RX trigger and RX interrupt. First determine the
+ * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired
+ * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the
+ * triggering point by applying trigger description on the FIFO size. Enable RX
+ * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires
+ * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering
+ * point value can be used to determine the RX FIFO level. If the interrupt
+ * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be
+ * completely emptied by repeatedly polling the Line Status
+ * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get().
+ * These steps are necessary if the UART does not implement FIFO level query
+ * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible
+ * Soft UART.
+ *
+ * Reading more data than that which is available can result in invalid data
+ * appearing like valid data.
+ *
+ * The FIFO must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       buffer
+ *              [out] Pointer to a buffer where the specified count of
+ *              characters from the receiver FIFO will be copied to.
+ *
+ * \param       count
+ *              The count of characters from the receiver FIFO to be copied.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle,
+                                    char * buffer,
+                                    size_t count);
+
+/*!
+ * Writes the given buffer to the transmitter FIFO in the UART.
+ *
+ * The available space in the FIFO can be determined by a few ways. Users can
+ * determine the number of items by calculating the FIFO capacity minus the
+ * FIFO level. This can be done by calling  alt_16550_fifo_size_get_tx() and
+ * alt_16550_fifo_level_get_tx() respectively.
+ *
+ * Another way is by using the TX trigger and TX interrupt. First determine the
+ * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired
+ * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the
+ * triggering point by applying the trigger description on the FIFO size.
+ * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX
+ * interrupt fires, calculate the empty entries in the FIFO by subtracting the
+ * TX FIFO size and the calculated value. These steps are necessary if the UART
+ * does not implement FIFO level query functionality. As of 13.0sp1, this
+ * applies to the Altera 16550 Compatible Soft UART.
+ *
+ * Writing more data that there is space can result in data lost due to
+ * overflowing.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       buffer
+ *              Pointer to a buffer from where the specified count of
+ *              characters will be copied to the transmitter FIFO.
+ *
+ * \param       count
+ *              The count of characters from the given buffer to be copied.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle,
+                                     const char * buffer,
+                                     size_t count);
+
+/*!
+ * Clears the contents of the receiver FIFO. Any characters which were
+ * previously contained in that FIFO will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Clears the contents of the transmitter FIFO. Any characters which were
+ * previously contained in that FIFO will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Clears the contents of the receiver and transmitter FIFO. Any characters
+ * which were previously contained on those FIFOs will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Queries the size of the receiver FIFO. 
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       size
+ *              [out] Pointer to an output parameter that contains the size of
+ *              the receiver FIFO.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle,
+                                           uint32_t * size);
+
+/*!
+ * Queries the size of the transmitter FIFO. 
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       size
+ *              [out] Pointer to an output parameter that contains the size of
+ *              the transmitter FIFO.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle,
+                                           uint32_t * size);
+
+/*!
+ * Queries the current level of the receiver FIFO.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * For the Altera 16550 Compatible UART, it may not be possible to read the
+ * FIFO level and this function may always report 0. For more information on
+ * interacting with the FIFO in this situation, see documentation for
+ * alt_16550_fifo_read().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       level
+ *              [out] Pointer to an output parameter that contains the level
+ *              or number of characters in the receiver FIFO.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle,
+                                            uint32_t * level);
+
+/*!
+ * Queries the current level of the transmitter FIFO.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * For the Altera 16550 Compatible UART, it may not be possible to read the
+ * FIFO level and this function may always report 0. For more information on
+ * interacting with the FIFO in this situation, see documentation for
+ * alt_16550_fifo_write().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       level
+ *              [out] Pointer to an output parameter that contains the level
+ *              or number of characters in the transmitter FIFO.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle,
+                                            uint32_t * level);
+
+/*!
+ * Sets the receiver FIFO level which will trigger the receiver FIFO to issue
+ * receiver FIFO full event. For the list of available receiver FIFO trigger
+ * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       trigger
+ *              The level of the receiver FIFO which is needed to trigger a
+ *              receiver FIFO full event.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle,
+                                              ALT_16550_FIFO_TRIGGER_RX_t trigger);
+
+/*!
+ * Sets the transmitter FIFO level which will trigger the transmitter FIFO to
+ * transmitter FIFO empty event. For the list of available transmitter FIFO
+ * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       trigger
+ *              The level of the transmitter FIFO which is needed to trigger a
+ *              transmitter FIFO empty event.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle,
+                                              ALT_16550_FIFO_TRIGGER_TX_t trigger);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_BAUD UART Baudrate Interface
+ *
+ * This group of APIs allows for the configuration of the UART's baudrate
+ * generation related functions.
+ *
+ * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with
+ * the configured divisor.
+ *
+ * @{
+ */
+
+/*!
+ * This enumeration lists out the common baudrates used with modem and serial
+ * ports. Not every baudrate is available for the UART due to the limits of
+ * the serial clock frequency and divisor value.
+ */
+typedef enum ALT_16550_BAUDRATE_e
+{
+    ALT_16550_BAUDRATE_50     =     50, /*!< 50 bps baudrate. */
+    ALT_16550_BAUDRATE_75     =     75, /*!< 75 bps baudrate. */
+    ALT_16550_BAUDRATE_150    =    150, /*!< 150 bps baudrate. */
+    ALT_16550_BAUDRATE_300    =    300, /*!< 300 bps baudrate. */
+    ALT_16550_BAUDRATE_600    =    600, /*!< 600 bps baudrate. */
+    ALT_16550_BAUDRATE_900    =    900, /*!< 900 bps baudrate. */
+    ALT_16550_BAUDRATE_1200   =   1200, /*!< 1200 bps baudrate. */
+    ALT_16550_BAUDRATE_1800   =   1800, /*!< 1800 bps baudrate. */
+    ALT_16550_BAUDRATE_2400   =   2400, /*!< 2400 bps baudrate. */
+    ALT_16550_BAUDRATE_3600   =   3600, /*!< 3600 bps baudrate. */
+    ALT_16550_BAUDRATE_4800   =   4800, /*!< 4800 bps baudrate. */
+    ALT_16550_BAUDRATE_7200   =   7200, /*!< 7200 bps baudrate. */
+    ALT_16550_BAUDRATE_9600   =   9600, /*!< 9600 bps baudrate. */
+    ALT_16550_BAUDRATE_14400  =  14400, /*!< 14400 bps baudrate. */
+    ALT_16550_BAUDRATE_19200  =  19200, /*!< 19200 bps baudrate. */
+    ALT_16550_BAUDRATE_28800  =  28800, /*!< 28800 bps baudrate. */
+    ALT_16550_BAUDRATE_38400  =  38400, /*!< 38400 bps baudrate. */
+    ALT_16550_BAUDRATE_57600  =  57600, /*!< 57600 bps baudrate. */
+    ALT_16550_BAUDRATE_115200 = 115200  /*!< 115200 bps baudrate. */
+}
+ALT_16550_BAUDRATE_t;
+
+/*!
+ * Gets the baudrate for the UART.
+ *
+ * This is done by calculating the baudrate from the divisor and the serial
+ * clock. The reported baudrate may not correspond exactly to the request
+ * baudrate.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       baudrate
+ *              [out] Pointer to an output paramter that contains the current
+ *              baudrate of the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle,
+                                       uint32_t * baudrate);
+
+/*!
+ * Sets the baudrate for the UART. This change will take effect when the UART
+ * moves from disabled to enabled.
+ *
+ * This is done by calculating the correct divisor using the request baudrate
+ * and the known serial clock.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       baudrate
+ *              The requested baudrate for the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ * \retval      ALT_E_ARG_RANGE The given baudrate is not possible due to
+ *                              limitations of the baudrate divisor and/or
+ *                              serial clock.
+ */
+ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle,
+                                       uint32_t baudrate);
+
+/*!
+ * Gets the baudrate divisor for the UART.
+ *
+ * The baudrate is determined by the following formula:
+ *  * Baudrate = (serial clock frequency) / (16 * divisor)
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       divisor
+ *              [out] Pointer to an output parameter that contains the current
+ *              divisor used for baudrate generation.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle,
+                                      uint32_t * divisor);
+
+/*!
+ * Sets the baudrate divisor for the UART. This change will take effect when
+ * the UART moves from disabled to enabled.
+ *
+ * The baudrate is determined by the following formula:
+ *  * Baudrate = (serial clock frequency) / (16 * divisor)
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       divisor
+ *              The specified divisor value to use for baudrate generation.
+ *              Valid values are 1 - 65535.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART identifier is invalid or the
+ *                              specified divisor is not supported by the
+ *                              UART.
+ */
+ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle,
+                                      uint32_t divisor);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_INT UART Interrupt Interface
+ *
+ * This group of APIs provides access, configuration, and control of the 
+ * UART interrupts. 
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the different interrupt conditions that can
+ * be generated by the UART controller.
+ *
+ * Interrupts are listed in highest to lowest priority order.
+ */
+typedef enum ALT_16550_INT_STATUS_e
+{
+    /*!
+     * This interrupt signals that a overrun, parity, or framing error 
+     * occurred, or a break event occured. The interrupt is cleared by reading
+     * the line status by calling alt_16550_line_status_get() or by disabling
+     * line status interrupts by calling alt_16550_int_disable_line().
+     */
+    ALT_16550_INT_STATUS_LINE = 0x6,
+
+    /*!
+     * This interrupt signals that some data is available to be read from the
+     * UART. The definition of some depends on whether FIFOs are enabled or
+     * not.
+     *
+     * If FIFOs are disabled, this interrupt signals that the receiver
+     * contains data. In this case, the interrupt is cleared by reading the
+     * data from the UART by calling alt_16550_read().
+     *
+     * If FIFOs are enabled, this interrupt signals that the receiver FIFO
+     * level is above the receiver trigger level specified. In this case, the
+     * interrupt is cleared by reading a sufficiently large buffer from the
+     * receiver FIFO such that the FIFO is filled below the receiver trigger
+     * level specified by calling alt_16550_fifo_read() or by adjusting the
+     * receiver trigger level appropriately by calling
+     * alt_16550_fifo_trigger_set_rx().
+     *
+     * In either case, this interrupt can also be cleared by disabling
+     * receiver interrupts by calling alt_16550_int_disable_rx().
+     */
+    ALT_16550_INT_STATUS_RX_DATA = 0x4,
+
+    /*!
+     * This interrupt signals that data is available in the receiver FIFO and
+     * that there has been no activity with the receiver FIFO for the last 4
+     * character frames. In essence, the receiver FIFO has temporarily settled
+     * thus it may be a good time to empty the receiver FIFO. This interrupt
+     * is only available if FIFOs are enabled. The interrupt is cleared by
+     * reading from the receiver FIFO by calling alt_16550_fifo_read() or by
+     * disabling receiver interrupts by calling alt_16550_int_disable_rx().
+     */
+    ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC,
+
+    /*!
+     * This interrupt signals that the transmitter is idling. The definition
+     * of idling depends on whether FIFOs are enabled or not.
+     *
+     * If FIFOs are disabled, this interrupt signals that the transmitter
+     * shift register is empty. In this case, the interrupt is cleared by
+     * writing data to the UART by calling alt_16550_write().
+     *
+     * If FIFO are enabled, this interrupt signals that the transmitter FIFO
+     * level is below the transmitter trigger level specified. In this case,
+     * the interrupt is cleared by writing a sufficiently large buffer to the
+     * transmitter FIFO such that the FIFO is filled above the transmitter
+     * trigger level specified by calling alt_16550_fifo_write() or by
+     * adjusting the transmitter trigger level appropriately by calling
+     * alt_16550_fifo_trigger_set_tx().
+     *
+     * In either case, this interrupt can also be cleared by disabling
+     * transmitter interrupts by calling alt_16550_int_disable_tx().
+     */
+    ALT_16550_INT_STATUS_TX_IDLE = 0x2,
+
+    /*!
+     * Modem status interrupt pending. The interrupt is cleared by reading the
+     * modem status by calling alt_16550_modem_status_get() or by disabling
+     * modem status interrupts by calling alt_16550_int_disable_modem().
+     */
+    ALT_16550_INT_STATUS_MODEM = 0x0,
+
+    /*!
+     * No interrupts pending.
+     */
+    ALT_16550_INT_STATUS_NONE = 0x1
+}
+ALT_16550_INT_STATUS_t;
+
+/*!
+ * Enables the receiver FIFO to generate interrupts. Enabling this interrupt
+ * allows for the following interrupt signal(s):
+ *  * ALT_16550_INT_STATUS_RX_DATA
+ *  * ALT_16550_INT_STATUS_RX_TIMEOUT
+ *
+ * This interrupt is disabled by default.
+ *
+ * The FIFOs must also be enabled for this interrupt to actually be generated.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the receiver FIFO from generating interrupts.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the transmitter FIFO to generate interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ *  * ALT_16550_INT_STATUS_TX_IDLE
+ *
+ * This interrupt is disabled by default.
+ *
+ * The FIFOs must also be enabled for this interrupt to actually be generated.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the transmitter FIFO from generating interrupts.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the receiver to generate line status interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ *  * ALT_16550_INT_STATUS_LINE
+ *
+ * This interrupt is disabled by default.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the receiver from generating line status interrupts.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the UART to generate modem status interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ *  * ALT_16550_INT_STATUS_MODEM
+ *
+ * This interrupt is disabled by default.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the UART from generate modem status interrupts.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables all interrupts on the UART.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Queries the interrupt status of the UART. This returns the highest priority
+ * interrupt pending. The appropriate interrupts must be enabled for them be
+ * generated in the UART.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       status
+ *              [out] Pointer to an output parameter that contains the current
+ *              interrupt status of the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE  alt_16550_int_status_get(ALT_16550_HANDLE_t * handle,
+                                          ALT_16550_INT_STATUS_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_MODEM UART Modem Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * Modem interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the set of UART modem status conditions as
+ * register mask values.
+ */
+typedef enum ALT_16550_MODEM_STATUS_e
+{
+    /*!
+     * Data Carrier Detect. This status indicates that the carrier has been
+     * detected by the modem. It corresponds to an inverted dcd_n input. DCD
+     * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0.
+     */
+    ALT_16550_MODEM_STATUS_DCD = 1 << 7,
+
+    /*!
+     * Ring Indicator. This status indicates that the telephone ringing signal
+     * has been redeived by the modem. It corresponds to an inverted ri_n
+     * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is
+     * logic 0.
+     */
+    ALT_16550_MODEM_STATUS_RI = 1 << 6,
+
+    /*!
+     * Data Set Ready. This status indicates that the modem is ready to
+     * establish communications with the UART. It corresponds to an inverted
+     * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when
+     * dsr_n is logic 0.
+     */
+    ALT_16550_MODEM_STATUS_DSR = 1 << 5,
+
+    /*!
+     * Clear To Send. This status indicates the current state of the modem
+     * cts_n line. It corresponds to an inverted cts_n input. CTS is
+     * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0.
+     */
+    ALT_16550_MODEM_STATUS_CTS = 1 << 4,
+
+    /*!
+     * Delta Data Carrier Detect. This status condition indicates that the
+     * Data Carrier Detect has changed since the last time the modem status
+     * was read. Reading the modem status clears this status. For more
+     * information about the Data Carrier Detect status, see
+     * ALT_16550_MODEM_STATUS_DCD.
+     */
+    ALT_16550_MODEM_STATUS_DDCD = 1 << 3,
+
+    /*!
+     * Trailing Edge of Ring Indicator. This status indicates that the Ring
+     * Indicator has changed from asserted to unasserted. Reading the modem
+     * status will clear this status. For more information about the Ring
+     * Indicator status, reference ALT_16550_MODEM_STATUS_RI.
+     */
+    ALT_16550_MODEM_STATUS_TERI = 1 << 2,
+
+    /*!
+     * Delta Data Set Ready. This status condition indicates that the Data Set
+     * Ready has changed since the last time the modem status was read.
+     * Reading the modem status will clear this status. For more information
+     * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR.
+     */
+    ALT_16550_MODEM_STATUS_DDSR = 1 << 1,
+
+    /*!
+     * Delta Clear To Send. This status condition indicates that the Clear To
+     * Send has changed since the last time the modem status was read. Reading
+     * the modem status will clear this status. For more information about the
+     * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS.
+     */
+    ALT_16550_MODEM_STATUS_DCTS = 1 << 0
+}
+ALT_16550_MODEM_STATUS_t;
+
+/*!
+ * Enables automatic flow control in the UART modem. When in this mode, the
+ * rts_n is gated with the threshold trigger condition of the receiver FIFO.
+ *
+ * The Altera 16550 Compatible Soft IP UART may not have this option enabled.
+ *
+ * The FIFOs must be enabled for flow control to be used.
+ *
+ * The recommended bring up for flow control is as follows:
+ *  * Enable automatic flow control by calling alt_16550_flowcontrol_enable().
+ *    This will allow both the receiver FIFO and user RTS to control the rts_n
+ *    output. Because the user RTS is not enabled, the rts_n will be inactive
+ *    high.
+ *  * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the
+ *    receiver FIFO to have full control of the rts_n output.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables automatic flow control in the UART modem.
+ *
+ * The recommended bring down for flow control is as follows:
+ *  * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable
+ *    generation of the rts_n ouput.
+ *  * Disable automatic flow control by calling
+ *    alt_16550_flowcontrol_disable().
+ *
+ * The receiver FIFO will still be active after these steps.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Puts the UART in loopback mode. This is used for diagnostic and test
+ * purposes.
+ *
+ * The SoCFPGA UARTs does not support automatic flow control when in loopback
+ * mode.
+ *
+ * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and
+ * later. Setting this has no effect with 13.0.
+ *
+ * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are
+ * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n)
+ * are held inactive high externally and internally looped back to the inputs.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Takes the UART out of loopback mode.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Unasserts the OUT1 output.  OUT1 is inverted then driven out to out1_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the RTS (Request To Send) output. RTS is inverted then driven out
+ * to rts_n. RTS is used to inform the modem that the UART is ready to receive
+ * data.
+ *
+ * There are special considerations when the UART is in automatic flow control
+ * mode. See alt_16550_flowcontrol_enable() for more information.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out
+ * to rts_n.
+ *
+ * There are special considerations when the UART is in automatic flow control
+ * mode. See alt_16550_flowcontrol_enable() for more information.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven
+ * out to dtr_n. DTR is used to inform the modem that UART is ready to
+ * establish communications.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven
+ * out to dtr_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the modem status from the UART.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       status
+ *              [out] Pointer to an output parameter that contains the current
+ *              modem status of the UART as a register mask.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle,
+                                           uint32_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_LINE UART Line Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * Line interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the supported databits per frame.
+ */
+typedef enum ALT_16550_DATABITS_e
+{
+    /*!
+     * This option selects 5 databits per frame.
+     */
+    ALT_16550_DATABITS_5 = 0,
+
+    /*!
+     * This option selects 6 databits per frame.
+     */
+    ALT_16550_DATABITS_6 = 1,
+
+    /*!
+     * This option selects 7 databits per frame.
+     */
+    ALT_16550_DATABITS_7 = 2,
+
+    /*!
+     * This option selects 8 databits per frame.
+     */
+    ALT_16550_DATABITS_8 = 3
+}
+ALT_16550_DATABITS_t;
+
+/*!
+ * This type definition enumerates the supported stopbits per frame.
+ */
+typedef enum ALT_16550_STOPBITS_e
+{
+    /*!
+     * This options specifies 1 stopbit per frame.
+     */
+    ALT_16550_STOPBITS_1 = 0,
+
+    /*!
+     * This options specifies 2 stopbits per frame. If the frame is
+     * configured with 5 databits, 1.5 stopbits is used instead.
+     */
+    ALT_16550_STOPBITS_2 = 1
+}
+ALT_16550_STOPBITS_t;
+
+/*!
+ * This type definition enumerates the possible parity to use per frame.
+ */
+typedef enum ALT_16550_PARITY_e
+{
+    /*!
+     * This option disables the parity error detection bit in the data frame.
+     */
+    ALT_16550_PARITY_DISABLE = 0,
+
+    /*!
+     * This option enables the odd parity error detection bit in the data
+     * frame.
+     */
+    ALT_16550_PARITY_ODD = 1,
+
+    /*!
+     * This option enables the even parity error detection bit in the data
+     * frame.
+     */
+    ALT_16550_PARITY_EVEN = 2
+}
+ALT_16550_PARITY_t;
+
+/*!
+ * This type definition enumerates the set of UART line status conditions as
+ * register mask values.
+ */
+typedef enum ALT_16550_LINE_STATUS_e
+{
+    /*!
+     * Receiver FIFO Error. This status indicates that one or more parity
+     * error, framing error, or break indication exists in the receiver FIFO.
+     * It is only set when FIFO is enabled. This status cleared when line
+     * status is read, the character with the issue is at the top of the FIFO,
+     * and when no other issues exist in the FIFO.
+     */
+    ALT_16550_LINE_STATUS_RFE = 1 << 7,
+
+    /*!
+     * Transmitter EMpTy (Empty). This status indicates that transmitter shift
+     * register is empty. If FIFOs are enabled, the status is set when the
+     * transmitter FIFO is also empty. This status is cleared when the
+     * transmitter shift registers is loaded by writing to the UART
+     * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is
+     * done by calling alt_16550_write() and alt_16550_fifo_write()
+     * respectively.
+     */
+    ALT_16550_LINE_STATUS_TEMT = 1 << 6,
+
+    /*!
+     * Transmitter Holding Register Empty. This status indicates that the 
+     * transmitter will run out of data soon. The definition of soon depends
+     * on whether the FIFOs are enabled.
+     *
+     * If FIFOs are disabled, this status indicates that the transmitter will
+     * run out of data to send after the current transmit shift register
+     * completes. In this case, this status is cleared when the data is
+     * written to the UART. This can be done by calling alt_16550_write().
+     *
+     * If FIFOs are enabled, this status indicates that the transmitter FIFO
+     * level is below the transmitter trigger level specified. In this case,
+     * this status is cleared by writing a sufficiently large buffer to the
+     * transmitter FIFO such that the FIFO is filled above the transmitter
+     * trigger level specified by calling alt_16550_fifo_write() or by
+     * adjusting the transmitter trigger level appropriately by calling 
+     * alt_16550_fifo_trigger_set_tx().
+     *
+     * \internal
+     * The implementation of the UART driver always ensures that IER[7] is
+     * set. This means that the UART always has Programmable THRE (Transmitter
+     * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled.
+     * \endinternal
+     */
+    ALT_16550_LINE_STATUS_THRE = 1 << 5,
+
+    /*!
+     * Break Interrupt. This status indicates that a break interrupt sequence
+     * is detected in the incoming serial data. This happens when the the data
+     * is 0 for longer than a frame would normally be transmitted. The break
+     * interrupt status is cleared by reading the line status by calling
+     * alt_16550_line_status_get().
+     *
+     * If FIFOs are enabled, this status will be set when the character with
+     * the break interrupt status is at the top of the receiver FIFO.
+     */
+    ALT_16550_LINE_STATUS_BI = 1 << 4,
+
+    /*!
+     * Framing Error. This status indicates that a framing error occurred in
+     * the receiver. This happens when the receiver detects a missing or
+     * incorrect number of stopbit(s).
+     *
+     * If FIFOs are enabled, this status will be set when the character with
+     * the framing error is at the top of the FIFO. When a framing error
+     * occurs, the UART attempts to resynchronize with the transmitting UART.
+     * This status is also set if break interrupt occurred.
+     */
+    ALT_16550_LINE_STATUS_FE = 1 << 3,
+
+    /*!
+     * Parity Error. This status indicates that a parity error occurred in the
+     * receiver.
+     *
+     * If FIFOs are enabled, this status will be set when the character with
+     * the parity error is at the top of the receiver FIFO. This status is
+     * also set if a break interrupt occurred.
+     */
+    ALT_16550_LINE_STATUS_PE = 1 << 2,
+
+    /*!
+     * Overrun Error. This status indicates that an overrun occurred in the
+     * receiver.
+     *
+     * If FIFOs are disabled, the arriving character will overwrite the
+     * existing character in the receiver. Any previously existing
+     * character(s) will be lost.
+     *
+     * If FIFOs are disabled, the arriving character will be discarded. The
+     * buffer will continue to contain the preexisting characters.
+     */
+    ALT_16550_LINE_STATUS_OE = 1 << 1,
+
+    /*!
+     * Data Ready. This status indicates that the receiver or receiver FIFO
+     * contains at least one character.
+     */
+    ALT_16550_LINE_STATUS_DR = 1 << 0
+}
+ALT_16550_LINE_STATUS_t;
+
+/*!
+ * Sets the configuration for a given character frame.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       databits
+ *              The number of databits for each character frame.
+ *
+ * \param       parity
+ *              The parity to use for each character frame.
+ *
+ * \param       stopbits
+ *              The number of stopbits for each character frame.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle,
+                                          ALT_16550_DATABITS_t databits,
+                                          ALT_16550_PARITY_t parity,
+                                          ALT_16550_STOPBITS_t stopbits);
+
+/*!
+ * Starts transmitting a break condition by transmitting a logic 0 state
+ * longer than a frame would normally be transmitted.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Stops transmitting a break condition.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the line status from the UART.
+ *
+ * \param       handle
+ *              The UART device handle.
+ *
+ * \param       status
+ *              [out] Pointer to an output parameter that contains the current
+ *              line status of the UART.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle,
+                                          uint32_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_16550_UART_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h
new file mode 100644
index 0000000..b66ccdf
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h
@@ -0,0 +1,390 @@
+/*! \file
+ *  Altera - SoC FPGA Address Space Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_ADDR_SPACE_H__
+#define __ALT_ADDR_SPACE_H__
+
+#include <stdbool.h>
+#include "hwlib.h"
+#include "socal/hps.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************/
+// ARM Level 2 Cache Controller L2C-310 Register Interface
+
+// Address Filtering Start Register
+// The Address Filtering Start Register is a read and write register.
+// Bits     Field                       Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_start   | Address filtering start address for
+//         |                           | bits [31:20] of the filtering address.
+// [19:1]  | Reserved                  | SBZ/RAZ
+// [0]     | address_filtering_enable  | 0 - address filtering disabled
+//         |                           | 1 - address filtering enabled.
+
+// Address Filtering Start Register Address
+#define L2_CACHE_ADDR_FILTERING_START_OFST      0xC00
+#define L2_CACHE_ADDR_FILTERING_START_ADDR      (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
+// Address Filtering Start Register - Start Value Mask
+#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
+// Address Filtering Start Register - Reset Start Address Value (1 MB)
+#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
+// Address Filtering Start Register - Enable Flag Mask
+#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK     0x00000001
+// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
+#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET    0x1
+
+// Address Filtering End Register
+// The Address Filtering End Register is a read and write register.
+// Bits     Field                       Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_end     | Address filtering end address for bits
+//         |                           | [31:20] of the filtering address.
+// [19:0]  | Reserved                  | SBZ/RAZ
+
+// Address Filtering End Register Address
+#define L2_CACHE_ADDR_FILTERING_END_OFST        0xC04
+#define L2_CACHE_ADDR_FILTERING_END_ADDR        (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
+// Address Filtering End Register - End Value Mask
+#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK   0xFFF00000
+// Address Filtering End Register - Reset End Address Value (3 GB)
+#define L2_CACHE_ADDR_FILTERING_END_RESET       0xC0000000
+
+#ifndef __ASSEMBLY__
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
+ *
+ * This module contains group APIs for managing the HPS address space. This
+ * module contains group APIs to manage:
+ * * Memory Map Control
+ * * Memory Coherence
+ * * Cache Managment
+ * * MMU Managment
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
+ *
+ * This group API provides functions to map and remap selected address ranges
+ * into the accessible (visible) views of the MPU and non MPU address spaces.
+ *
+ * \b Caveats
+ *
+ * \b NOTE: Caution should be observed when remapping address 0 to different
+ * memory.  The code performing the remapping operation should not be executing
+ * in the address range being remapped to different memory.
+ *
+ * For example, if address 0 is presently mapped to OCRAM and the code is
+ * preparing to remap address 0 to SDRAM, then the code must not be executing in
+ * the range 0 to 64 KB as this address space is about to be remapped to
+ * different memory. If the code performing the remap operation is executing
+ * from OCRAM then it needs to be executing from its permanently mapped OCRAM
+ * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
+ *
+ * \b NOTE: The MPU address space view is controlled by two disparate hardware
+ * control interfaces: the L3 remap register and the L2 cache address filtering
+ * registers. To complicate matters, the L3 remap register is write-only which
+ * means not only that current remap register state cannot be read but also that
+ * a read-modify-write operation cannot be performed on the register.
+ *
+ * This should not present a problem in most use case scenarios except for the
+ * case where a current MPU address space mapping of 0 to SDRAM is being changed
+ * to to a mapping of 0 to Boot ROM or OCRAM.
+ *
+ * In this case, a two step process whereby the L3 remap register is first set
+ * to the new desired MPU address 0 mapping and then the L2 cache address
+ * filtering registers have their address ranges adjusted accordingly must be
+ * followed. An example follows:
+\verbatim
+// 1 MB reset default value for address filtering start
+#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
+uint32_t addr_filt_start;
+uint32_t addr_filt_end;
+
+// Perform L3 remap register programming first by setting the desired new MPU
+// address space 0 mapping. Assume OCRAM for the example.
+alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
+
+// Next, adjust the L2 cache address filtering range. Set the start address to
+// the default reset value and retain the existing end address configuration.
+alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
+if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
+{
+    alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
+}
+\endverbatim
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the MPU address space attributes.
+ *
+ * The MPU address space consists of the ARM Cortex A9 processors and associated
+ * processor peripherals (cache, MMU).
+ */
+typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
+{
+    ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,     /*!< Maps the Boot ROM to address
+                                             *   0x0 for the MPU L3 master. Note
+                                             *   that the Boot ROM is also
+                                             *   always mapped to address
+                                             *   0xfffd_0000 for the MPU L3
+                                             *   master independent of
+                                             *   attribute.
+                                             */
+
+    ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM        /*!< Maps the On-chip RAM to address
+                                             *   0x0 for the MPU L3 master. Note
+                                             *   that the On-chip RAM is also
+                                             *   always mapped to address
+                                             *   0xffff_0000 for the MPU L3
+                                             *   master independent of this
+                                             *   attribute.
+                                             */
+} ALT_ADDR_SPACE_MPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the non-MPU address space attributes.
+ *
+ * The non-MPU address space consists of the non-MPU L3 masters including the
+ * DMA controllers (standalone and those built into peripherals), the F2H AXI
+ * Bridge, and the DAP.
+ */
+typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
+{
+    ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,    /*!< Maps the SDRAM to address 0x0
+                                             *   for the non-MPU L3 masters.
+                                             */
+    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM     /*!< Maps the On-chip RAM to address
+                                             *   0x0 for the non-MPU L3
+                                             *   masters. Note that the On-chip
+                                             *   RAM is also always mapped to
+                                             *   address 0xffff_0000 for the
+                                             *   non-MPU L3 masters independent
+                                             *   of this attribute.
+                                             */
+} ALT_ADDR_SPACE_NONMPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the HPS to FPGA bridge accessiblity
+ * attributes.
+ */
+typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
+{
+    ALT_ADDR_SPACE_H2F_INACCESSIBLE,        /*!< The H2F AXI Bridge is not
+                                             *   visible to L3 masters. Accesses
+                                             *   to the associated address range
+                                             *   return an AXI decode error to
+                                             *   the master.
+                                             */
+    ALT_ADDR_SPACE_H2F_ACCESSIBLE           /*!< The H2F AXI Bridge is visible
+                                             *   to L3 masters.
+                                             */
+} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the Lightweight HPS to FPGA bridge
+ * accessiblity attributes.
+ */
+typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
+{
+    ALT_ADDR_SPACE_LWH2F_INACCESSIBLE,      /*!< The LWH2F AXI Bridge is not
+                                             *   visible to L3 masters. Accesses
+                                             *   to the associated address range
+                                             *   return an AXI decode error to
+                                             *   the master.
+                                             */
+    ALT_ADDR_SPACE_LWH2F_ACCESSIBLE         /*!< The LWH2F AXI Bridge is visible
+                                             *   to L3 masters.
+                                             */
+} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * Configures the mapped and accessible (visible) address ranges for the HPS
+ * MPU, non-MPU, and Bridge address spaces.
+ *
+ * \param       mpu_attr
+ *              The MPU address space configuration attributes.
+ *              
+ * \param       nonmpu_attr
+ *              The non-MPU address space configuration attributes.
+ *              
+ * \param       h2f_attr
+ *              The H2F Bridge attribute mapping and accessibility attributes.
+ *              
+ * \param       lwh2f_attr
+ *              The Lightweight H2F Bridge attribute mapping and accessibility
+ *              attributes.
+ *              
+ * 
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_INV_OPTION    One or more invalid attribute options were
+ *                                  specified.
+ */
+ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
+                                     ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
+                                     ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
+                                     ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
+
+/******************************************************************************/
+/*!
+ * Maps SDRAM to address 0x0 for the MPU address space view.
+ *
+ * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
+ * 64KB of the boot region are accessible because the size of the Boot ROM and
+ * on-chip RAM are only 64KB.  Addresses in the range 0x100000 (1MB) to
+ * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to
+ * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not
+ * accessible to the MPU unless address 0 is remapped to SDRAM after reset.
+ *
+ * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access
+ * SDRAM.
+ *
+ * \internal
+ * The remap to address 0x0 is achieved by configuring the L2 cache Address
+ * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
+ * AXI (M1) master port by calling:
+ *
+ * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
+ * 
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em>.
+ * \endinternal
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
+ *
+ * The L2 cache address filter controls where physical addresses within certain
+ * ranges of the MPU address space are directed.
+ *
+ * The L2 cache has master port connections to the L3 interconnect and the SDRAM
+ * controller. A programmable address filter controls which portions of the
+ * 32-bit physical address space use each master.
+ * 
+ * When l2 address filtering is configured and enabled, a physical address will
+ * be redirected to one master or the other based upon the address filter
+ * configuration.
+ *
+ * If \b address_filter_start <= \e physical_address < \b address_filter_end:
+ * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
+ * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
+ *
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the L2 cache address filtering configuration settings.
+ *
+ * \param       addr_filt_start
+ *              [out] An output parameter variable for the address filtering
+ *              start address for the range of physical addresses redirected to
+ *              the SDRAM AXI master port. The value returned is always a 1 MB
+ *              aligned address.
+ *              
+ * \param       addr_filt_end
+ *              [out] An output parameter variable for the address filtering
+ *              end address for the range of physical addresses redirected to
+ *              the SDRAM AXI master port. The value returned is always a 1 MB
+ *              aligned address.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An bad argument was passed. Either \e addr_filt_start
+ *                              or \e addr_filt_end or both are invalid addresses.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
+                                           uint32_t* addr_filt_end);
+
+/******************************************************************************/
+/*!
+ * Set the L2 cache address filtering configuration settings.
+ *
+ * Address filtering start and end values must be 1 MB aligned.
+ *
+ * \param       addr_filt_start
+ *              The address filtering start address for the range of physical
+ *              addresses redirected to the SDRAM AXI master port. Only bits
+ *              [31:20] of the address are valid. Any bits outside the range
+ *              [31:20] are invalid and will cause an error status to be
+ *              returned.
+ *              
+ * \param       addr_filt_end
+ *              The address filtering end address for the range of physical
+ *              addresses redirected to the SDRAM AXI master port. Only bits
+ *              [31:20] of the address are valid. Any bits outside the range
+ *              [31:20] are invalid and will cause an error status to be
+ *              returned.
+ *              
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ *                              more address arguments do not satisfy the argument
+ *                              constraints.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
+                                           uint32_t addr_filt_end);
+
+/*! @} */
+
+/*! @} */
+
+#endif  /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_ADDR_SPACE_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_bridge_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_bridge_manager.h
new file mode 100644
index 0000000..253d889
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_bridge_manager.h
@@ -0,0 +1,269 @@
+/*! \file
+ *  Altera - SoC FPGA FPGA/HPS Bridge Management
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_BRG_MGR_H__
+#define __ALT_BRG_MGR_H__
+
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************/
+/*! \addtogroup ALT_BRIDGE The AXI Bridge Manager
+ *
+ * The functions in this group manage access, configuration, and control of the
+ * AXI bridges between the FPGA and HPS.
+ * 
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the AXI bridge interfaces between the FPGA
+ * and HPS.
+ */
+typedef enum ALT_BRIDGE_e
+{
+    ALT_BRIDGE_F2H,             /*!< FPGA-to-HPS AXI bridge providing a
+                                 *   high-performance, statically configurable
+                                 *   width interface that gives the FPGA the
+                                 *   ability to:
+                                 *   * master transactions to slaves in the HPS
+                                 *   * have full visibility into the HPS address space
+                                 *   * access the coherent memory interface (ACP)
+                                 *
+                                 *   The width (32/64/128 bits) of this bridge
+                                 *   is statically configurable at design time
+                                 *   using \e Quartus.
+                                 */
+    ALT_BRIDGE_H2F,             /*!< HPS-to-FPGA AXI bridge providing a
+                                 *   statically configurable width,
+                                 *   high-performance master interface to the
+                                 *   FPGA fabric. The bridge provides a 1GB
+                                 *   address space and gives any master in the
+                                 *   HPS system access to logic, peripherals,
+                                 *   and memory implemented in the FPGA.
+                                 */
+    ALT_BRIDGE_LWH2F            /*!< Lightweight HPS-to-FPGA AXI bridge
+                                 *   providing a secondary, fixed-width, smaller
+                                 *   address space, lower-performance master
+                                 *   interface to the FPGA fabric. The bridge
+                                 *   provides a 2MB address space and gives any
+                                 *   master in the HPS access to logic,
+                                 *   peripherals, and memory implemented in the
+                                 *   FPGA fabric. The bridge master exposed to
+                                 *   the FPGA fabric has a fixed data width of
+                                 *   32 bits.
+                                 *
+                                 *   The bridge provides clock crossing logic to
+                                 *   allow the logic in the FPGA to run
+                                 *   asynchronous to the HPS. The bridge
+                                 *   simplifies the process of connecting the
+                                 *   HPS to soft logic. Soft logic can even be
+                                 *   designed to support only a subset of the
+                                 *   full AXI protocol that the bridge
+                                 *   supports. Use the lightweight HPS-to-FPGA
+                                 *   bridge for high-latency, low-bandwidth
+                                 *   traffic, such as memory-mapped register
+                                 *   accesses of FPGA peripherals. This approach
+                                 *   diverts traffic from the high-performance
+                                 *   HPS-to-FPGA bridge, which can improve
+                                 *   overall performance.
+                                 */
+} ALT_BRIDGE_t;
+
+/******************************************************************************/
+/*!
+ * Type definition for a callback function prototype used by the
+ * alt_bridge_init() bridge initialization function to determine whether the
+ * FPGA is ready to begin transactions across the bridge interface.
+ *
+ * The implementation of the callback function is user defined allowing the user
+ * to define a flexible signaling protocol for the FPGA to indicate its
+ * readiness to begin transactions across the initialized bridge interface.
+ *
+ * The range of values returned by the callback function may be extended per the
+ * user defined FPGA readiness signaling protocol but any return value other
+ * than ALT_E_SUCCESS will be interpreted by the alt_bridge_init() bridge
+ * initialization function as an indication that the FPGA is not ready to
+ * commence bridge interface transactions.
+ *
+ * \param       user_arg
+ *              This is a user defined parameter available to pass additional
+ *              data that might be needed to support the user defined FPGA
+ *              readiness signaling protocol.
+ *
+ * \retval      ALT_E_SUCCESS   The FPGA is ready to commence bridge interface 
+ *                              transactions.
+ * \retval      ALT_E_ERROR     An error has occurred. The FPGA is not ready to
+ *                              commence bridge interface transactions.
+ * \retval      ALT_E_TMO       The FPGA failed to signal a ready to commence
+ *                              bridge interface transactions indication before
+ *                              the response timeout period expired.
+ */
+typedef ALT_STATUS_CODE (*alt_bridge_fpga_is_ready_t)(void* user_arg);
+
+/******************************************************************************/
+/*!
+ * Initialize the bridge for bus transactions by bringing up the interface in a
+ * safe, controlled sequence.
+ *
+ * The following actions are performed as part of the process of initializing
+ * the bridge interface for transactions:
+ *
+ * * Sets and holds bridge interface in reset.
+ * * Ensures that the bridge interface is ready by asserting that:
+ *   - FPGA is powered and configured (i.e. in USER mode).
+ *   - Bridge interface clock is ready and stable.
+ *   - FPGA soft IP is ready for transactions across the bridge interface.
+ * * Releases bridge interface from reset.
+ *
+ * The mechanism used by alt_bridge_init() to determine whether the FPGA soft IP
+ * is ready to begin bus transactions across the interface is the user defined
+ * callback \e fpga_is_ready.
+ *
+ * \internal
+ * This process of software controlled bring-up of HPS/FPGA interfaces is
+ * detailed in <em> Hammerhead-P HPS FPGA Interface NPP, Section 4 Software
+ * Bring-up/Tear-down</em>.
+ * \endinternal
+ *
+ * \param       bridge
+ *              The bridge interface to initialize.
+ *
+ * \param       fpga_is_ready
+ *              A pointer to a user defined callback function to determine
+ *              whether the FPGA is ready to commence bridge interface
+ *              transactions. If NULL is passed, then bridge interface
+ *              initialization proceeds without making a determination of
+ *              whether the FPGA is ready to commence bridge interface
+ *              transactions or not.
+ *
+ * \param       user_arg
+ *              A user defined argument value for passing support data to the \e
+ *              fpga_is_ready callback function.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_bridge_init(ALT_BRIDGE_t bridge,
+                                alt_bridge_fpga_is_ready_t fpga_is_ready,
+                                void* user_arg);
+
+/******************************************************************************/
+/*!
+ * Type definition for a callback function prototype used by the
+ * alt_bridge_uninit() function to conduct a handshake protocol with the FPGA
+ * notifying it that the bridge interface is being taken down.
+ *
+ * The callback function implementation is user defined and allows the user to
+ * implement a flexible handshake notification protocol with the FPGA to allow
+ * an orderly interface shutdown prior to the bridge being taken down.
+ *
+ * The handshake protocol is user defined but normally consists of two parts:
+ * * The processor notifies the FPGA soft IP that the bridge interface is being
+ *   taken down. The notification mechanism used to signal the FPGA is user
+ *   defined.
+ * * The process waits for an acknowledgement response from the FPGA.
+ *
+ * The range of return values for the callback function may be extended per the
+ * user defined handshake notification protocol but any return value other than
+ * ALT_E_SUCCESS will be interpreted by the alt_bridge_uninit() function as an
+ * indication that the handshake protocol was unsuccessful.
+ *
+ * \param       user_arg
+ *              This is a user defined parameter available to pass additional
+ *              data that might be needed to support the user defined handshake
+ *              notification protocol.
+ *
+ * \retval      ALT_E_SUCCESS   The handshake notification protocol was successful.
+ * \retval      ALT_E_ERROR     An error has occurred. The handshake notification 
+ *                              protocol was unsuccessful.
+ * \retval      ALT_E_TMO       The handshake notification protocol failed
+ *                              because a response timeout period expired.
+ */
+typedef ALT_STATUS_CODE (*alt_bridge_teardown_handshake_t)(void* user_arg);
+
+/******************************************************************************/
+/*!
+ * Uninitialize the bridge by tearing down the interface in a safe and
+ * controlled sequence.
+ *
+ * The process of taking down the bridge interface entails:
+ * * Optional: Conduct teardown handshake notification protocol 
+ *   - Bridge Manager informs FPGA that the bridge interface is being torn down.
+ *   - Bridge Manager waits for FPGA response to notification.
+ * * Processor waits for the completion of outstanding transactions on the AXI
+ *   bridge. Note, that HPS has no mechanism to track outstanding AXI transactions;
+ *   this needs to be provided by the customer design.
+ * * Places and holds the bridge interface in reset.
+ *
+ * The mechanism used by alt_bridge_uninit() to initiate the handshake
+ * notification to the FPGA soft IP that the bridge interface is being taken
+ * down is the user defined \e handshake callback.
+ *
+ * \internal
+ * This function implements the software controlled tear-down procedure detailed
+ * in <em> Hammerhead-P HPS FPGA Interface NPP, Section 4 Software
+ * Bring-up/Tear-down</em>.
+ * \endinternal
+ *
+ * \param       bridge
+ *              The bridge interface to uninitialize.
+ *
+ * \param       handshake
+ *              A pointer to a user defined tear-down handshake protocol. If
+ *              NULL is passed, then the bridge interface take down proceeds
+ *              without conducting any handshake notification protocol.
+ *
+ * \param       user_arg
+ *              A user defined argument value for passing support data to the
+ *              \e teardown_hs callback function.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_bridge_uninit(ALT_BRIDGE_t bridge,
+                                  alt_bridge_teardown_handshake_t handshake,
+                                  void* user_arg);
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_BRG_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h
new file mode 100644
index 0000000..a5e8c92
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h
@@ -0,0 +1,95 @@
+/*! \file
+ *  Contains the definition of an opaque data structure that contains raw
+ *  configuration information for a clock group.
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_CLK_GRP_H__
+#define __ALT_CLK_GRP_H__
+
+#include "hwlib.h"
+#include "socal/alt_clkmgr.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/*! This type definition enumerates the clock groups
+*/
+typedef enum ALT_CLK_GRP_e
+{
+	ALT_MAIN_PLL_CLK_GRP,					/*!< Main PLL clock group */
+
+	ALT_PERIPH_PLL_CLK_GRP,					/*!< Peripheral PLL clock group */
+
+	ALT_SDRAM_PLL_CLK_GRP					/*!< SDRAM PLL clock group */
+
+} ALT_CLK_GRP_t;
+
+
+
+/*! This type definition defines an opaque data structure for holding the
+ *  configuration settings for a complete clock group.
+ */
+typedef struct ALT_CLK_GROUP_RAW_CFG_s
+{
+    uint32_t      			  verid;		/*!< SoC FPGA version identifier. This field
+											*   encapsulates the silicon identifier and
+											*   version information associated with this
+											*   clock group configuration. It is used to
+											*   assert that this clock group configuration
+											*   is valid for this device.
+											*/
+    uint32_t				  siliid2;		/*!< Reserved register - reserved for future
+     	 	 	 	 	 	 	 	 	 	*	 device IDs or capability flags/
+     	 	 	 	 	 	 	 	 	 	*/
+    ALT_CLK_GRP_t     		  clkgrpsel;	/*!< Clock group union discriminator */
+
+
+    /*! This union holds the raw register values for configuration of the set of
+     *  possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
+     *  identifies the valid clock group union data member.
+     */
+    union ALT_CLK_GROUP_RAW_CFG_u
+    {
+        ALT_CLKMGR_MAINPLL_t  mainpllgrp;   /*!< Raw clock group configuration for Main PLL group */
+        ALT_CLKMGR_PERPLL_t   perpllgrp;    /*!< Raw clock group configuration for Peripheral PLL group */
+        ALT_CLKMGR_SDRPLL_t   sdrpllgrp;    /*!< Raw clock group configuration for SDRAM PLL group */
+    } clkgrp;
+} ALT_CLK_GROUP_RAW_CFG_t;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_CLK_GRP_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h
new file mode 100644
index 0000000..7cf0e12
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h
@@ -0,0 +1,1431 @@
+/*! \file
+ *  Contains definitions for the Altera Hardware Libraries Clock Manager
+ *  Application Programming Interface
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_CLK_MGR_H__
+#define __ALT_CLK_MGR_H__
+
+#include "hwlib.h"
+#include "alt_clock_group.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*! \addtogroup CLK_MGR The Clock Manager API
+ *
+ * This module defines the Clock Manager API for accessing, configuring, and
+ * controlling the HPS clock resources.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition is an opaque type definition for clock frequency values
+ * in Hz.
+ */
+typedef uint32_t    alt_freq_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the names of the clock and PLL resources
+ * managed by the Clock Manager.
+ */
+typedef enum ALT_CLK_e
+{
+    /* Clock Input Pins */
+    ALT_CLK_IN_PIN_OSC1,
+                                        /*!< \b OSC_CLK_1_HPS
+                                         *   External oscillator input:
+                                         *   * Input Pin
+                                         *   * Clock source to Main PLL
+                                         *   * Clock source to SDRAM PLL
+                                         *     and Peripheral PLL if selected via
+                                         *     register write
+                                         *   * Clock source for clock in safe mode
+                                         */
+
+    ALT_CLK_IN_PIN_OSC2,
+                                        /*!< \b OSC_CLK_2_HPS
+                                         *   External Oscillator input:
+                                         *   * Input Pin
+                                         *   * Optional clock source to SDRAM PLL 
+                                         *     and Peripheral PLL if selected
+                                         *   * Typically used for Ethernet
+                                         *     reference clock
+                                         */
+
+
+    /* FPGA Clock Sources External to HPS */
+    ALT_CLK_F2H_PERIPH_REF,
+                                        /*<! Alternate clock source from FPGA
+                                         * for HPS Peripheral PLL. */
+
+    ALT_CLK_F2H_SDRAM_REF,
+                                        /*<! Alternate clock source from FPGA
+                                         * for HPS SDRAM PLL. */
+
+
+    /* Other Clock Sources External to HPS */
+    ALT_CLK_IN_PIN_JTAG,
+                                        /*!< \b JTAG_TCK_HPS
+                                         *   * Input Pin
+                                         *   * External HPS JTAG clock input.
+                                         */
+
+    ALT_CLK_IN_PIN_ULPI0,
+                                        /*!< \b ULPI0_CLK
+                                         *   ULPI Clock provided by external USB0
+                                         *   PHY
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_ULPI1,
+                                        /*!< \b ULPI1_CLK
+                                         *   ULPI Clock provided by external USB1
+                                         *   PHY
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_EMAC0_RX,
+                                        /*!< \b EMAC0:RX_CLK
+                                         *   Rx Reference Clock for EMAC0
+                                         *   * Input Pin
+                                         */
+
+    ALT_CLK_IN_PIN_EMAC1_RX,
+                                        /*!< \b EMAC1:RX_CLK
+                                         *   Rx Reference Clock for EMAC1
+                                         *   * Input Pin
+                                         */
+
+    
+    /* PLLs */
+    ALT_CLK_MAIN_PLL,
+                                        /*!< \b main_pll_ref_clkin
+                                         *   Main PLL input reference clock,
+                                         *   used to designate the Main PLL in
+                                         *   PLL clock selections.
+                                         */
+
+    ALT_CLK_PERIPHERAL_PLL,
+                                        /*!< \b periph_pll_ref_clkin 
+                                         *   Peripheral PLL input reference
+                                         *   clock, used to designate the
+                                         *   Peripheral PLL in PLL clock
+                                         *   selections.
+                                         */
+
+    ALT_CLK_SDRAM_PLL,
+                                        /*!< \b sdram_pll_ref_clkin
+                                         *   SDRAM PLL input reference clock,
+                                         *   used to designate the SDRAM PLL in
+                                         *   PLL clock selections.
+                                         */
+
+    /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
+     * directly from the osc_clk_1_HPS pin */
+    ALT_CLK_OSC1,
+                                        /*!< \b osc1_clk
+                                         *   OSC1 Clock Group - The
+                                         *   OSC1 clock group contains
+                                         *   those clocks which are
+                                         *   derived directly from the
+                                         *   osc_clk_1_HPS pin.
+                                         *   * alias for ALT_CLK_IN_PIN_OSC1
+                                         */
+
+    /* Main Clock Group - The following clocks are derived from the Main PLL. */
+    ALT_CLK_MAIN_PLL_C0,
+                                        /*!< \b Main PLL C0 Output */
+
+    ALT_CLK_MAIN_PLL_C1,
+                                        /*!< \b Main PLL C1 Output */
+
+    ALT_CLK_MAIN_PLL_C2,
+                                        /*!< \b Main PLL C2 Output */
+
+    ALT_CLK_MAIN_PLL_C3,
+                                        /*!< \b Main PLL C3 Output */
+
+    ALT_CLK_MAIN_PLL_C4,
+                                        /*!< \b Main PLL C4 Output */
+
+    ALT_CLK_MAIN_PLL_C5,
+                                        /*!< \b Main PLL C5 Output */
+
+    ALT_CLK_MPU,
+                                        /*!< \b mpu_clk
+                                         *   Main PLL C0 Output. Clock for MPU
+                                         *   subsystem, including CPU0 and CPU1.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C0
+                                         */
+
+    ALT_CLK_MPU_L2_RAM,
+                                        /*!< \b mpu_l2_ram_clk
+                                         *   Clock for MPU level 2 (L2) RAM
+                                         */
+
+    ALT_CLK_MPU_PERIPH,
+                                        /*!< \b mpu_periph_clk
+                                         *   Clock for MPU snoop control unit
+                                         *   (SCU) peripherals, such as the
+                                         *   general interrupt controller (GIC)
+                                         */
+
+    ALT_CLK_L3_MAIN,
+                                        /*!< \b main_clk
+                                         *   Main PLL C1 Output
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C1
+                                         */
+
+    ALT_CLK_L3_MP,
+                                        /*!< \b l3_mp_clk
+                                         *   Clock for L3 Master Peripheral Switch
+                                         */
+
+    ALT_CLK_L3_SP,
+                                        /*!< \b l3_sp_clk
+                                         *   Clock for L3 Slave Peripheral Switch
+                                         */
+
+    ALT_CLK_L4_MAIN,
+                                        /*!< \b l4_main_clk
+                                         *   Clock for L4 main bus
+                                         *   * Clock for DMA
+                                         *   * Clock for SPI masters
+                                         */
+
+    ALT_CLK_L4_MP,
+                                        /*!< \b l4_mp_clk
+                                         *   Clock for L4 master peripherals (MP) bus
+                                         */
+
+    ALT_CLK_L4_SP,
+                                        /*!< \b l4_sp_clk
+                                         *   Clock for L4 slave peripherals (SP) bus 
+                                         */
+
+    ALT_CLK_DBG_BASE,
+                                        /*!< \b dbg_base_clk
+                                         *   Main PLL C2 Output
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C2
+                                         */
+
+    ALT_CLK_DBG_AT,
+                                        /*!< \b dbg_at_clk
+                                         *   Clock for CoreSight debug Advanced
+                                         *   Microcontroller Bus Architecture
+                                         *   (AMBA) Trace Bus (ATB)
+                                         */
+
+    ALT_CLK_DBG_TRACE,
+                                        /*!< \b dbg_trace_clk
+                                         *   Clock for CoreSight debug Trace
+                                         *   Port Interface Unit (TPIU)
+                                         */
+
+    ALT_CLK_DBG_TIMER,
+                                        /*!< \b dbg_timer_clk
+                                         *   Clock for the trace timestamp
+                                         *   generator
+                                         */
+
+    ALT_CLK_DBG,
+                                        /*!< \b dbg_clk
+                                         *   Clock for Debug Access Port (DAP)
+                                         *   and debug Advanced Peripheral Bus
+                                         *   (APB)
+                                         */
+
+    ALT_CLK_MAIN_QSPI,
+                                        /*!< \b main_qspi_clk
+                                         *   Main PLL C3 Output. Quad SPI flash
+                                         *   internal logic clock.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C3
+                                         */
+
+    ALT_CLK_MAIN_NAND_SDMMC,
+                                        /*!< \b main_nand_sdmmc_clk 
+                                         *   Main PLL C4 Output. Input clock to
+                                         *   flash controller clocks block.
+                                         *   * Alias for \e ALT_CLK_MAIN_PLL_C4
+                                         */
+
+    ALT_CLK_CFG,
+                                        /*!< \b cfg_clk 
+                                         *   FPGA manager configuration clock.
+                                         */
+
+    ALT_CLK_H2F_USER0,
+                                        /*!< \b h2f_user0_clock
+                                         *   Clock to FPGA fabric
+                                         */
+
+    
+    /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
+    ALT_CLK_PERIPHERAL_PLL_C0,
+                                        /*!< \b Peripheral PLL C0 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C1,
+                                        /*!< \b Peripheral PLL C1 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C2,
+                                        /*!< \b Peripheral PLL C2 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C3,
+                                        /*!< \b Peripheral PLL C3 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C4,
+                                        /*!< \b Peripheral PLL C4 Output */
+
+    ALT_CLK_PERIPHERAL_PLL_C5,
+                                        /*!< \b Peripheral PLL C5 Output */
+
+    ALT_CLK_USB_MP,
+                                        /*!< \b usb_mp_clk
+                                         *   Clock for USB
+                                         */
+
+    ALT_CLK_SPI_M,
+                                        /*!< \b spi_m_clk
+                                         *   Clock for L4 SPI master bus
+                                         */
+
+    ALT_CLK_QSPI,
+                                        /*!< \b qspi_clk
+                                         *   Clock for Quad SPI
+                                         */
+
+    ALT_CLK_NAND_X,
+                                        /*!< \b nand_x_clk
+                                         *   NAND flash controller master and
+                                         *   slave clock
+                                         */
+
+    ALT_CLK_NAND,
+                                        /*!< \b nand_clk
+                                         *   Main clock for NAND flash
+                                         *   controller
+                                         */
+
+    ALT_CLK_SDMMC,
+                                        /*!< \b sdmmc_clk
+                                         *   Clock for SD/MMC logic input clock
+                                         */
+
+    ALT_CLK_EMAC0,
+                                        /*!< \b emac0_clk
+                                         *   EMAC 0 clock - Peripheral PLL C0
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0
+                                         */
+
+    ALT_CLK_EMAC1,
+                                        /*!< \b emac1_clk
+                                         *   EMAC 1 clock - Peripheral PLL C1
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1
+                                         */
+
+    ALT_CLK_CAN0,
+                                        /*!< \b can0_clk
+                                         *   Controller area network (CAN)
+                                         *   controller 0 clock
+                                         */
+
+    ALT_CLK_CAN1,
+                                        /*!< \b can1_clk
+                                         *   Controller area network (CAN)
+                                         *   controller 1 clock
+                                         */
+
+    ALT_CLK_GPIO_DB,
+                                        /*!< \b gpio_db_clk
+                                         *   Debounce clock for GPIO0, GPIO1,
+                                         *   and GPIO2
+                                         */
+
+    ALT_CLK_H2F_USER1,
+                                        /*!< \b h2f_user1_clock
+                                         *   Clock to FPGA fabric - Peripheral
+                                         *   PLL C5 Output
+                                         *   * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5
+                                         */
+
+
+    /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
+    ALT_CLK_SDRAM_PLL_C0,
+                                        /*!< \b SDRAM PLL C0 Output */
+
+    ALT_CLK_SDRAM_PLL_C1,
+                                        /*!< \b SDRAM PLL C1 Output */
+
+    ALT_CLK_SDRAM_PLL_C2,
+                                        /*!< \b SDRAM PLL C2 Output */
+
+    ALT_CLK_SDRAM_PLL_C3,
+                                        /*!< \b SDRAM PLL C3 Output */
+
+    ALT_CLK_SDRAM_PLL_C4,
+                                        /*!< \b SDRAM PLL C4 Output */
+
+    ALT_CLK_SDRAM_PLL_C5,
+                                        /*!< \b SDRAM PLL C5 Output */
+
+    ALT_CLK_DDR_DQS,
+                                        /*!< \b ddr_dqs_clk
+                                         *   Clock for MPFE, single-port
+                                         *   controller, CSR access, and PHY -
+                                         *   SDRAM PLL C0 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C0
+                                         */
+
+    ALT_CLK_DDR_2X_DQS,
+                                        /*!< \b ddr_2x_dqs_clk
+                                         *    Clock for PHY - SDRAM PLL C1 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C1
+                                         */
+
+    ALT_CLK_DDR_DQ,
+                                        /*!< \b ddr_dq_clk
+                                         *   Clock for PHY - SDRAM PLL C2 Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C2
+                                         */
+
+    ALT_CLK_H2F_USER2,
+                                        /*!< \b h2f_user2_clock
+                                         *   Clock to FPGA fabric - SDRAM PLL C5
+                                         *   Output
+                                         *   * Alias for \e ALT_CLK_SDRAM_PLL_C5
+                                         */
+
+    /* Clock Output Pins */
+    ALT_CLK_OUT_PIN_EMAC0_TX,
+                                       /*!< \b EMAC0:TX_CLK
+                                        *   Tx Reference Clock for EMAC0
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_EMAC1_TX,
+                                       /*!< \b EMAC1:TX_CLK
+                                        *   Tx Reference Clock for EMAC1
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SDMMC,
+                                       /*!< \b SDMMC:CLK
+                                        *   SD/MMC Card Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C0_SCL,
+                                       /*!< \b I2C0:SCL
+                                        *   I2C Clock for I2C0
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C1_SCL,
+                                       /*!< \b I2C1:SCL
+                                        *   I2C Clock for I2C1
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C2_SCL,
+                                       /*!< \b I2C2:SCL
+                                        *   I2C Clock for I2C2/2 wire
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_I2C3_SCL,
+                                       /*!< \b I2C3:SCL
+                                        *   I2C Clock for I2C1/2 wire
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SPIM0,
+                                       /*!< \b SPIM0:CLK
+                                        *   SPI Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_SPIM1,
+                                       /*!< \b SPIM1:CLK
+                                        *   SPI Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_OUT_PIN_QSPI,
+                                       /*!< \b QSPI:CLK
+                                        *   QSPI Flash Clock
+                                        *   * Output Pin
+                                        */
+
+    ALT_CLK_UNKNOWN
+} ALT_CLK_t;
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_STATUS Clock Manager Status
+ *
+ * This functional group provides status information on various aspects and
+ * properties of the Clock Manager state.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition defines the lock condition status codes for each of the
+ * PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable())
+ * then it contributes to the overall \b clkmgr_IRQ signal assertion state.
+ */
+typedef enum ALT_CLK_PLL_LOCK_STATUS_e
+{
+    ALT_MAIN_PLL_LOCK_ACHV    = 0x00000001, /*!< This condition is set if the Main
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_PERIPH_PLL_LOCK_ACHV  = 0x00000002, /*!< This condition is set if the Peripheral
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_SDR_PLL_LOCK_ACHV     = 0x00000004, /*!< This condition is set if the SDRAM
+                                             *   PLL has achieved lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_MAIN_PLL_LOCK_LOST    = 0x00000008, /*!< This condition is set if the Main
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_PERIPH_PLL_LOCK_LOST  = 0x00000010, /*!< This condition is set if the Peripheral
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+    ALT_SDR_PLL_LOCK_LOST     = 0x00000020  /*!< This condition is set if the SDRAM
+                                             *   PLL has lost lock at least once
+                                             *   since this condition was last
+                                             *   cleared.
+                                             */
+} ALT_CLK_PLL_LOCK_STATUS_t;
+
+/******************************************************************************/
+/*!
+ * Clear the selected PLL lock status conditions.
+ *
+ * This function clears assertions of one or more of the PLL lock status
+ * conditions.
+ *
+ * NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source
+ * assertion conditions.
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to clear. \e lock_stat_mask 
+ *              is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t
+ *              values designating the PLL lock conditions to clear.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Returns the PLL lock status condition values.
+ *
+ * This function returns the value of the PLL lock status conditions.
+ *
+ * \returns The current values of the PLL lock status conditions as defined by
+ * the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set
+ * then the condition is asserted.
+ */
+uint32_t alt_clk_lock_status_get(void);
+
+/******************************************************************************/
+/*!
+ * Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE
+ * otherwise.
+ *
+ * \param       pll
+ *              The PLL to return the lock status of.
+ *
+ * \retval      ALT_E_TRUE      The specified PLL is currently locked.
+ * \retval      ALT_E_FALSE     The specified PLL is currently not locked.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
+ *                              value.
+ * \internal
+ * NOTE: This function uses the
+ *       * \b hps::clkmgr::inter::mainplllocked
+ *       * \b hps::clkmgr::inter::perplllocked, 
+ *       * \b hps::clkmgr::inter::sdrplllocked
+ *
+ *       bits to determine if the PLL is locked or not.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options
+ *
+ * When safe mode is enabled, clocks in the HPS are directly generated from the
+ * \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode
+ * request from the reset manager or by a cold reset. Assertion of the safe mode
+ * request from the reset manager sets the safe mode bit in the clock manager
+ * control register. No other control register bits are affected by the safe
+ * mode request from the reset manager.
+ * 
+ * While in safe mode, clock manager register settings which control clock
+ * behavior are not changed. However, the output of the registers which control
+ * the clock manager state are forced to the safe mode values such that the
+ * following conditions occur:
+ * * All PLLs are bypassed to the \b osc1_clk clock, including their counters.
+ * * Clock dividers select their default reset values.
+ * * The flash controllers source clock selections are set to the peripheral 
+ *   PLL.
+ * * All clocks are enabled.
+ * * Safe mode is optionally applied to debug clocks.
+ * 
+ * A write by software is the only way to clear the safe mode bit. All registers
+ * and clocks need to be configured correctly and all software-managed clocks
+ * need to be gated off before clearing safe mode. Software can then gate clocks
+ * on as required.
+ * 
+ * On cold reset, all clocks are put in safe mode.
+ * 
+ * On warm reset, safe mode is optionally and independently applied to debug
+ * clocks and normal (i.e.non-debug) clocks based on clock manager register
+ * settings. The default response for warm reset is to put all clocks in safe
+ * mode.
+ * 
+ * The APIs in this group provide control of the Clock Manager safe mode warm
+ * reset response behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the safe mode clock domains under control of
+ * the Clock Manager.
+ */
+typedef enum ALT_CLK_SAFE_DOMAIN_e
+{
+    /*!
+     * This enumeration literal specifies the normal safe mode domain. The
+     * normal domain consists of all clocks except debug clocks.
+     */ 
+    ALT_CLK_DOMAIN_NORMAL,
+    /*!
+     * This enumeration literal specifies the debug safe mode domain. The debug
+     * domain consists of all debug clocks.
+     */ 
+    ALT_CLK_DOMAIN_DEBUG
+} ALT_CLK_SAFE_DOMAIN_t;
+
+/******************************************************************************/
+/*!
+ * Clear the safe mode status of the Clock Manager following a reset.
+ *
+ * NOTE: Safe mode should only be cleared once clocks have been correctly
+ * configured.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified safe mode clock domain is in safe mode or not.
+ *
+ * \param       clk_domain
+ *              The safe mode clock domain to check whether in safe mode or not.
+ *
+ * \retval      TRUE            The safe mode clock domain is in safe mode.
+ * \retval      FALSE           The safe mode clock domain is not in safe mode.
+ */
+bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control
+ *
+ * When a PLL is in bypass, the PLL clock logic is kept in reset. In this
+ * manner, the PLL clock can be free running while it stabilizes and achieves
+ * lock. The bypass logic isolates PLL configuration registers from the clock
+ * while changes are made to the PLL settings.
+ *
+ * The bypass controls are used by software to change the source clock input
+ * reference (for Peripheral and SDRAM PLLs) and is recommended when changing
+ * settings that may affect the ability of the VCO to maintain lock.  When a PLL
+ * is taken in or out of bypass the PLL output clocks will pause momentarily
+ * while the clocks are in transition, There will be no glitches or clocks
+ * shorter than the either the old or the new clock period.
+ *
+ * In summary, the PLL bypass controls permit:
+ * * Each PLL to be individually bypassed.
+ * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs 
+ *   reference clock input source reference clock selection.
+ * * Isolation of a the PLL VCO frequency registers (multiplier and divider),
+     phase shift registers (negative phase) , and post scale counters.
+ * * Glitch free clock transitions.
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable bypass mode for the specified PLL. This operation takes the PLL out
+ * of bypass mode.
+ *
+ * \param       pll
+ *              The PLL to take out of bypass mode.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument specified a non PLL clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Enable bypass mode for the specified PLL.
+ *
+ * \param       pll
+ *              The PLL to put into bypass mode.
+ *
+ * \param       use_input_mux
+ *              If TRUE then use the PLLs reference clock input source selection
+ *              to directly drive the bypass clock. If FALSE then use bypass
+ *              clock directly driven by the \b osc1_clk.
+ *
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_BAD_ARG       The \e pll argument specified a non PLL
+ *                                  clock value.
+ * \retval      ALT_E_INV_OPTION    TRUE is an invalid option for
+ *                                  \e use_input_mux with the \e pll selection.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
+                                          bool use_input_mux);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified PLL is in bypass or not.
+ *
+ * \internal 
+ * This function must also test the \b clkmgr.ctrl.safemode bit in
+ * addition to the PLLs bypass bit to tell whether the bypass mode is
+ * effect or not.
+ * \endinternal
+ *
+ * \param       pll
+ *              The PLL to check whether in bypass mode or not.
+ *
+ * \retval      ALT_E_TRUE      The PLL is in bypass mode.
+ * \retval      ALT_E_FALSE     The PLL is not in bypass mode.
+ * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GATE Clock Gating Control
+ *
+ * This functional group provides gating control of selected clock signals.
+ *
+ * When a clock is enabled, then its clock signal propogates to its respective
+ * clocked IP block(s).  When a clock is disabled, then its clock signal is
+ * prevented from propogating to its respective clocked IP block(s).
+ *
+ * The following clocks may be gated:
+ *
+ * * Main PLL Group
+ *   - l4_main_clk
+ *   - l3_mp_clk
+ *   - l4_mp_clk
+ *   - l4_sp_clk
+ *   - dbg_at_clk
+ *   - dbg_clk
+ *   - dbg_trace_clk
+ *   - dbg_timer_clk
+ *   - cfg_clk
+ *   - s2f_user0_clk
+ *
+ * * SDRAM PLL Group
+ *   - ddr_dqs_clk
+ *   - ddr_2x_clk
+ *   - ddr_dq_clk
+ *   - s2f_user2_clk
+ *
+ * * Peripheral PLL Group
+ *   - emac0_clk
+ *   - emac1_clk
+ *   - usb_mp_clk
+ *   - spi_m_clk
+ *   - can0_clk
+ *   - can1_clk
+ *   - gpio_db_clk
+ *   - s2f_user1_clk
+ *   - sdmmc_clk
+ *   - nand_clk
+ *   - nand_x_clk
+ *   - qspi_clk
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable the specified clock. Once the clock is disabled, its clock signal does
+ * not propogate to its clocked elements.
+ *
+ * \param       clk
+ *              The clock to disable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Enable the specified clock. Once the clock is enabled, its clock signal
+ * propogates to its elements.
+ *
+ * \param       clk
+ *              The clock to enable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified clock is enabled or not.
+ *
+ * \param       clk
+ *              The clock to check whether enabled or not.
+ *
+ * \retval      ALT_E_TRUE      The clock is enabled.
+ * \retval      ALT_E_FALSE     The clock is not enabled.
+ * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
+ *                              value.
+ */
+ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection
+ *
+ * This API group provide access and control to the input reference clock source
+ * selection for a clock or PLL.
+ *
+ * \internal
+ * These are the clocks that have software configurable input reference clock
+ * source selection available. Each clock below is listed with its valid
+ * input reference clock source selections.
+ *
+ * + Valid reference clock input selections for \b sdram_pll_ref_clkin
+ *   - osc_clk_1
+ *   - osc_clk_2
+ *   - f2h_sdram_ref_clk
+ *
+ * + Valid reference clock input selections for \b periph_pll_ref_clkin
+ *   - osc_clk_1
+ *   - osc_clk_2,
+ *   - f2h_periph_ref_clk
+ *
+ * + Valid reference clock input selections for \b l4_mp_clk
+ *   - periph_base_clk
+ *   - main_clk
+ *
+ * + Valid reference clock input selections for \b l4_sp_clk
+ *   - periph_base_clk
+ *   - main_clk
+ *
+ * + Valid reference clock input selections for \b sdmmc_clk
+ *   - f2h_periph_ref_clk
+ *   - main_nand_sdmmc_clk
+ *   - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b nand_clk
+ *   - f2h_periph_ref_clk
+ *   - main_nand_sdmmc_clk
+ *   - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b qspi_clk
+ *   - f2h_periph_ref_clk
+ *   - main_qspi_clk
+ *   - periph_qspi_clk
+ *
+ * \endinternal
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Get the input reference clock source selection value for the specified clock
+ * or PLL.
+ *
+ * NOTE: This function returns a clock value even though \e clk may specify a 
+ *       clock that does not have a selectable input reference clock source. In 
+ *       this case, the clock value returned is the static clock source for the 
+ *       specified clock. For example calling alt_clk_source_get() with \e clk
+ *       set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1.
+ *       
+ * \param       clk
+ *              The clock or PLL to retrieve the input reference clock source
+ *              selection value for.
+ *
+ * \returns     The clock's currently selected input reference clock source.
+ */
+ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Set the specified clock's input reference clock source selection.
+ *
+ * \param       clk
+ *              The clock or PLL to set the input reference clock source
+ *              selection for.
+ *
+ * \param       ref_clk
+ *              The input reference clock source selection value.
+ *
+ * \retval      ALT_E_SUCCESS       The operation was succesful.
+ * \retval      ALT_E_ERROR         The operation failed.
+ * \retval      ALT_E_BAD_ARG       The \e clk argument designates a clock that 
+ *                                  does not have a selectable input reference 
+ *                                  clock source.
+ * \retval      ALT_E_INV_OPTION    The \e ref_clk argument designates a clock that 
+ *                                  is an invalid reference clock source for the 
+ *                                  specified clock.
+ */
+ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, 
+                                   ALT_CLK_t ref_clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_FREQ Clock Frequency Control
+ *
+ * This API group provides access and control of the output frequency of a clock
+ * or PLL.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Set the external clock frequency value.
+ *
+ * The function is used to specify the frequency of the external clock source as
+ * a measure of Hz. The supplied frequency should be within the Fmin and Fmax
+ * values allowed for the external clock source.
+ *
+ * \param       clk
+ *              The external clock source. Valid external clocks are
+ *              * \e ALT_CLK_OSC1
+ *              * \e ALT_CLK_OSC2
+ *              * \e ALT_CLK_F2H_PERIPH_REF
+ *              * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \param       freq
+ *              The frequency of the external clock in Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either the \e clk
+ *                              argument is bad or not a valid external clock 
+ *                              source
+ * \retval      ALT_E_ARG_RANGE The frequency value violates the range constraints
+ *                              for the specified clock.
+
+ */
+ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
+                                         alt_freq_t freq);
+
+/******************************************************************************/
+/*!
+ * Get the external clock frequency value.
+ *
+ * This function returns the frequency of the external clock source as
+ * a measure of Hz.
+ *
+ * \param       clk
+ *              The external clock source. Valid external clocks are
+ *              * \e ALT_CLK_OSC1
+ *              * \e ALT_CLK_OSC2
+ *              * \e ALT_CLK_F2H_PERIPH_REF
+ *              * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \retval      freq
+ *              The frequency of the external clock in Hz.
+ *
+ */
+alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * This type definition defines a structure to contain the generalized
+ * configuration settings for a PLL.
+ */
+typedef struct ALT_CLK_PLL_CFG_s
+{
+    ALT_CLK_t           ref_clk;        /*!< PLL Reference Clock Source */
+    uint32_t            mult;           /*!< VCO Frequency Configuration - 
+                                         *   Multiplier (M) value, range 1 to 4096
+                                         */
+    uint32_t            div;            /*!< VCO Frequency Configuration - 
+                                         *   Divider (N) value, range 1 to 64
+                                         */
+    uint32_t            cntrs[6];       /*!< Post-Scale Counters (C0 - C5) -
+                                         *   range 1 to 512
+                                         */
+    uint32_t            pshift[6];      /*!< Phase Shift - 1/8 (45 degrees) of
+    									 *   negative phase shift per increment,
+                                         *   range 0 to 4096
+                                         */
+} ALT_CLK_PLL_CFG_t;
+
+/******************************************************************************/
+/*!
+ * Get the current PLL configuration.
+ *
+ * \param       pll
+ *              The PLL to get the configuration from.
+ *
+ * \param       pll_cfg
+ *              [out] Pointer to an output parameter variable for the returned
+ *              PLL configuration.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
+                                    ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the PLL configuration using the configuration parameters specified in
+ * \e pll_cfg.
+ *
+ * \param       pll
+ *              The PLL to set the configuration for.
+ *
+ * \param       pll_cfg
+ *              Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired
+ *              PLL configuration.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
+                                    const ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Get the current PLL VCO frequency configuration.
+ *
+ * \param       pll
+ *              The PLL to get the VCO frequency configuration for.
+ *
+ * \param       mult
+ *              [out] Pointer to an output variable for the returned
+ *              configured PLL VCO multiplier (M) value.
+ *
+ * \param       div
+ *              [out] Pointer to an output variable for the returned
+ *              configured PLL VCO divider (N) value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
+                                        uint32_t* mult,
+                                        uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the PLL VCO frequency configuration using the supplied multiplier and
+ * divider arguments.
+ *
+ * \param       pll
+ *              The PLL to set the VCO frequency configuration for.
+ *
+ * \param       mult
+ *              The PLL VCO multiplier (M). Expected argument range 1 to 4096.
+ *
+ * \param       div
+ *              The PLL VCO divider (N). Expected argument range 1 to 64.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
+                                        uint32_t mult,
+                                        uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the VCO frequency of the specified PLL.
+ *
+ * \param       pll
+ *              The PLL to retrieve the VCO frequency from.
+ *
+ * \param       freq
+ *              [out] Pointer to the an output parameter variable to return the
+ *              PLL VCO frequency value. The frequency value is returned as a
+ *              measures of Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either
+ *                              the \e pll argument is invalid or a bad
+ *                              \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
+                                         alt_freq_t* freq);
+
+/******************************************************************************/
+/*!
+ * Get the PLL frequency guard band value.
+ *
+ * \param       pll
+ *              The PLL from which to return the current guard band value.
+ *
+ * \returns     The current guard band range in effect for the PLL.
+ */
+uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Set the PLL frequency guard band value.
+ *
+ * Once a PLL has achieved lock, any changes to the PLL VCO frequency that are
+ * within a specific guard band range (default value 20%) of the reference
+ * period should not cause the PLL to lose lock.
+ *
+ * Programmatic changes to the PLL frequency within this guard band range are
+ * permitted to be made without the risk of breaking lock during the transition
+ * to the new frequency.
+ *
+ * The clk_mgr_pll_guard_band_set() function changes the guard band from its
+ * current value to permit a more lenient or stringent policy to be in effect in
+ * the implementation of the functions configuring PLL VCO frequency. The
+ * rationale for changing the default guard band value might be to accommodate
+ * unexpected environmental conditions (noise, temperature, and other
+ * instability factors) that may affect the PLLs ability to maintain lock during
+ * a frequency change.
+ *
+ * \param       pll
+ *              The PLL to set the guard band value for.
+ *
+ * \param       guard_band
+ *              The guard band value. Value should be 0 <= \e guard_band <= 100.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_ARG_RANGE The guard band value violates its range constraint.
+ */
+ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
+                                           uint32_t guard_band);
+
+/******************************************************************************/
+/*!
+ * Get the configured divider value for the specified clock.
+ *
+ * This function is used to get the configured values of both internal and
+ * external clock dividers.  The internal divider (PLL counters C0-C5) values
+ * are retrieved by specifying the clock name that is the divider output
+ * (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n
+ * It returns the actual divider value, not the encoded bitfield stored
+ * in the register, due to the variety of different encodings.
+ *
+ * \param       clk
+ *              The clock divider to get the value from.
+ *
+ * \param       div
+ *              [out] Pointer to an output variable for the returned clock
+ *              divider value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An invalid clock argument was specified or a
+ *                              clock that does not have a divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
+                                    uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the divider value for the specified clock.
+ *
+ * This function is used to set the values of both internal and external clock
+ * dividers.  The internal divider (PLL counters C0-C5) values are set by
+ * specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is
+ * used to set the Main PLL C0 counter value).
+ *
+ * \param       clk
+ *              The clock divider to set the value for.
+ *
+ * \param       div
+ *              The clock divider value. NOTE: The valid range of clock divider
+ *              values depends on the clock being configured. This is the
+ *              real divisor ratio, not how the divisor is coded into the
+ *              register, and is always one or greater.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   An invalid clock argument was specified or a
+ *                              clock that does not have a divider.
+ * \retval      ALT_E_ARG_RANGE The divider value violates the range constraints
+ *                              for the clock divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
+                                    uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the output frequency of the specified clock.
+ *
+ * \param       clk
+ *              The clock to retrieve the output frequency from.
+ *
+ * \param       freq
+ *              [out] Pointer to the an output parameter variable to return the
+ *              clock output frequency value. The frequency value is returned as
+ *              a measures of Hz.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either
+ *                              the \e clk argument is invalid or a bad
+ *                              \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
+                                 alt_freq_t* freq);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management
+ *
+ * The functions in this group provide management of interrupts originating from
+ * the Clock Manager.
+ *
+ * The following interrupt request (IRQ) signals are sourced from the Clock
+ * Manager:
+ *
+ * * \b clkmgr_IRQ - Clock Manager lock status interrupt output.  The PLL lock 
+ *                   status interrupt is the logical \e OR of six interrupt
+ *                   sources defining the loss or achievement of lock status for
+ *                   each PLL. The six PLL lock status conditions are:
+ *                   - Main PLL Achieved Lock
+ *                   - Main PLL Lost Lock
+ *                   - Peripheral PLL Achieved Lock
+ *                   - Peripheral PLL Lost Lock
+ *                   - SDRAM PLL Achieved Lock
+ *                   - SDRAM PLL Lost Lock
+ *
+ *                   They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t.
+ *
+ *                   Each PLL lock condition may be individually disabled/enabled 
+ *                   as a contributor to the determination of the \b clkmgr_IRQ
+ *                   assertion status.
+ *
+ *                   The alt_clk_lock_status_clear() function is used to clear
+ *                   the PLL lock conditions causing the \b clkmgr_IRQ
+ *                   assertion.
+ *
+ * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the 
+ *                      MPU to "wake up" after a transition of the Main PLL into
+ *                      or out of bypass mode has been safely achieved. The need
+ *                      for the "wake up" notification is because the PLL clocks
+ *                      pause for a short number of clock cycles during bypass
+ *                      state transition. ARM recommeds that the CPUs are placed
+ *                      in standby if the clocks are ever paused.
+ *
+ * NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not
+ *        be part of the public API although clearly it has important utility in
+ *        implementing safe changes to PLL settings and transitions into and out
+ *        of bypass mode.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function disables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A set bit for a PLL lock status condition in the mask value does not
+ * have the effect of enabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_enable is used to enable PLL
+ * lock status source condition(s).
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to disable as interrupt
+ *              source contributors. \e lock_stat_mask is a mask of logically
+ *              OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ *              conditions to disable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function enables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any PLL lock status condition in the mask value does
+ * not have the effect of disabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_disable is used to disable
+ * PLL lock status source condition(s).
+ *
+ * \param       lock_stat_mask
+ *              Specifies the PLL lock status conditions to enable as interrupt
+ *              source contributors. \e lock_stat_mask is a mask of logically
+ *              OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ *              conditions to enable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e lock_stat_mask argument contains an
+ *                              unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration
+ *
+ * This API provides the ability to safely set the configuration of a clock
+ * group with a single function call.
+ *
+ * A clock group is defined as set of clocks and signals generated from a common
+ * PLL VCO. The PLL and its derived clocks are treated as a single clock
+ * group. The clocks sourced directly or indirectly from the PLL may or may not
+ * have these features:
+ * * Clock Gates
+ * * Clock Dividers
+ * * Clock Source Selection Options
+ *
+ * The use case for application of the Clock Group Configuration functions is the
+ * ability to safely configure an entire clock group from a known good clock
+ * group configuration using the run-time function alt_clk_group_cfg_raw_set().
+ *
+ * A known good clock group configuration may be generated by one of the
+ * following methods:
+ * 
+ * * As static design information generated by an ACDS clock configuration tool 
+ *   and passed to embedded software for dynamic loading.
+ * 
+ * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has
+ *   programmatically established a known good clock group configuration using
+ *   the clock manager API configuration functions.
+ * 
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the raw configuration state of the designated clock group.
+ *
+ * This function is used to capture the configuration state of the specified
+ * clock group in a private (raw) data structure.  The raw data structure may be
+ * saved and used later to restore the clock group configuration using
+ * alt_clk_group_cfg_raw_get().
+ *
+ * \param       clk_group
+ *              The clock group configuration to capture.
+ *
+ * \param       clk_group_raw_cfg
+ *              [out] A pointer to a private (raw) data structure to store the
+ *              captured clock group configuration.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_ERROR     Details about error status code
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
+                                          ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the clock group configuration.
+ *
+ * This function is used to safely set the configuration state of a clock
+ * group from a raw clock group configuration specification.  The raw clock
+ * group configuration specification may be a configuration previously 
+ * captured with alt_clk_group_cfg_raw_get() or a group clock configuration
+ * generated by an external utility.
+ *
+ * \param       clk_group_raw_cfg
+ *              A pointer to the specification to use in the configuration of
+ *              the clock group.
+ *
+ * \retval      ALT_E_SUCCESS       Successful status.
+ * \retval      ALT_E_ERROR         Details about error status code
+ * \retval      ALT_E_BAD_VERSION   The clock group configuration specification is
+ *                                  invalid for this device.
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+/*! @} */
+
+/*! @} */
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_CLK_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h
new file mode 100644
index 0000000..c5af9f2
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h
@@ -0,0 +1,940 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_DMA_H__
+#define __ALT_DMA_H__
+
+#include "hwlib.h"
+#include "alt_dma_common.h"
+#include "alt_dma_program.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA DMA Controller API
+ *
+ * This module defines the API for configuration and use of the general purpose
+ * DMA controller for the SoC. The DMA controller is an instance of the ARM
+ * Corelink DMA Controller (DMA-330).
+ *
+ * References:
+ *  * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference
+ *    Manual.
+ *  * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink
+ *    DMA Controller DMA-330.
+ *  * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System
+ *    Technical Reference Manual, DMA Controller.
+ *
+ * @{
+ */
+
+/*!
+ * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status
+ *
+ * This API provides functions for configuration, control, and status queries
+ * of the DMA controller.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the operational states that the DMA manager
+ * may have.
+ */
+typedef enum ALT_DMA_MANAGER_STATE_e
+{
+    ALT_DMA_MANAGER_STATE_STOPPED     = 0, /*!< Stopped */
+    ALT_DMA_MANAGER_STATE_EXECUTING   = 1, /*!< Executing */
+    ALT_DMA_MANAGER_STATE_CACHE_MISS  = 2, /*!< Cache Miss */
+    ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */
+    ALT_DMA_MANAGER_STATE_WFE         = 4, /*!< Waiting for Event */
+    ALT_DMA_MANAGER_STATE_FAULTING    = 15 /*!< Faulting */
+}
+ALT_DMA_MANAGER_STATE_t;
+
+/*!
+ * This type definition enumerates the operational states that a DMA channel
+ * may have.
+ */
+typedef enum ALT_DMA_CHANNEL_STATE_e
+{
+    ALT_DMA_CHANNEL_STATE_STOPPED             = 0,  /*!< Stopped */
+    ALT_DMA_CHANNEL_STATE_EXECUTING           = 1,  /*!< Executing */
+    ALT_DMA_CHANNEL_STATE_CACHE_MISS          = 2,  /*!< Cache Miss */
+    ALT_DMA_CHANNEL_STATE_UPDATING_PC         = 3,  /*!< Updating PC */
+    ALT_DMA_CHANNEL_STATE_WFE                 = 4,  /*!< Waiting for Event */
+    ALT_DMA_CHANNEL_STATE_AT_BARRIER          = 5,  /*!< At Barrier */
+    ALT_DMA_CHANNEL_STATE_WFP                 = 7,  /*!< Waiting for Peripheral */
+    ALT_DMA_CHANNEL_STATE_KILLING             = 8,  /*!< Killing */
+    ALT_DMA_CHANNEL_STATE_COMPLETING          = 9,  /*!< Completing */
+    ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */
+    ALT_DMA_CHANNEL_STATE_FAULTING            = 15  /*!< Faulting */
+}
+ALT_DMA_CHANNEL_STATE_t;
+
+/*!
+ * This type definition enumerates the possible fault status that the DMA
+ * manager can have as a register mask.
+ */
+typedef enum ALT_DMA_MANAGER_FAULT_e
+{
+    /*!
+     * The DMA manager abort occured because of an instruction issued through
+     * the debug interface.
+     */
+    ALT_DMA_MANAGER_FAULT_DBG_INSTR       = (int32_t)(1UL << 30),
+
+    /*!
+     * The DMA manager instruction fetch AXI bus response was not OKAY.
+     */
+    ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16),
+
+    /*!
+     * The DMA manager attempted to execute DMAWFE or DMASEV with
+     * inappropriate security permissions.
+     */
+    ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR    = (int32_t)(1UL <<  5),
+
+    /*!
+     * The DMA manager attempted to execute DMAGO with inappropriate security
+     * permissions.
+     */
+    ALT_DMA_MANAGER_FAULT_DMAGO_ERR       = (int32_t)(1UL <<  4),
+
+    /*!
+     * The DMA manager attempted to execute an instruction operand that was
+     * not valid for the DMA configuration.
+     */
+    ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL <<  1),
+
+    /*!
+     * The DMA manager attempted to execute an undefined instruction.
+     */
+    ALT_DMA_MANAGER_FAULT_UNDEF_INSTR     = (int32_t)(1UL <<  0)
+}
+ALT_DMA_MANAGER_FAULT_t;
+
+/*!
+ * This type definition enumerates the possible fault status that a channel
+ * may have as a register mask.
+ */
+typedef enum ALT_DMA_CHANNEL_FAULT_e
+{
+    /*!
+     * The DMA channel has locked up due to resource starvation.
+     */
+    ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR          = (int32_t)(1UL << 31),
+
+    /*!
+     * The DMA channel abort occured because of an instruction issued through
+     * the debug interface.
+     */
+    ALT_DMA_CHANNEL_FAULT_DBG_INSTR           = (int32_t)(1UL << 30),
+
+    /*!
+     * The DMA channel data read AXI bus reponse was not OKAY.
+     */
+    ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR       = (int32_t)(1UL << 18),
+
+    /*!
+     * The DMA channel data write AXI bus response was not OKAY.
+     */
+    ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR      = (int32_t)(1UL << 17),
+
+    /*!
+     * The DMA channel instruction fetch AXI bus response was not OKAY.
+     */
+    ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR     = (int32_t)(1UL << 16),
+
+    /*!
+     * The DMA channel MFIFO did not have the data for the DMAST instruction.
+     */
+    ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13),
+
+    /*!
+     * The DMA channel MFIFO is too small to hold the DMALD instruction data,
+     * or too small to servic the DMAST instruction request.
+     */
+    ALT_DMA_CHANNEL_FAULT_MFIFO_ERR           = (int32_t)(1UL << 12),
+
+    /*!
+     * The DMA channel in non-secure state attempted to perform a secure read
+     * or write.
+     */
+    ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR         = (int32_t)(1UL <<  7),
+
+    /*!
+     * The DMA channel in non-secure state attempted to execute the DMAWFP,
+     * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral.
+     */
+    ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR       = (int32_t)(1UL <<  6),
+
+    /*!
+     * The DMA channel in non-secure state attempted to execute the DMAWFE or
+     * DMASEV instruction for a secure event or secure interrupt (if
+     * applicable).
+     */
+    ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR         = (int32_t)(1UL <<  5),
+
+    /*!
+     * The DMA channel attempted to execute an instruction operand that was
+     * not valid for the DMA configuration.
+     */
+    ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID     = (int32_t)(1UL <<  1),
+
+    /*!
+     * The DMA channel attempted to execute an undefined instruction.
+     */
+    ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR         = (int32_t)(1UL <<  0)
+}
+ALT_DMA_CHANNEL_FAULT_t;
+
+/*!
+ * This type definition enumerates the possible DMA event-interrupt behavior
+ * option selections when a DMASEV instruction is executed.
+ */
+typedef enum ALT_DMA_EVENT_SELECT_e
+{
+    /*!
+     * If the DMA controller executes DMASEV for the event-interrupt resource
+     * then the DMA sends the event to all of the channel threads.
+     */
+    ALT_DMA_EVENT_SELECT_SEND_EVT,
+
+    /*!
+     * If the DMA controller executes DMASEV for the event-interrupt resource
+     * then the DMA sets the \b irq[N] HIGH.
+     */
+    ALT_DMA_EVENT_SELECT_SIG_IRQ
+}
+ALT_DMA_EVENT_SELECT_t;
+
+/*!
+ * This type enumerates the DMA peripheral interface MUX selection options
+ * available.
+ */
+typedef enum ALT_DMA_PERIPH_MUX_e
+{
+    /*! 
+     * Accept the reset default MUX selection
+     */ 
+    ALT_DMA_PERIPH_MUX_DEFAULT = 0,
+
+    /*!
+     * Select FPGA as the peripheral interface
+     */
+    ALT_DMA_PERIPH_MUX_FPGA    = 1,
+
+    /*!
+     * Select CAN as the peripheral interface
+     */
+    ALT_DMA_PERIPH_MUX_CAN     = 2
+}
+ALT_DMA_PERIPH_MUX_t;
+
+/*!
+ * This type defines the structure used to specify the configuration of the
+ * security states and peripheral interface MUX selections for the DMA
+ * controller.
+ */
+typedef struct ALT_DMA_CFG_s
+{
+    /*!
+     * DMA Manager security state configuration.
+     */
+    ALT_DMA_SECURITY_t manager_sec;
+
+    /*!
+     * DMA interrupt output security state configurations. Security state
+     * configurations are 0-based index-aligned with the enumeration values
+     * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type.
+     */
+    ALT_DMA_SECURITY_t irq_sec[8];
+
+    /*!
+     * Peripheral request interface security state configurations. Security
+     * state configurations are 0-based index-aligned with the enumeration
+     * values of the ALT_DMA_PERIPH_t type.
+     */
+    ALT_DMA_SECURITY_t periph_sec[32];
+
+    /*!
+     * DMA Peripheral Register Interface MUX Selections. MUX selections are
+     * 0-based index-aligned with the enumeration values
+     * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through
+     * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type.
+     */
+    ALT_DMA_PERIPH_MUX_t periph_mux[4];
+}
+ALT_DMA_CFG_t;
+
+/*!
+ * Initialize the DMA controller.
+ *
+ * Initializes the DMA controller by setting the necessary control values to
+ * establish the security state and MUXed peripheral request interface selection
+ * configurations before taking the DMA controller out of reset.
+ *
+ * After the DMA is initialized, the following conditions hold true:
+ *  * All DMA channel threads are in the Stopped state.
+ *  * All DMA channel threads are available for allocation.
+ *  * DMA Manager thread is waiting for an instruction from either APB
+ *    interface.
+ *  * The security state configurations of the DMA Manager, interrupt outputs,
+ *    and peripheral request interfaces are established and immutable until the
+ *    DMA is reset.
+ *  * The MUXed peripheral request interface selection configurations are
+ *    established and immutable until the DMA is reset.
+ *
+ * \param       dma_cfg
+ *              A pointer to a ALT_DMA_CFG_t structure containing the desired
+ *              DMA controller security state and peripheral request interface
+ *              MUX selections.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg);
+
+/*!
+ * Uninitializes the DMA controller.
+ *
+ * Uninitializes the DMA controller by killing any running channel threads and
+ * putting the DMA controller into reset.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_uninit(void);
+
+/*!
+ * Allocate a DMA channel resource for use.
+ *
+ * \param       channel
+ *              A DMA controller channel.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Allocate a free DMA channel resource for use if there are any.
+ *
+ * \param       allocated
+ *              [out] A pointer to an output parameter that will contain the
+ *              channel allocated.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed. An unallocated channel
+ *                              may not be available at the time of the API
+ *                              call.
+ */
+ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated);
+
+/*!
+ * Free a DMA channel resource for reuse.
+ *
+ * \param       channel
+ *              The DMA controller channel resource to free.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed. The channel may not be in
+ *                              the STOPPED state.
+ */
+ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Start execution of a DMA microcode program on the specified DMA channel
+ * thread resource.
+ *
+ * \param       channel
+ *              The DMA channel thread used to execute the microcode program.
+ *
+ * \param       pgm
+ *              The DMA microcode program.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel,
+                                     ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Kill (abort) execution of any microcode program executing on the specified
+ * DMA channel thread resource.
+ *
+ * Terminates the channel thread of execution by issuing a DMAKILL instruction
+ * using the DMA APB slave interface.
+ *
+ * \param       channel
+ *              The DMA channel thread to abort any executing microcode program
+ *              on.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_TMO       Timeout waiting for the channel to change into
+ *                              KILLING or STOPPED state.
+ */
+ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Returns the current register value for the given DMA channel.
+ *
+ * \param       channel
+ *              The DMA channel thread to abort any executing microcode program
+ *              on.
+ *
+ * \param       reg
+ *              Register to get the value for.
+ *
+ * \param       val
+ *              [out] The current value of the requested register.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The specified channel or register is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel,
+                                        ALT_DMA_PROGRAM_REG_t reg, uint32_t * val);
+
+/*!
+ * Signals the occurrence of an event or interrupt, using the specified event
+ * number.
+ *
+ * Causes the CPU to issue a DMASEV instruction using the DMA APB slave
+ * interface.
+ *
+ * The Interrupt Enable Register (INTEN) register is used to control if each
+ * event-interrupt resource is either an event or an interrupt. The INTEN
+ * register sets the event-interrupt resource to function as an:
+ *  * Event - The DMAC generates an event for the specified event-interrupt
+ *            resource. When the DMAC executes a DMAWFE instruction for the
+ *            same event-interrupt resource then it clears the event.
+ *  * Interrupt - The DMAC sets the \b IRQ[N] signal high, where
+ *                \e evt_num is the number of the specified event
+ *                resource. The interrupt must be cleared after being handled.
+ *
+ * When the configured to generate an event, this function may be used to
+ * restart one or more waiting DMA channels (i.e. having executed a DMAWFE
+ * instruction).
+ *
+ * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller
+ * DMA-330 Technical Reference Manual for implementation details and use cases:
+ *   * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface
+ *   * 2.7, Using Events and Interrupts
+ *
+ * \param       evt_num   
+ *              A DMA event-interrupt resource. Allowable event values may be
+ *              ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is
+ *              not.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given event number is invalid.
+ */
+ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num);
+
+/*!
+ * Returns the current operational state of the DMA manager thread.
+ *
+ * \param       state
+ *              [out] Pointer to an output parameter to contain the DMA
+ *              channel thread state.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state);
+
+/*!
+ * Returns the current operational state of the specified DMA channel thread.
+ *
+ * \param       channel
+ *              The DMA channel thread to return the operational state of.
+ *
+ * \param       state
+ *              [out] Pointer to an output parameter to contain the DMA
+ *              channel thread state.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel,
+                                          ALT_DMA_CHANNEL_STATE_t * state);
+
+/*!
+ * Return the current fault status of the DMA manager thread.
+ *
+ * \param       fault
+ *              [out] Pointer to an output parameter to contain the DMA
+ *              manager fault status.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault);
+
+/*!
+ * Return the current fault status of the specified DMA channel thread.
+ *
+ * \param       channel
+ *              The DMA channel thread to return the fault status of.
+ *
+ * \param       fault
+ *              [out] Pointer to an output parameter to contain the DMA
+ *              channel fault status.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel,
+                                                 ALT_DMA_CHANNEL_FAULT_t * fault);
+
+/*!
+ * Select whether the DMA controller sends the specific event to all channel
+ * threads or signals an interrupt using the corressponding \b irq when a DMASEV
+ * instruction is executed for the specified event-interrupt resource number.
+ *
+ * \param       evt_num
+ *              The event-interrupt resource number. Valid values are
+ *              ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \param       opt
+ *              The desired behavior selection for \e evt_num when a DMASEV is
+ *              executed.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given selection identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num,
+                                         ALT_DMA_EVENT_SELECT_t opt);
+
+/*!
+ * Returns the status of the specified event-interrupt resource.
+ *
+ * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns
+ * ALT_E_FALSE if event is inactive or \b irq[N] is LOW.
+ *
+ * \param       evt_num
+ *              The event-interrupt resource number. Valid values are
+ *              ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval      ALT_E_TRUE      Event is active or \b irq[N] is HIGH.
+ * \retval      ALT_E_FALSE     Event is inactive or \b irq[N] is LOW.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num);
+
+/*!
+ * Returns the status of the specified interrupt resource.
+ *
+ * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and
+ * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW.
+ *
+ * \param       irq_num
+ *              The interrupt resource number. Valid values are
+ *              ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval      ALT_E_TRUE      Event is active or \b irq[N] is HIGH.
+ * \retval      ALT_E_FALSE     Event is inactive or \b irq[N] is LOW.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num);
+
+/*!
+ * Clear the active (HIGH) status of the specified interrupt resource.
+ *
+ * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the
+ * event-interrupt resource is configured (see: alt_dma_event_int_enable()) 
+ * to signal an interrupt. Otherwise, the status of \b irq[N] does not change.
+ *
+ * \param       irq_num
+ *              The interrupt resource number. Valid values are
+ *              ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations
+ *
+ * The functions in this group provide common DMA operations for common bulk
+ * data transfers between:
+ *  * Memory to Memory
+ *  * Memory to Peripheral
+ *  * Peripheral to Memory
+ *
+ * All copy operations are asynchronous. Interrupt handlers or other
+ * mechanisms can be used to be notified of transfer completion or faults.
+ *
+ * @{
+ */
+
+/*!
+ * Uses the DMA engine to copy the specified memory from the given source
+ * address to the given destination address.
+ *
+ * Overlapping memory regions are not supported.
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       dest
+ *              The destination memory address to copy to.
+ *
+ * \param       src
+ *              The source memory address to copy from.
+ *
+ * \param       size
+ *              The size of the transfer in bytes.
+ *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel or event identifier (if
+ *                              used) is invalid, or the memory regions
+ *                              specified are overlapping.
+ */
+ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel,
+                                         ALT_DMA_PROGRAM_t * program,
+                                         void * dest,
+                                         const void * src,
+                                         size_t size,
+                                         bool send_evt,
+                                         ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to zero out the specified memory buffer.
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       buf
+ *              The buffer memory address to zero out.
+ *
+ * \param       size
+ *              The size of the buffer in bytes.
+ *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel or event identifier (if
+ *                              used) is invalid.
+ */
+ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel,
+                                       ALT_DMA_PROGRAM_t * program,
+                                       void * buf,
+                                       size_t size,
+                                       bool send_evt,
+                                       ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to transfer the contents of a memory buffer to a keyhole
+ * register.
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       dst_reg
+ *              The address of the register to write buffer to.
+ *
+ * \param       src_buf
+ *              The address of the memory buffer for the data.
+ *
+ * \param       count
+ *              The number of transfers to make.
+ *
+ * \param       register_width_bits
+ *              The width of the register to transfer to in bits. Valid values
+ *              are 8, 16, 32, and 64.
+ *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel, event identifier (if used),
+ *                              or register width are invalid, or if the
+ *                              destination register or source buffer is
+ *                              unaligned to the register width.
+ */
+ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel,
+                                           ALT_DMA_PROGRAM_t * program,
+                                           void * dst_reg,
+                                           const void * src_buf,
+                                           size_t count,
+                                           uint32_t register_width_bits,
+                                           bool send_evt,
+                                           ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to transfer the contents of a keyhole register to a
+ * memory buffer.
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       dst_buf
+ *              The address of the memory buffer to copy to.
+ *
+ * \param       src_reg
+ *              The address of the keyhole register to read from.
+ *
+ * \param       count
+ *              The number of transfers to make.
+ *
+ * \param       register_width_bits
+ *              The width of the register to transfer to in bits. Valid values
+ *              are 8, 16, 32, and 64.
+ *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel, event identifier (if used),
+ *                              or register width are invalid, or if the
+ *                              destination buffer or source register is
+ *                              unaligned to the register width.
+ */
+ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel,
+                                           ALT_DMA_PROGRAM_t * program,
+                                           void * dst_buf,
+                                           const void * src_reg,
+                                           size_t count,
+                                           uint32_t register_width_bits,
+                                           bool send_evt,
+                                           ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to copy memory from the given source address to the
+ * specified peripheral. Because different peripheral has different
+ * characteristics, individual peripherals need to be explicitly supported.
+ *
+ * The following lists the peripheral IDs supported by this API:
+ *  * ALT_DMA_PERIPH_UART0_TX
+ *  * ALT_DMA_PERIPH_UART1_TX
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       dest
+ *              The destination peripheral to copy memory to.
+ *
+ * \param       src
+ *              The source memory address to copy from.
+ *
+ * \param       size
+ *              The size of the transfer in bytes.
+ *
+ * \param       periph_info
+ *              A pointer to a peripheral specific data structure. The
+ *              following list shows what data structure should be used for
+ *              peripherals:
+ *               * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the
+ *                 ALT_16550_HANDLE_t used to interact with that UART.
+ *               * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the
+ *                 ALT_16550_HANDLE_t used to interact with that UART.
+ *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel, peripheral, or event
+ *                              identifier (if used) is invalid.
+ *
+ * \internal
+ * Priority peripheral IDs to be supported:
+ *  * ALT_DMA_PERIPH_FPGA_0
+ *  * ALT_DMA_PERIPH_FPGA_1
+ *  * ALT_DMA_PERIPH_FPGA_2
+ *  * ALT_DMA_PERIPH_FPGA_3
+ *  * ALT_DMA_PERIPH_FPGA_4
+ *  * ALT_DMA_PERIPH_FPGA_5
+ *  * ALT_DMA_PERIPH_FPGA_6
+ *  * ALT_DMA_PERIPH_FPGA_7
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel,
+                                         ALT_DMA_PROGRAM_t * program,
+                                         ALT_DMA_PERIPH_t dest,
+                                         const void * src,
+                                         size_t size,
+                                         void * periph_info,
+                                         bool send_evt,
+                                         ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to copy memory from the specified peripheral to the
+ * given destination address. Because different peripheral has different
+ * characteristics, individual peripherals need to be explicitly supported.
+ *
+ * The following lists the peripheral IDs supported by this API:
+ *  * ALT_DMA_PERIPH_UART0_RX
+ *  * ALT_DMA_PERIPH_UART1_RX
+ *
+ * \param       channel
+ *              The DMA channel thread to use for the transfer.
+ *
+ * \param       program
+ *              An allocated DMA program buffer to use for the life of the
+ *              transfer.
+ *
+ * \param       dest
+ *              The destination memory address to copy to.
+ *
+ * \param       src
+ *              The source peripheral to copy memory from.
+ *
+ * \param       size
+ *              The size of the transfer in bytes.
+ *
+ * \param       periph_info
+ *              A pointer to a peripheral specific data structure. The
+ *              following list shows what data structure should be used for
+ *              peripherals:
+ *               * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the
+ *                 ALT_16550_HANDLE_t used to interact with that UART.
+ *               * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the
+ *                 ALT_16550_HANDLE_t used to interact with that UART.
+ * *
+ * \param       send_evt
+ *              If set to true, the DMA engine will be instructed to send an
+ *              event upon completion or fault.
+ *
+ * \param       evt
+ *              If send_evt is true, the event specified will be sent.
+ *              Otherwise the parameter is ignored.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The given channel, peripheral, or event
+ *                              identifier (if used) is invalid.
+*
+ * \internal
+ * Priority peripheral IDs to be supported:
+ *  * ALT_DMA_PERIPH_FPGA_0
+ *  * ALT_DMA_PERIPH_FPGA_1
+ *  * ALT_DMA_PERIPH_FPGA_2
+ *  * ALT_DMA_PERIPH_FPGA_3
+ *  * ALT_DMA_PERIPH_FPGA_4
+ *  * ALT_DMA_PERIPH_FPGA_5
+ *  * ALT_DMA_PERIPH_FPGA_6
+ *  * ALT_DMA_PERIPH_FPGA_7
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel,
+                                         ALT_DMA_PROGRAM_t * program,
+                                         void * dest,
+                                         ALT_DMA_PERIPH_t src,
+                                         size_t size,
+                                         void * periph_info,
+                                         bool send_evt,
+                                         ALT_DMA_EVENT_t evt);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __ALT_DMA_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h
new file mode 100644
index 0000000..e82bc1a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ * 
+ ******************************************************************************/
+
+#ifndef __ALT_DMA_COMMON_H__
+#define __ALT_DMA_COMMON_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
+ *
+ * This module contains the common definitions for the DMA controller related
+ * APIs.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the DMA controller channel threads.
+ */
+typedef enum ALT_DMA_CHANNEL_e
+{
+    ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
+    ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
+    ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
+    ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
+    ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
+    ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
+    ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
+    ALT_DMA_CHANNEL_7 = 7  /*!< DMA Channel Thread 7 */
+}
+ALT_DMA_CHANNEL_t;
+
+/*!
+ * This type definition enumerates the SoC system peripherals implementing the
+ * required request interface that enables direct DMA transfers to/from the
+ * device.
+ *
+ * FPGA soft IP interface to the DMA are required to comply with the Synopsys
+ * protocol.
+ *
+ * Request interface numbers 4 through 7 are multiplexed between the CAN
+ * controllers and soft logic implemented in the FPGA fabric. The selection
+ * between the CAN controller and FPGA interfaces is determined at DMA
+ * initialization.
+ */
+typedef enum ALT_DMA_PERIPH_e
+{
+    ALT_DMA_PERIPH_FPGA_0             = 0,  /*!< FPGA soft IP interface 0 */
+    ALT_DMA_PERIPH_FPGA_1             = 1,  /*!< FPGA soft IP interface 1 */
+    ALT_DMA_PERIPH_FPGA_2             = 2,  /*!< FPGA soft IP interface 2 */
+    ALT_DMA_PERIPH_FPGA_3             = 3,  /*!< FPGA soft IP interface 3 */
+
+    ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4,  /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
+    ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5,  /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
+    ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6,  /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
+    ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7,  /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
+
+    ALT_DMA_PERIPH_FPGA_4             = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
+    ALT_DMA_PERIPH_FPGA_5             = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
+    ALT_DMA_PERIPH_FPGA_6             = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
+    ALT_DMA_PERIPH_FPGA_7             = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
+
+    ALT_DMA_PERIPH_CAN0_IF1           = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
+    ALT_DMA_PERIPH_CAN0_IF2           = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
+    ALT_DMA_PERIPH_CAN1_IF1           = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
+    ALT_DMA_PERIPH_CAN1_IF2           = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
+
+    ALT_DMA_PERIPH_I2C0_TX            = 8,  /*!< I<sup>2</sup>C 0 TX */
+    ALT_DMA_PERIPH_I2C0_RX            = 9,  /*!< I<sup>2</sup>C 0 RX */
+    ALT_DMA_PERIPH_I2C1_TX            = 10, /*!< I<sup>2</sup>C 1 TX */
+    ALT_DMA_PERIPH_I2C1_RX            = 11, /*!< I<sup>2</sup>C 1 RX */
+    ALT_DMA_PERIPH_I2C2_TX            = 12, /*!< I<sup>2</sup>C 2 TX */
+    ALT_DMA_PERIPH_I2C2_RX            = 13, /*!< I<sup>2</sup>C 2 RX */
+    ALT_DMA_PERIPH_I2C3_TX            = 14, /*!< I<sup>2</sup>C 3 TX */
+    ALT_DMA_PERIPH_I2C3_RX            = 15, /*!< I<sup>2</sup>C 3 RX */
+    ALT_DMA_PERIPH_SPI0_MASTER_TX     = 16, /*!< SPI 0 Master TX */
+    ALT_DMA_PERIPH_SPI0_MASTER_RX     = 17, /*!< SPI 0 Master RX */
+    ALT_DMA_PERIPH_SPI0_SLAVE_TX      = 18, /*!< SPI 0 Slave TX */
+    ALT_DMA_PERIPH_SPI0_SLAVE_RX      = 19, /*!< SPI 0 Slave RX */
+    ALT_DMA_PERIPH_SPI1_MASTER_TX     = 20, /*!< SPI 1 Master TX */
+    ALT_DMA_PERIPH_SPI1_MASTER_RX     = 21, /*!< SPI 1 Master RX */
+    ALT_DMA_PERIPH_SPI1_SLAVE_TX      = 22, /*!< SPI 1 Slave TX */
+    ALT_DMA_PERIPH_SPI1_SLAVE_RX      = 23, /*!< SPI 1 Slave RX */
+    ALT_DMA_PERIPH_QSPI_FLASH_TX      = 24, /*!< QSPI Flash TX */
+    ALT_DMA_PERIPH_QSPI_FLASH_RX      = 25, /*!< QSPI Flash RX */
+    ALT_DMA_PERIPH_STM                = 26, /*!< System Trace Macrocell */
+    ALT_DMA_PERIPH_RESERVED           = 27, /*!< Reserved */
+    ALT_DMA_PERIPH_UART0_TX           = 28, /*!< UART 0 TX */
+    ALT_DMA_PERIPH_UART0_RX           = 29, /*!< UART 0 RX */
+    ALT_DMA_PERIPH_UART1_TX           = 30, /*!< UART 1 TX */
+    ALT_DMA_PERIPH_UART1_RX           = 31  /*!< UART 1 RX */
+}
+ALT_DMA_PERIPH_t;
+
+/*!
+ * This type enumerates the DMA security state options available.
+ */
+typedef enum ALT_DMA_SECURITY_e
+{
+    ALT_DMA_SECURITY_DEFAULT   = 0, /*!< Use the default security value (e.g. reset default) */
+    ALT_DMA_SECURITY_SECURE    = 1, /*!< Secure */
+    ALT_DMA_SECURITY_NONSECURE = 2  /*!< Non-secure */
+}
+ALT_DMA_SECURITY_t;
+
+/*!
+ * This type definition enumerates the DMA event-interrupt resources.
+ */
+typedef enum ALT_DMA_EVENT_e
+{
+    ALT_DMA_EVENT_0     = 0, /*!< DMA Event 0 */
+    ALT_DMA_EVENT_1     = 1, /*!< DMA Event 1 */
+    ALT_DMA_EVENT_2     = 2, /*!< DMA Event 2 */
+    ALT_DMA_EVENT_3     = 3, /*!< DMA Event 3 */
+    ALT_DMA_EVENT_4     = 4, /*!< DMA Event 4 */
+    ALT_DMA_EVENT_5     = 5, /*!< DMA Event 5 */
+    ALT_DMA_EVENT_6     = 6, /*!< DMA Event 6 */
+    ALT_DMA_EVENT_7     = 7, /*!< DMA Event 7 */
+    ALT_DMA_EVENT_ABORT = 8  /*!< DMA Abort Event */
+}
+ALT_DMA_EVENT_t;
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_COMMON_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h
new file mode 100644
index 0000000..67f4839
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h
@@ -0,0 +1,949 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __ALT_DMA_PROGRAM_H__
+#define __ALT_DMA_PROGRAM_H__
+
+#include "hwlib.h"
+#include "alt_dma_common.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA_PRG DMA Controller Programming API
+ *
+ * This API provides functions for dynamically defining and assembling microcode
+ * programs for execution on the DMA controller.
+ *
+ * The microcode program assembly API provides users with the ability to develop
+ * highly optimized and tailored algorithms for data transfer between SoC FPGA
+ * IP blocks and/or system memory.
+ *
+ * The same microcode program assembly facilities are also used to implement the
+ * functions found in the HWLIB Common DMA Operations functional API.
+ *
+ * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA
+ * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated
+ * from used specified system memory. Once a microcode program has been
+ * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA
+ * channel thread. The microcode program may be rerun on any DMA channel thread
+ * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t
+ * containing the program is maintained.
+ *
+ * @{
+ */
+
+/*!
+ * This preprocessor declares the DMA channel thread microcode instruction
+ * cache line width in bytes. It is recommended that the program buffers be
+ * sized to a multiple of the cache line size. This will allow for the most
+ * efficient microcode speed and space utilization.
+ */
+#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE     (32)
+
+/*!
+ * This preprocessor declares the DMA channel thread microcode instruction
+ * cache line count. Thus the total size of the cache is the cache line size
+ * multipled by the cache line count. Programs larger than the cache size risk
+ * having a cache miss while executing.
+ */
+#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT    (16)
+
+/*!
+ * This preprocessor definition determines the size of the program buffer
+ * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate
+ * size for most DMA microcode programs. If calls within this API are
+ * reporting out of memory response codes, consider increasing the provisioned
+ * program buffersize.
+ *
+ * To specify another DMA microcode program buffer size, redefine the macro
+ * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in
+ * your Makefile. It is recommended that the size be a multiple of the
+ * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for
+ * more information. The largest supported buffer size is 65536 bytes.
+ */
+#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
+#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE   (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
+#endif
+
+/*!
+ * This type defines the structure used to assemble and contain a microcode
+ * program which can be executed by the DMA controller. The internal members
+ * are undocumented and should not be altered outside of this API.
+ */
+typedef struct ALT_DMA_PROGRAM_s
+{
+    uint32_t flag;
+
+    uint16_t buffer_start;
+    uint16_t code_size;
+
+    uint16_t loop0;
+    uint16_t loop1;
+
+    uint16_t sar;
+    uint16_t dar;
+
+    /*
+     * Add a little extra space so that regardless of where this structure
+     * sits in memory, a suitable start address can be aligned to the cache
+     * line stride while providing the requested buffer space.
+     */
+    uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +
+                    ALT_DMA_PROGRAM_CACHE_LINE_SIZE];
+}
+ALT_DMA_PROGRAM_t;
+
+/*!
+ * This type definition enumerates the DMA controller register names for use in
+ * microcode program definition.
+ */
+typedef enum ALT_DMA_PROGRAM_REG_e
+{
+    /*! Source Address Register */
+    ALT_DMA_PROGRAM_REG_SAR = 0x0,
+
+    /*! Destination Address Register */
+    ALT_DMA_PROGRAM_REG_DAR = 0x2,
+
+    /*! Channel Control Register */
+    ALT_DMA_PROGRAM_REG_CCR = 0x1
+}
+ALT_DMA_PROGRAM_REG_t;
+
+/*!
+ * This type definition enumerates the instruction modifier options available
+ * for use with selected DMA microcode instructions.
+ *
+ * The enumerations values are context dependent upon the instruction being
+ * modified.
+ *
+ * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and
+ * <b>DMASTP\<S|B></b> microcode instructions, the enumeration
+ * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier
+ * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b>
+ * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies
+ * that no modifier is present for instructions where use of <b>[S|B]</b> is
+ * optional.
+ *
+ * For the <b>DMAWFP</b> microcode instruction, the enumerations
+ * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or
+ * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding
+ * options <b>\<single|burst|periph></b>.
+ */
+typedef enum ALT_DMA_PROGRAM_INST_MOD_e
+{
+    /*!
+     * This DMA instruction modifier specifies that no special modifier is
+     * added to the instruction.
+     */
+    ALT_DMA_PROGRAM_INST_MOD_NONE,
+
+    /*!
+     * Depending on the DMA microcode instruction modified, this modifier
+     * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a
+     * <b>\<single|burst|periph></b>.
+     */
+    ALT_DMA_PROGRAM_INST_MOD_SINGLE,
+
+    /*!
+     * Depending on the DMA microcode instruction modified, this modifier
+     * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a
+     * <b>\<single|burst|periph></b>.
+     */
+    ALT_DMA_PROGRAM_INST_MOD_BURST,
+
+    /*!
+     * This DMA instruction modifier specifies a <b>\<periph></b> for a
+     * <b>\<single|burst|periph></b>.
+     */
+    ALT_DMA_PROGRAM_INST_MOD_PERIPH
+}
+ALT_DMA_PROGRAM_INST_MOD_t;
+
+/*!
+ * This function initializes a system memory buffer for use as a DMA microcode
+ * program buffer. This should be the first API call made on the program
+ * buffer type.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     Details about error status code
+ */
+ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function verifies that the DMA microcode program buffer is no longer
+ * in use and performs any needed uninitialization steps.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     Details about error status code
+ */
+ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function clears the existing DMA microcode program in the given
+ * program buffer.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     Details about error status code.
+ */
+ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function validate that the given DMA microcode program buffer contains
+ * a well formed program.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \retval      ALT_E_SUCCESS   The given program is well formed.
+ * \retval      ALT_E_ERROR     The given program is not well formed.
+ */
+ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function reports the number bytes incremented for the register
+ * specified. The purpose is to determine the progress of an ongoing DMA
+ * transfer.
+ *
+ * It is implemented by calculating the difference of the programmed SAR or DAR
+ * with the current channel SAR or DAR register value.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \param       channel
+ *              The channel that the program is running on.
+ *
+ * \param       reg
+ *              Register to change the value for. Valid for only
+ *              ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
+ *
+ * \param       current
+ *              The current snapshot value of the register read from the DMA
+ *              channel.
+ *
+ * \param       progress
+ *              [out] A pointer to a memory location that will be used to store
+ *              the number of bytes transfered.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     Details about error status code.
+ * \retval      ALT_E_BAD_ARG   The specified channel is invalid, the specified
+ *                              register is invalid, or the DMAMOV for the
+ *                              specified register has not yet been assembled
+ *                              in the current program buffer.
+ */
+ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm,
+                                             ALT_DMA_PROGRAM_REG_t reg,
+                                             uint32_t current, uint32_t * progress);
+
+/*!
+ * This function updates a pre-existing DMAMOV value affecting the SAR or DAR
+ * registers. This allows for pre-assembled programs that can be used on
+ * different source and destination addresses.
+ *
+ * \param       pgm
+ *              A pointer to a DMA program buffer structure.
+ *
+ * \param       reg
+ *              Register to change the value for. Valid for only
+ *              ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
+ *
+ * \param       val
+ *              The value to update to.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     Details about error status code.
+ * \retval      ALT_E_BAD_ARG   The specified register is invalid or the DMAMOV
+ *                              for the specified register has not yet been
+ *                              assembled in the current program buffer.
+ */
+ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm,
+                                           ALT_DMA_PROGRAM_REG_t reg, uint32_t val);
+
+/*!
+ */
+
+/*!
+ * Assembles a DMAADDH (Add Halfword) instruction into the microcode program
+ * buffer. This instruction uses 3 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA program buffer to contain the assembled instruction.
+ *
+ * \param       addr_reg
+ *              The channel address register (ALT_DMA_PROGRAM_REG_DAR or
+ *              ALT_DMA_PROGRAM_REG_SAR) to add the value to.
+ *
+ * \param       val
+ *              The 16-bit unsigned value to add to the channel address
+ *              register.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
+ */
+// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate>
+ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm,
+                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
+
+/*!
+ * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode
+ * program buffer. This instruction uses 3 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       addr_reg
+ *              The channel address register (ALT_DMA_PROGRAM_REG_DAR or
+ *              ALT_DMA_PROGRAM_REG_SAR) to add the value to.
+ *
+ * \param       val
+ *              The 16-bit unsigned value to add to the channel address
+ *              register.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
+ */
+// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate>
+ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm,
+                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
+
+/*!
+ * Assembles a DMAEND (End) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAEND
+ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode
+ * program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       periph
+ *              The peripheral to flush.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid peripheral specified.
+ */
+// Assembler Syntax: DMAFLUSHP <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm,
+                                          ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMAGO (Go) instruction into the microcode program buffer. This
+ * instruction uses 6 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       channel
+ *              The stopped channel to act upon.
+ *
+ * \param       val
+ *              The value to write to the channel program counter register.
+ *
+ * \param       sec
+ *              The security state for the operation.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid channel or security specified.
+ */
+// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns]
+ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm,
+                                      ALT_DMA_CHANNEL_t channel, uint32_t val,
+                                      ALT_DMA_SECURITY_t sec);
+
+/*!
+ * Assembles a DMAKILL (Kill) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAKILL
+ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMALD (Load) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       mod
+ *              The program instruction modifier for the type of transfer.
+ *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
+ *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid instruction modifier specified.
+ */
+// Assembler Syntax: DMALD[S|B]
+ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm,
+                                      ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMALDP (Load and notify Peripheral) instruction into the
+ * microcode program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       mod
+ *              The program instruction modifier for the type of transfer.
+ *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
+ *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \param       periph
+ *              The peripheral to notify.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid instruction modifier or peripheral
+ *                                  specified.
+ */
+// Assembler Syntax: DMALDP<S|B> <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMALP (Loop) instruction into the microcode program buffer.
+ * This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       iterations
+ *              The number of iterations to run for. Valid values are 1 - 256.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid iterations specified.
+ * \retval      ALT_E_BAD_OPERATION All loop registers are in use.
+ */
+// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations>
+ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm,
+                                      uint32_t iterations);
+
+/*!
+ * Assembles a DMALPEND (Loop End) instruction into the microcode program
+ * buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       mod
+ *              The program instruction modifier for the loop terminator. Only
+ *              ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE
+ *              and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid instruction modifier specified.
+ * \retval      ALT_E_ARG_RANGE     Loop size is too large to be supported.
+ * \retval      ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to
+ *                                  the program buffer before adding this
+ *                                  DMALPEND instruction.
+ */
+// Assembler Syntax: DMALPEND[S|B]
+ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm,
+                                         ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMALPFE (Loop Forever) instruction into the microcode program
+ * buffer. No instruction is added to the buffer but a previous DMALPEND to
+ * create an infinite loop.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMALPFE
+ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAMOV (Move) instruction into the microcode program buffer.
+ * This instruction uses 6 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       chan_reg
+ *              The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR,
+ *              ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy
+ *              the value to.
+ *
+ * \param       val
+ *              The value to write to the specified register.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
+ */
+// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate>
+ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val);
+
+/*!
+ * Assembles a DMANOP (No Operation) instruction into the microcode program
+ * buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMANOP
+ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode
+ * program buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMARMB
+ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMASEV (Send Event) instruction into the microcode program
+ * buffer. This instruction uses 2 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       evt
+ *              The event to send.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid event specified.
+ */
+// Assembler Syntax: DMASEV <event_num>
+ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_EVENT_t evt);
+
+/*!
+ * Assembles a DMAST (Store) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       mod
+ *              The program instruction modifier for the type of transfer.
+ *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
+ *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAST[S|B]
+ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm,
+                                      ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMASTP (Store and notify Peripheral) instruction into the
+ * microcode program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       mod
+ *              The program instruction modifier for the type of transfer.
+ *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
+ *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \param       periph
+ *              The peripheral to notify.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid instruction modifier or peripheral
+ *                                  specified.
+ */
+// Assembler Syntax: DMASTP<S|B> <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMASTZ (Store Zero) instruction into the microcode program
+ * buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMASTZ
+ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAWFE (Wait For Event) instruction into the microcode program
+ * buffer. This instruction uses 2 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       evt
+ *              The event to wait for.
+ *
+ * \param       invalid
+ *              If invalid is set to true, the instruction will be configured
+ *              to invalidate the instruction cache for the current DMA
+ *              thread.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid event specified.
+ */
+// Assembler Syntax: DMAWFE <event_num>[, invalid]
+ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_EVENT_t evt, bool invalid);
+
+/*!
+ * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode
+ * program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param       periph
+ *              The peripheral to wait on.
+ *
+ * \param       mod
+ *              The program instruction modifier for the type of transfer.
+ *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE,
+ *              ALT_DMA_PROGRAM_INST_MOD_BURST, or
+ *              ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ * \retval      ALT_E_BAD_ARG       Invalid peripheral or instruction modifier
+ *                                  specified.
+ */
+// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph>
+ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm,
+                                       ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode
+ * program buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param       pgm
+ *              The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
+ * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAWMB
+ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * \addtogroup DMA_CCR Support for DMAMOV CCR
+ *
+ * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the
+ * dynamic microcode programming of the assembler directive:
+\verbatim
+
+DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>]
+            [SP<imm3>] [SC<imm4>]
+            [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>]
+            [DP<imm3>] [DC<imm4>]
+            [ES<8|16|32|64|128>]
+
+\endverbatim
+* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()).
+*
+* For example the assembler directive:
+\verbatim
+DMAMOV CCR SB1 SS32 DB1 DS32
+\endverbatim
+* would be dynamically programmed with the following API call:
+\verbatim
+alt_dma_program_DMAMOV( pgm,
+                        ALT_DMA_PROGRAM_REG_CCR,
+                        (   ALT_DMA_CCR_OPT_SB1
+                          | ALT_DMA_CCR_OPT_SS32
+                          | ALT_DMA_CCR_OPT_SA_DEFAULT
+                          | ALT_DMA_CCR_OPT_SP_DEFAULT
+                          | ALT_DMA_CCR_OPT_SC_DEFAULT
+                          | ALT_DMA_CCR_OPT_DB1
+                          | ALT_DMA_CCR_OPT_DS32
+                          | ALT_DMA_CCR_OPT_DA_DEFAULT
+                          | ALT_DMA_CCR_OPT_DP_DEFAULT
+                          | ALT_DMA_CCR_OPT_DC_DEFAULT
+                          | ALT_DMA_CCR_OPT_ES8
+                        )
+                      );
+\endverbatim
+*
+* Each CCR option category should be specified regardless of whether it
+* specifies a custom value or the normal default value (i.e. an
+* ALT_DMA_CCR_OPT_*_DEFAULT.
+*
+* @{
+*/
+
+/*
+ * Source Address {Fixed,Incrementing}
+ */
+/*! Source Address Fixed address burst. */
+#define ALT_DMA_CCR_OPT_SAF         (0 << 0)
+/*! Source Address Incrementing address burst. */
+#define ALT_DMA_CCR_OPT_SAI         (1 << 0)
+/*! Source Address Default value. */
+#define ALT_DMA_CCR_OPT_SA_DEFAULT  ALT_DMA_CCR_OPT_SAI
+
+/*
+ * Source burst Size (in bits)
+ */
+/*! Source burst Size of 8 bits. */
+#define ALT_DMA_CCR_OPT_SS8         (0 << 1)
+/*! Source burst Size of 16 bits. */
+#define ALT_DMA_CCR_OPT_SS16        (1 << 1)
+/*! Source burst Size of 32 bits. */
+#define ALT_DMA_CCR_OPT_SS32        (2 << 1)
+/*! Source burst Size of 64 bits. */
+#define ALT_DMA_CCR_OPT_SS64        (3 << 1)
+/*! Source burst Size of 128 bits. */
+#define ALT_DMA_CCR_OPT_SS128       (4 << 1)
+/*! Source burst Size default bits. */
+#define ALT_DMA_CCR_OPT_SS_DEFAULT  ALT_DMA_CCR_OPT_SS8
+
+/*
+ * Source burst Length (in transfer(s))
+ */
+/*! Source Burst length of 1 transfer. */
+#define ALT_DMA_CCR_OPT_SB1         (0x0 << 4)
+/*! Source Burst length of 2 transfers. */
+#define ALT_DMA_CCR_OPT_SB2         (0x1 << 4)
+/*! Source Burst length of 3 transfers. */
+#define ALT_DMA_CCR_OPT_SB3         (0x2 << 4)
+/*! Source Burst length of 4 transfers. */
+#define ALT_DMA_CCR_OPT_SB4         (0x3 << 4)
+/*! Source Burst length of 5 transfers. */
+#define ALT_DMA_CCR_OPT_SB5         (0x4 << 4)
+/*! Source Burst length of 6 transfers. */
+#define ALT_DMA_CCR_OPT_SB6         (0x5 << 4)
+/*! Source Burst length of 7 transfers. */
+#define ALT_DMA_CCR_OPT_SB7         (0x6 << 4)
+/*! Source Burst length of 8 transfers. */
+#define ALT_DMA_CCR_OPT_SB8         (0x7 << 4)
+/*! Source Burst length of 9 transfers. */
+#define ALT_DMA_CCR_OPT_SB9         (0x8 << 4)
+/*! Source Burst length of 10 transfers. */
+#define ALT_DMA_CCR_OPT_SB10        (0x9 << 4)
+/*! Source Burst length of 11 transfers. */
+#define ALT_DMA_CCR_OPT_SB11        (0xa << 4)
+/*! Source Burst length of 12 transfers. */
+#define ALT_DMA_CCR_OPT_SB12        (0xb << 4)
+/*! Source Burst length of 13 transfers. */
+#define ALT_DMA_CCR_OPT_SB13        (0xc << 4)
+/*! Source Burst length of 14 transfers. */
+#define ALT_DMA_CCR_OPT_SB14        (0xd << 4)
+/*! Source Burst length of 15 transfers. */
+#define ALT_DMA_CCR_OPT_SB15        (0xe << 4)
+/*! Source Burst length of 16 transfers. */
+#define ALT_DMA_CCR_OPT_SB16        (0xf << 4)
+/*! Source Burst length default transfers. */
+#define ALT_DMA_CCR_OPT_SB_DEFAULT  ALT_DMA_CCR_OPT_SB1
+
+/*
+ * Source Protection
+ */
+/*! Source Protection bits for AXI bus ARPROT[2:0]. */
+#define ALT_DMA_CCR_OPT_SP(imm3)    ((imm3) << 8)
+/*! Source Protection bits default value. */
+#define ALT_DMA_CCR_OPT_SP_DEFAULT  ALT_DMA_CCR_OPT_SP(0)
+
+/*
+ * Source cache
+ */
+/*! Source Cache bits for AXI bus ARCACHE[2:0]. */
+#define ALT_DMA_CCR_OPT_SC(imm4)    ((imm4) << 11)
+/*! Source Cache bits default value. */
+#define ALT_DMA_CCR_OPT_SC_DEFAULT  ALT_DMA_CCR_OPT_SC(0)
+
+/*
+ * Destination Address {Fixed,Incrementing}
+ */
+/*! Destination Address Fixed address burst. */
+#define ALT_DMA_CCR_OPT_DAF         (0 << 14)
+/*! Destination Address Incrementing address burst. */
+#define ALT_DMA_CCR_OPT_DAI         (1 << 14)
+/*! Destination Address Default value. */
+#define ALT_DMA_CCR_OPT_DA_DEFAULT  ALT_DMA_CCR_OPT_DAI
+
+/*
+ * Destination burst Size (in bits)
+ */
+/*! Destination burst Size of 8 bits. */
+#define ALT_DMA_CCR_OPT_DS8         (0 << 15)
+/*! Destination burst Size of 16 bits. */
+#define ALT_DMA_CCR_OPT_DS16        (1 << 15)
+/*! Destination burst Size of 32 bits. */
+#define ALT_DMA_CCR_OPT_DS32        (2 << 15)
+/*! Destination burst Size of 64 bits. */
+#define ALT_DMA_CCR_OPT_DS64        (3 << 15)
+/*! Destination burst Size of 128 bits. */
+#define ALT_DMA_CCR_OPT_DS128       (4 << 15)
+/*! Destination burst Size default bits. */
+#define ALT_DMA_CCR_OPT_DS_DEFAULT  ALT_DMA_CCR_OPT_DS8
+
+/*
+ * Destination Burst length (in transfer(s))
+ */
+/*! Destination Burst length of 1 transfer. */
+#define ALT_DMA_CCR_OPT_DB1         (0x0 << 18)
+/*! Destination Burst length of 2 transfers. */
+#define ALT_DMA_CCR_OPT_DB2         (0x1 << 18)
+/*! Destination Burst length of 3 transfers. */
+#define ALT_DMA_CCR_OPT_DB3         (0x2 << 18)
+/*! Destination Burst length of 4 transfers. */
+#define ALT_DMA_CCR_OPT_DB4         (0x3 << 18)
+/*! Destination Burst length of 5 transfers. */
+#define ALT_DMA_CCR_OPT_DB5         (0x4 << 18)
+/*! Destination Burst length of 6 transfers. */
+#define ALT_DMA_CCR_OPT_DB6         (0x5 << 18)
+/*! Destination Burst length of 7 transfers. */
+#define ALT_DMA_CCR_OPT_DB7         (0x6 << 18)
+/*! Destination Burst length of 8 transfers. */
+#define ALT_DMA_CCR_OPT_DB8         (0x7 << 18)
+/*! Destination Burst length of 9 transfers. */
+#define ALT_DMA_CCR_OPT_DB9         (0x8 << 18)
+/*! Destination Burst length of 10 transfers. */
+#define ALT_DMA_CCR_OPT_DB10        (0x9 << 18)
+/*! Destination Burst length of 11 transfers. */
+#define ALT_DMA_CCR_OPT_DB11        (0xa << 18)
+/*! Destination Burst length of 12 transfers. */
+#define ALT_DMA_CCR_OPT_DB12        (0xb << 18)
+/*! Destination Burst length of 13 transfers. */
+#define ALT_DMA_CCR_OPT_DB13        (0xc << 18)
+/*! Destination Burst length of 14 transfers. */
+#define ALT_DMA_CCR_OPT_DB14        (0xd << 18)
+/*! Destination Burst length of 15 transfers. */
+#define ALT_DMA_CCR_OPT_DB15        (0xe << 18)
+/*! Destination Burst length of 16 transfers. */
+#define ALT_DMA_CCR_OPT_DB16        (0xf << 18)
+/*! Destination Burst length default transfers. */
+#define ALT_DMA_CCR_OPT_DB_DEFAULT  ALT_DMA_CCR_OPT_DB1
+
+/*
+ * Destination Protection
+ */
+/*! Destination Protection bits for AXI bus AWPROT[2:0]. */
+#define ALT_DMA_CCR_OPT_DP(imm3)    ((imm3) << 22)
+/*! Destination Protection bits default value. */
+#define ALT_DMA_CCR_OPT_DP_DEFAULT  ALT_DMA_CCR_OPT_DP(0)
+
+/*
+ * Destination Cache
+ */
+/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */
+#define ALT_DMA_CCR_OPT_DC(imm4)    ((imm4) << 25)
+/*! Destination Cache bits default value. */
+#define ALT_DMA_CCR_OPT_DC_DEFAULT  ALT_DMA_CCR_OPT_DC(0)
+
+/*
+ * Endian Swap size (in bits)
+ */
+/*! Endian Swap: No swap, 8-bit data. */
+#define ALT_DMA_CCR_OPT_ES8         (0 << 28)
+/*! Endian Swap: Swap bytes within 16-bit data. */
+#define ALT_DMA_CCR_OPT_ES16        (1 << 28)
+/*! Endian Swap: Swap bytes within 32-bit data. */
+#define ALT_DMA_CCR_OPT_ES32        (2 << 28)
+/*! Endian Swap: Swap bytes within 64-bit data. */
+#define ALT_DMA_CCR_OPT_ES64        (3 << 28)
+/*! Endian Swap: Swap bytes within 128-bit data. */
+#define ALT_DMA_CCR_OPT_ES128       (4 << 28)
+/*! Endian Swap: Default byte swap. */
+#define ALT_DMA_CCR_OPT_ES_DEFAULT  ALT_DMA_CCR_OPT_ES8
+
+/*! Default CCR register options for a DMAMOV CCR assembler directive. */
+#define ALT_DMA_CCR_OPT_DEFAULT \
+    (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
+     ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
+     ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
+     ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
+     ALT_DMA_CCR_OPT_ES8)
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif /* __ALT_DMA_PROGRAM_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_fpga_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_fpga_manager.h
new file mode 100644
index 0000000..706f5d8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_fpga_manager.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_FPGA_MGR_H__
+#define __ALT_FPGA_MGR_H__
+
+#include "hwlib.h"
+#include "alt_dma.h"
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * \addtogroup FPGA_MGR The FPGA Manager
+ *
+ * This module defines the FPGA Manager API for accessing, configuring, and
+ * controlling the FPGA fabric and the FPGA/HPS interface.
+ *
+ * @{
+ */
+
+
+/*!
+ * This preprocessor definition determines if DMA support for FPGA programming
+ * is enabled or not. Enabling DMA support enables the following API:
+ *  * alt_fpga_configure_dma()
+ *  * alt_fpga_istream_configure_dma()
+ *
+ * To enable DMA support, define ALT_FPGA_ENABLE_DMA_SUPPORT=1 in the Makefile.
+ */
+#ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
+#define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
+#endif
+
+/*!
+ * Initializes the FPGA manager. This should be the first API called when using
+ * the FPGA manager API.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_fpga_init(void);
+
+/*!
+ * Uninitializes the FPGA manager
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_fpga_uninit(void);
+
+/*!
+ * \addtogroup FPGA_MGR_STATUS FPGA Manager Status and Control
+ *
+ * This group provides functions for controlling and determining status of the
+ * FPGA Manager.
+ *
+ * @{
+ */
+
+/*!
+ * Instructs the CPU core to acquire control of the FPGA control block. This
+ * must API must be called before any other API is issued.
+ *
+ * \retval      ALT_E_SUCCESS       Successful status.
+ * \retval      ALT_E_ERROR         Error acquiring control of the FPGA control
+ *                                  block. This is likely due to another device
+ *                                  on the system controlling the FPGA control
+ *                                  block or a repeat call to this API without
+ *                                  first being released.
+ */
+ALT_STATUS_CODE alt_fpga_control_enable(void);
+
+/*!
+ * Instructs the CPU core to release control of the FPGA control block. This
+ * API should be called after all FPGA related operations are completed. This
+ * will allow another device on the system to configure the FPGA.
+ *
+ * \retval      ALT_E_SUCCESS       Successful status.
+ * \retval      ALT_E_ERROR         Failure status.
+ */
+ALT_STATUS_CODE alt_fpga_control_disable(void);
+
+/*!
+ * Returns \b true if the HPS currently has control of the FPGA control block
+ * and \b false otherwise.
+ *
+ * \retval      true                HPS has control of the FPGA control block.
+ * \retval      false               HPS does not have control of the FPGA
+ *                                  control block.
+ */
+bool alt_fpga_control_is_enabled(void);
+
+/*!
+ * This type definition enumerates the possible states the FPGA can be in at
+ * any one time.
+ */
+typedef enum ALT_FPGA_STATE_e
+{
+    /*!
+     * FPGA in Power Up Phase. This is the state of the FPGA just after
+     * powering up.
+     *
+     * \internal
+     * Register documentation calls it "PWR_OFF" which is really a misnomer as
+     * the FPGA is powered as evident from alt_fpga_mon_status_get() and
+     * looking at the ALT_FPGA_MON_FPGA_POWER_ON bit.
+     * \endinternal
+     */
+    ALT_FPGA_STATE_POWER_UP = 0x0,
+
+    /*!
+     * FPGA in Reset Phase. In this phase, the FPGA resets, clears the FPGA
+     * configuration RAM bits, tri-states all FPGA user I/O pins, pulls the
+     * nSTATUS and CONF_DONE pins low, and determines the configuration mode
+     * by reading the value of the MSEL pins.
+     */
+    ALT_FPGA_STATE_RESET = 0x1,
+
+    /*!
+     * FPGA in Configuration Phase. This state represents the phase when the
+     * configuration bitstream is loaded into the FPGA fabric. The
+     * configuration phase is complete after the FPGA has received all the
+     * configuration data.
+     */
+    ALT_FPGA_STATE_CFG = 0x2,
+
+    /*!
+     * FPGA in Initialization Phase. In this state the FPGA prepares to enter
+     * User Mode. In Configuration via PCI Express (CVP), this state indicates
+     * I/O configuration has completed.
+     */
+    ALT_FPGA_STATE_INIT = 0x3,
+
+    /*!
+     * FPGA in User Mode. In this state, the FPGA performs the function loaded
+     * during the configuration phase. The FPGA user I/O are functional as
+     * determined at design time.
+     */
+    ALT_FPGA_STATE_USER_MODE = 0x4,
+
+    /*!
+     * FPGA state has not yet been determined. This only occurs briefly after
+     * reset.
+     */
+    ALT_FPGA_STATE_UNKNOWN = 0x5,
+
+    /*!
+     * FPGA is powered off.
+     *
+     * \internal
+     * This is a software only state which is determined by
+     * alt_fpga_mon_status_get() and looking at the ALT_FPGA_MON_FPGA_POWER_ON
+     * bit. The hardware register sourced for ALT_FPGA_STATE_t is only 3 bits
+     * wide so this will never occur in hardware.
+     * \endinternal
+     */
+    ALT_FPGA_STATE_POWER_OFF = 0xF
+
+} ALT_FPGA_STATE_t;
+
+/*!
+ * Returns the current operational state of the FPGA fabric.
+ *
+ * \returns     The current operational state of the FPGA.
+ */
+ALT_FPGA_STATE_t alt_fpga_state_get(void);
+
+/*!
+ * This type definition enumerates the monitored status conditions for the FPGA
+ * Control Block (CB).
+ */
+typedef enum ALT_FPGA_MON_STATUS_e
+{
+    /*!
+     * 0 if the FPGA is in Reset Phase or if the FPGA detected an error during
+     * the Configuration Phase.
+     */
+    ALT_FPGA_MON_nSTATUS = 0x0001,
+
+    /*!
+     * 0 during the FPGA Reset Phase and 1 when the FPGA Configuration Phase is
+     * done.
+     */
+    ALT_FPGA_MON_CONF_DONE = 0x0002,
+
+    /*!
+     * 0 during the FPGA Configuration Phase and 1 when the FPGA Initialization
+     * Phase is done.
+     */
+    ALT_FPGA_MON_INIT_DONE = 0x0004,
+
+    /*!
+     * CRC error indicator. A 1 indicates that the FPGA detected a CRC error
+     * while in User Mode.
+     */
+    ALT_FPGA_MON_CRC_ERROR = 0x0008,
+
+    /*!
+     * Configuration via PCIe (CVP) Done indicator. A 1 indicates that CVP is
+     * done.
+     */
+    ALT_FPGA_MON_CVP_CONF_DONE = 0x0010,
+
+    /*!
+     * Partial Reconfiguration ready indicator. A 1 indicates that the FPGA is
+     * ready to receive partial reconfiguration or external scrubbing data.
+     */
+    ALT_FPGA_MON_PR_READY = 0x0020,
+
+    /*!
+     * Partial Reconfiguration error indicator. A 1 indicates that the FPGA
+     * detected an error during partial reconfiguration or external scrubbing.
+     */
+    ALT_FPGA_MON_PR_ERROR = 0x0040,
+
+    /*!
+     * Partial Reconfiguration done indicator. A 1 indicates partial
+     * reconfiguration or external scrubbing is done.
+     */
+    ALT_FPGA_MON_PR_DONE = 0x0080,
+
+    /*!
+     * Value of the nCONFIG pin. This can be pulled-down by the FPGA in this
+     * device or logic external to this device connected to the nCONFIG pin.
+     * See the description of the nCONFIG field in this register to understand
+     * when the FPGA in this device pulls-down the nCONFIG pin. Logic external
+     * to this device pulls-down the nCONFIG pin to put the FPGA into the Reset
+     * Phase.
+     */
+    ALT_FPGA_MON_nCONFIG_PIN = 0x0100,
+
+    /*!
+     * Value of the nSTATUS pin. This can be pulled-down by the FPGA in this
+     * device or logic external to this device connected to the nSTATUS pin.
+     * See the description of the nSTATUS field in this register to understand
+     * when the FPGA in this device pulls-down the nSTATUS pin. Logic external
+     * to this device pulls-down the nSTATUS pin during Configuration Phase or
+     * Initialization Phase if it detected an error.
+     */
+    ALT_FPGA_MON_nSTATUS_PIN = 0x0200,
+
+    /*!
+     * Value of the CONF_DONE pin. This can be pulled-down by the FPGA in this
+     * device or logic external to this device connected to the CONF_DONE pin.
+     * See the description of the CONF_DONE field in this register to
+     * understand when the FPGA in this device pulls-down the CONF_DONE pin.
+     * See FPGA documentation to determine how logic external to this device
+     * drives CONF_DONE.
+     */
+    ALT_FPGA_MON_CONF_DONE_PIN = 0x0400,
+
+    /*!
+     * FPGA powered on indicator.
+     */
+    ALT_FPGA_MON_FPGA_POWER_ON = 0x0800,
+
+} ALT_FPGA_MON_STATUS_t;
+
+/*!
+ * Returns the FPGA Control Block monitor status conditions.
+ *
+ * This function returns the current value of the FPGA Control Block monitor
+ * status conditions.
+ *
+ * \returns     The current values of the FPGA Control Block monitor status
+ *              conditions as defined by the \ref ALT_FPGA_MON_STATUS_t mask
+ *              bits. If the corresponding bit is set then the condition is
+ *              asserted.
+ *
+ * \internal
+ * Use the Raw Interrupt Status Register \b hps::fpgamgrregs::mon::gpio_ext_porta
+ * to retrieve the monitor status conditions.
+ * \endinternal
+ */
+uint32_t alt_fpga_mon_status_get(void);
+
+/*!
+ * Assert and hold the FPGA in reset.
+ *
+ * This function asserts and holds the FPGA in reset. Any FPGA configuration is
+ * cleared. The FPGA must be reconfigured to resume operation.
+ * 
+ * The FPGA is reset by the assertion of the nCONFIG signal. The signal remains
+ * asserted until alt_fgpa_reset_deassert() is called.
+ *
+ * \retval      ALT_E_SUCCESS           Successful status.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ */
+ALT_STATUS_CODE alt_fgpa_reset_assert(void);
+
+/*!
+ * Deassert and release the FPGA from reset.
+ *
+ * This function deasserts the FPGA from reset. The FPGA must be reconfigured to
+ * resume operation.
+ * 
+ * The FPGA is reset by the deassertion of the nCONFIG signal. 
+ *
+ * \retval      ALT_E_SUCCESS           Successful status.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ */
+ALT_STATUS_CODE alt_fgpa_reset_deassert(void);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup FPGA_MGR_CFG FPGA Configuration
+ *
+ * This functional group provides the following services:
+ *  * Determination of the FPGA configuration mode.
+ *  * Software control for full configuration of the FPGA.
+ *  * Software control for partial reconfiguration of the FPGA \e (Future).
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the available modes for configuring the
+ * FPGA.
+ */
+typedef enum ALT_FPGA_CFG_MODE_e
+{
+    /*!
+     * 16-bit Passive Parallel with Fast Power on Reset Delay; No AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x1.
+     */
+    ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC = 0x0,
+
+    /*!
+     * 16-bit Passive Parallel with Fast Power on Reset Delay; With AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x4.
+     */
+    ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC = 0x1,
+
+    /*!
+     * 16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional;
+     * With Data Compression. CDRATIO must be programmed to x8.
+     */
+    ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC = 0x2,
+
+    /*!
+     * 16-bit Passive Parallel with Slow Power on Reset Delay; No AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x1.
+     */
+    ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC = 0x4,
+
+    /*!
+     * 16-bit Passive Parallel with Slow Power on Reset Delay; With AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x4.
+     */
+    ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC = 0x5,
+
+    /*!
+     * 16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional;
+     * With Data Compression. CDRATIO must be programmed to x8.
+     */
+    ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC = 0x6,
+
+    /*!
+     * 32-bit Passive Parallel with Fast Power on Reset Delay; No AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x1.
+     */
+    ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC = 0x8,
+
+    /*!
+     * 32-bit Passive Parallel with Fast Power on Reset Delay; With AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x4.
+     */
+    ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC = 0x9,
+
+    /*!
+     * 32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional;
+     * With Data Compression. CDRATIO must be programmed to x8.
+     */
+    ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC = 0xa,
+
+    /*!
+     * 32-bit Passive Parallel with Slow Power on Reset Delay; No AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x1.
+         */
+    ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC = 0xc,
+
+    /*!
+     * 32-bit Passive Parallel with Slow Power on Reset Delay; With AES
+     * Encryption; No Data Compression. CDRATIO must be programmed to x4.
+     */
+    ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC = 0xd,
+
+    /*!
+     * 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional;
+     * With Data Compression. CDRATIO must be programmed to x8.
+     */
+    ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC = 0xe,
+
+    /*!
+     * Unknown FPGA Configuration Mode.
+     */
+    ALT_FPGA_CFG_MODE_UNKNOWN = 0x20,
+
+} ALT_FPGA_CFG_MODE_t;
+
+/*!
+ * Gets the FPGA configuration mode currently in effect.
+ *
+ * Presently, the FPGA configuration mode is statically set by the external MSEL
+ * pin values and cannot be programmatically overridden by HPS software.
+ *
+ * \returns     The current FPGA configuration mode as determined by the MSEL
+ *              pin values.
+ */
+ALT_FPGA_CFG_MODE_t alt_fpga_cfg_mode_get(void);
+
+/*!
+ * Sets the FPGA configuration mode.
+ *
+ * Presently, the FPGA configuration mode is statically set by the external
+ * MSEL pin values and cannot be programmatically overridden by HPS software.
+ * This function should always return ALT_E_ERROR at least for Hammerhead-P.
+ * This may change with future SoCFPGA devices.
+ *
+ * \param       cfg_mode
+ *              The desired FPGA configuration mode.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_ERROR     Failed to set the FPGA configuration mode.
+ *
+ * \internal
+ * This should set the fpgamgrregs::stat::msel. The full configuration reads
+ * this to program the fpgamgrregs::ctrl with the appropriate parameters
+ * decoded from msel.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_fpga_cfg_mode_set(ALT_FPGA_CFG_MODE_t cfg_mode);
+
+/*!
+ * Type definition for the callback function prototype used by the FPGA Manager
+ * to read configuration bitstream data from a user defined input source
+ * stream.
+ *
+ * The purpose of this callback function declaration is to provide a prototype
+ * for a user defined method of sequentially reading FPGA configuration
+ * bitstream data from an arbitrary input source. Example input sources include
+ * a file resident on a file system, a network stream socket, or a fixed
+ * address block in flash memory. The only requirement on the input source is
+ * that it is capable of supplying consecutive blocks of data of the requested
+ * size from the FPGA configuration bitstream as demanded by the FPGA Manager.
+ *
+ * During FPGA configuration, the FPGA Manager periodically calls the user
+ * defined callback function to fetch the next \e buf_len consecutive
+ * configuration data bytes from the user defined input stream. The callback
+ * function fills the FPGA Manager supplied buffer \e buf with up to the next
+ * \e buf_len bytes of configuration bitsteam data as read from the input
+ * source stream. The callback function returns the number of configuration
+ * bytes read into \e buf or 0 upon reaching the end of the configuration
+ * bitstream data.
+ *
+ * If an error occurs on the configuration bitstream input source, then the
+ * callback function should return an error code value less than 0.
+ *
+ * \param       buf
+ *              A pointer to a buffer to fill with FPGA configuration bitstream
+ *              data bytes.
+ *
+ * \param       buf_len
+ *              The length of the input buffer \e buf in bytes. The number of
+ *              FPGA configuration bitstream data bytes copied into \e buf
+ *              should not exceed \e buf_len.
+ *
+ * \param       user_data
+ *              A 32-bit data word for passing user defined data. The content
+ *              of this parameter is user defined. The FPGA Manager merely
+ *              forwards the \e user_data value when it invokes the callback.
+ * 
+ * \retval      >0      The number of bytes returned in buf.
+ * \retval      =0      The end of the input stream has been reached.
+ * \retval      <0      An error occurred on the input stream.
+ */
+typedef int32_t (*alt_fpga_istream_t)(void* buf, size_t buf_len, void* user_data);
+
+/*!
+ * \addtogroup FPGA_MGR_CFG_FULL FPGA Full Configuration
+ *
+ * These functions manage full configuration of the FPGA fabric from HPS
+ * software.
+ *
+ * @{
+ */
+
+/*!
+ * Perform a full configuration of the FPGA from the specified configuration
+ * bitstream located in addressable memory.
+ *
+ * Due to the nature of FPGA configuration, there may be intermittent and
+ * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG,
+ * it is advisable to retry configuration up to 5 times. If the error still
+ * persists, there may be an unrecoverable configuration error or a problem
+ * with configuration image bitstream data.
+ *
+ * \internal
+ * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted
+ * configuration file"
+ * \endinternal
+ *
+ * \param       cfg_buf
+ *              A pointer to a buffer containing FPGA configuration bitstream
+ *              data.
+ *
+ * \param       cfg_buf_len
+ *              The length of the configuration bitstream data in bytes.
+ *
+ * \retval      ALT_E_SUCCESS           FPGA configuration was successful.
+ * \retval      ALT_E_FPGA_CFG          FPGA configuration error detected.
+ * \retval      ALT_E_FPGA_CRC          FPGA CRC error detected.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ */
+ALT_STATUS_CODE alt_fpga_configure(const void* cfg_buf,
+                                   size_t cfg_buf_len);
+
+#if ALT_FPGA_ENABLE_DMA_SUPPORT
+
+/*!
+ * Perform a full configuration of the FPGA from the specified configuration
+ * bitstream located in addressable memory using the DMA engine. Using DMA can
+ * have a large performance benefit in FPGA programming time.
+ *
+ * Due to the nature of FPGA configuration, there may be intermittent and
+ * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG,
+ * it is advisable to retry configuration up to 5 times. If the error still
+ * persists, there may be an unrecoverable configuration error or a problem
+ * with configuration image bitstream data.
+ *
+ * \internal
+ * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted
+ * configuration file"
+ * \endinternal
+ *
+ * \param       cfg_buf
+ *              A pointer to a buffer containing FPGA configuration bitstream
+ *              data.
+ *
+ * \param       cfg_buf_len
+ *              The length of the configuration bitstream data in bytes.
+ *
+ * \retval      ALT_E_SUCCESS           FPGA configuration was successful.
+ * \retval      ALT_E_FPGA_CFG          FPGA configuration error detected.
+ * \retval      ALT_E_FPGA_CRC          FPGA CRC error detected.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ * \retval      ALT_E_BAD_ARG           The user provided buffer is unaligned
+ *                                      to the 32-bit boundary.
+ */
+
+ALT_STATUS_CODE alt_fpga_configure_dma(const void* cfg_buf,
+                                       size_t cfg_buf_len,
+                                       ALT_DMA_CHANNEL_t dma_channel);
+
+#endif
+
+/*!
+ * Perform a full configuration of the FPGA from the user defined configuration
+ * bitstream input source.
+ *
+ * Due to the nature of FPGA configuration, there may be intermittent and
+ * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG,
+ * it is advisable to retry configuration up to 5 times. If the error still
+ * persists, there may be an unrecoverable configuration error or a problem
+ * with configuration image bitstream data.
+ *
+ * \internal
+ * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted
+ * configuration file"
+ * \endinternal
+ *
+ * \param       cfg_stream
+ *              A pointer to a callback function used to consecutively read
+ *              configuration bitstream data from a user defined input stream.
+ * 
+ * \param       user_data
+ *              A 32-bit user defined data word. The content of this parameter
+ *              is user defined. The FPGA Manager merely forwards the \e
+ *              user_data value when it invokes the \e cfg_stream callback.
+ *
+ * \retval      ALT_E_SUCCESS           FPGA configuration FPGA was successful.
+ * \retval      ALT_E_FPGA_CFG          FPGA configuration error detected.
+ * \retval      ALT_E_FPGA_CRC          FPGA CRC error detected.
+ * \retval      ALT_E_FPGA_CFG_STM      An error occurred on the FPGA
+ *                                      configuration bitstream input source.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ */
+ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream,
+                                           void * user_data);
+
+#if ALT_FPGA_ENABLE_DMA_SUPPORT
+
+/*!
+ * Perform a full configuration of the FPGA from the user defined configuration
+ * bitstream input source using the DMA engine. Using DMA can have a large
+ * performance benefit in FPGA programming time.
+ *
+ * Due to the nature of FPGA configuration, there may be intermittent and
+ * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG,
+ * it is advisable to retry configuration up to 5 times. If the error still
+ * persists, there may be an unrecoverable configuration error or a problem
+ * with configuration image bitstream data.
+ *
+ * \internal
+ * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted
+ * configuration file"
+ * \endinternal
+ *
+ * \param       cfg_stream
+ *              A pointer to a callback function used to consecutively read
+ *              configuration bitstream data from a user defined input stream.
+ * 
+ * \param       user_data
+ *              A 32-bit user defined data word. The content of this parameter
+ *              is user defined. The FPGA Manager merely forwards the \e
+ *              user_data value when it invokes the \e cfg_stream callback.
+ *
+ * \retval      ALT_E_SUCCESS           FPGA configuration FPGA was successful.
+ * \retval      ALT_E_FPGA_CFG          FPGA configuration error detected.
+ * \retval      ALT_E_FPGA_CRC          FPGA CRC error detected.
+ * \retval      ALT_E_FPGA_CFG_STM      An error occurred on the FPGA
+ *                                      configuration bitstream input source.
+ * \retval      ALT_E_FPGA_PWR_OFF      FPGA is not powered on.
+ * \retval      ALT_E_FPGA_NO_SOC_CTRL  SoC software is not in control of the
+ *                                      FPGA. Use alt_fpga_control_enable() to
+ *                                      gain control.
+ * \retval      ALT_E_BAD_ARG           The user provided buffer is unaligned
+ *                                      to the 32-bit boundary.
+ */
+ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream,
+                                               void * user_data,
+                                               ALT_DMA_CHANNEL_t dma_channel);
+
+#endif
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup FPGA_MGR_INT FPGA Manager Interrupt Control
+ *
+ * The functions in this group provide management of interrupts originating
+ * from the FPGA Manager.
+ *
+ * The following interrupt request (IRQ) signal is sourced from the FPGA
+ * Manager:
+ *
+ * * \b fpga_man_IRQ - FPGA Manager control block interrupt output. Provides
+ *                     monitoring of the configuration and operational status
+ *                     of the FPGA.  The interrupt signal assertion value is
+ *                     the logical \e OR of twelve sources that monitor the
+ *                     status of the FPGA control block (CB).  The twelve FPGA
+ *                     CB interrupt sources are enumerated and described by the
+ *                     type \ref ALT_FPGA_MON_STATUS_t.
+ *
+ *                     Each FPGA monitor status condition may be individually
+ *                     disabled/enabled as a contributor to the determination
+ *                     of the \b fpga_man_IRQ assertion status.
+ *
+ *                     The \b fpga_man_IRQ and its contributing FPGA monitor
+ *                     status conditions are treated as a level sensitive
+ *                     interrupt. As as consequence, there are no explicit
+ *                     functions to explicitly clear an asserted FPGA monitor
+ *                     status conditions.
+ *
+ * @{
+ */
+
+/*!
+ * Disable the \b fpga_man_IRQ interrupt signal source monitor status
+ * condition(s).
+ *
+ * This function disables one or more of the monitor status conditions as
+ * contributors to the \b fpga_man_IRQ interrupt signal state.
+ *
+ * NOTE: A set bit for a monitor status condition in the mask value does not
+ * have the effect of enabling it as a contributor to the \b fpga_man_IRQ
+ * interrupt signal state. The function alt_fpga_man_irq_enable() is used to
+ * enable monitor status source condition(s).
+ *
+ * \param       mon_stat_mask
+ *              Specifies the monitor status conditions to disable as interrupt
+ *              source contributors. \e mon_stat_mask is a mask of logically
+ *              OR'ed ALT_FPGA_MON_STATUS_t values that designate the monitor
+ *              status conditions to disable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e mon_stat_mask argument contains an
+ *                              unknown monitor status value.
+ */
+ALT_STATUS_CODE alt_fpga_man_irq_disable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
+
+/*!
+ * Enable the \b fpga_man_IRQ interrupt signal source monitor status
+ * condition(s).
+ *
+ * This function enables one or more of the monitor status conditions as
+ * contributors to the \b fpga_man_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any monitor status condition in the mask value does
+ * not have the effect of disabling it as a contributor to the \b fpga_man_IRQ
+ * interrupt signal state. The function alt_fpga_man_irq_disable() is used to
+ * disable monitor status source condition(s).
+ *
+ * \param       mon_stat_mask
+ *              Specifies the monitor status conditions to enable as interrupt
+ *              source contributors. \e mon_stat_mask is a mask of logically
+ *              OR'ed ALT_FPGA_MON_STATUS_t values that designate the monitor
+ *              conditions to enable.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_BAD_ARG   The \e mon_stat_mask argument contains an
+ *                              unknown monitor status value.
+ */
+ALT_STATUS_CODE alt_fpga_man_irq_enable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup FPGA_MGR_GPIO SoC to FPGA General Purpose I/O Signals
+ *
+ * These functions provide a simple, low-latency, low-performance signal
+ * interface between the SoC and the FPGA.  There is a General Purpose Output
+ * (GPO) register that provides a path to drive up to 32 signals from the SoC
+ * to the FPGA.  There is a General Purpose Input (GPI) register that provides
+ * a path to read up to 32 signals driven from the FPGA to the SoC.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the signal mask selections for the General
+ * Purpose Input (GPI) signals driven from the FPGA to the SoC.
+ */
+typedef enum ALT_FPGA_GPI_e
+{
+    /*! Signal driven from the FPGA fabric on f2s_gp[0] */
+    ALT_FPGA_GPI_0  = (int32_t)(1UL <<  0),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[1] */
+    ALT_FPGA_GPI_1  = (int32_t)(1UL <<  1),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[2] */
+    ALT_FPGA_GPI_2  = (int32_t)(1UL <<  2),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[3] */
+    ALT_FPGA_GPI_3  = (int32_t)(1UL <<  3),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[4] */
+    ALT_FPGA_GPI_4  = (int32_t)(1UL <<  4),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[5] */
+    ALT_FPGA_GPI_5  = (int32_t)(1UL <<  5),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[6] */
+    ALT_FPGA_GPI_6  = (int32_t)(1UL <<  6),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[7] */
+    ALT_FPGA_GPI_7  = (int32_t)(1UL <<  7),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[8] */
+    ALT_FPGA_GPI_8  = (int32_t)(1UL <<  8),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[9] */
+    ALT_FPGA_GPI_9  = (int32_t)(1UL <<  9),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[10] */
+    ALT_FPGA_GPI_10 = (int32_t)(1UL << 10),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[11] */
+    ALT_FPGA_GPI_11 = (int32_t)(1UL << 11),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[12] */
+    ALT_FPGA_GPI_12 = (int32_t)(1UL << 12),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[13] */
+    ALT_FPGA_GPI_13 = (int32_t)(1UL << 13),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[14] */
+    ALT_FPGA_GPI_14 = (int32_t)(1UL << 14),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[15] */
+    ALT_FPGA_GPI_15 = (int32_t)(1UL << 15),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[16] */
+    ALT_FPGA_GPI_16 = (int32_t)(1UL << 16),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[17] */
+    ALT_FPGA_GPI_17 = (int32_t)(1UL << 17),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[18] */
+    ALT_FPGA_GPI_18 = (int32_t)(1UL << 18),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[19] */
+    ALT_FPGA_GPI_19 = (int32_t)(1UL << 19),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[20] */
+    ALT_FPGA_GPI_20 = (int32_t)(1UL << 20),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[21] */
+    ALT_FPGA_GPI_21 = (int32_t)(1UL << 21),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[22] */
+    ALT_FPGA_GPI_22 = (int32_t)(1UL << 22),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[23] */
+    ALT_FPGA_GPI_23 = (int32_t)(1UL << 23),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[24] */
+    ALT_FPGA_GPI_24 = (int32_t)(1UL << 24),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[25] */
+    ALT_FPGA_GPI_25 = (int32_t)(1UL << 25),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[26] */
+    ALT_FPGA_GPI_26 = (int32_t)(1UL << 26),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[27] */
+    ALT_FPGA_GPI_27 = (int32_t)(1UL << 27),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[28] */
+    ALT_FPGA_GPI_28 = (int32_t)(1UL << 28),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[29] */
+    ALT_FPGA_GPI_29 = (int32_t)(1UL << 29),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[30] */
+    ALT_FPGA_GPI_30 = (int32_t)(1UL << 30),
+
+    /*! Signal driven from the FPGA fabric on f2s_gp[31] */
+    ALT_FPGA_GPI_31 = (int32_t)(1UL << 31)
+
+} ALT_FPGA_GPI_t;
+
+/*!
+ * Reads the General Purpose Input (GPI) register value.
+ *
+ * Returns the GPI register value that is the masked selection of the 32 \b
+ * f2s_gp signal values driven by the FPGA. The \e mask may be defined by the
+ * logical OR of \ref ALT_FPGA_GPI_t values.
+ *
+ * NOTE: If the FPGA is not in User Mode then the value of this register
+ *       undefined.
+ *
+ * \param       mask
+ *              The set of signals (where mask bits equal one) to read.  Other
+ *              signals values (where mask bits equal zero) are returned as 0.
+ *
+ * \returns     Returns the GPI register value that is the masked selection of
+ *              the 32 \b f2s_gp signals from the FPGA.
+ */
+uint32_t alt_fpga_gpi_read(uint32_t mask);
+
+/*!
+ * This type definition enumerates the signal mask selections for the General
+ * Purpose Output (GPO) signals driven from the SoC to the FPGA.
+ */
+typedef enum ALT_FPGA_GPO_e
+{
+    /*! Signal driven from the FPGA fabric on s2f_gp[0] */
+    ALT_FPGA_GPO_0  = (int32_t)(1UL <<  0),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[1] */
+    ALT_FPGA_GPO_1  = (int32_t)(1UL <<  1),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[2] */
+    ALT_FPGA_GPO_2  = (int32_t)(1UL <<  2),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[3] */
+    ALT_FPGA_GPO_3  = (int32_t)(1UL <<  3),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[4] */
+    ALT_FPGA_GPO_4  = (int32_t)(1UL <<  4),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[5] */
+    ALT_FPGA_GPO_5  = (int32_t)(1UL <<  5),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[6] */
+    ALT_FPGA_GPO_6  = (int32_t)(1UL <<  6),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[7] */
+    ALT_FPGA_GPO_7  = (int32_t)(1UL <<  7),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[8] */
+    ALT_FPGA_GPO_8  = (int32_t)(1UL <<  8),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[9] */
+    ALT_FPGA_GPO_9  = (int32_t)(1UL <<  9),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[10] */
+    ALT_FPGA_GPO_10 = (int32_t)(1UL << 10),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[11] */
+    ALT_FPGA_GPO_11 = (int32_t)(1UL << 11),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[12] */
+    ALT_FPGA_GPO_12 = (int32_t)(1UL << 12),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[13] */
+    ALT_FPGA_GPO_13 = (int32_t)(1UL << 13),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[14] */
+    ALT_FPGA_GPO_14 = (int32_t)(1UL << 14),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[15] */
+    ALT_FPGA_GPO_15 = (int32_t)(1UL << 15),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[16] */
+    ALT_FPGA_GPO_16 = (int32_t)(1UL << 16),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[17] */
+    ALT_FPGA_GPO_17 = (int32_t)(1UL << 17),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[18] */
+    ALT_FPGA_GPO_18 = (int32_t)(1UL << 18),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[19] */
+    ALT_FPGA_GPO_19 = (int32_t)(1UL << 19),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[20] */
+    ALT_FPGA_GPO_20 = (int32_t)(1UL << 20),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[21] */
+    ALT_FPGA_GPO_21 = (int32_t)(1UL << 21),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[22] */
+    ALT_FPGA_GPO_22 = (int32_t)(1UL << 22),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[23] */
+    ALT_FPGA_GPO_23 = (int32_t)(1UL << 23),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[24] */
+    ALT_FPGA_GPO_24 = (int32_t)(1UL << 24),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[25] */
+    ALT_FPGA_GPO_25 = (int32_t)(1UL << 25),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[26] */
+    ALT_FPGA_GPO_26 = (int32_t)(1UL << 26),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[27] */
+    ALT_FPGA_GPO_27 = (int32_t)(1UL << 27),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[28] */
+    ALT_FPGA_GPO_28 = (int32_t)(1UL << 28),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[29] */
+    ALT_FPGA_GPO_29 = (int32_t)(1UL << 29),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[30] */
+    ALT_FPGA_GPO_30 = (int32_t)(1UL << 30),
+
+    /*! Signal driven from the FPGA fabric on s2f_gp[31] */
+    ALT_FPGA_GPO_31 = (int32_t)(1UL << 31)
+
+} ALT_FPGA_GPO_t;
+
+/*!
+ * Writes the General Purpose Output (GPO) register value.
+ *
+ * Writes the GPO data outputs with the specified values. The GPO drives the 32
+ * \b s2f_gp signal values to the FPGA. Output signals are only written if
+ * their corresponding mask bits are set.
+ *
+ * NOTE: If the FPGA is not in User Mode then the effect of this operation is 
+ *       undefined.
+ *
+ * \param       mask
+ *              The set of signals (where mask bits equal one) to write.  Other
+ *              signals (where mask bits equal zero) are not changed. The \e
+ *              mask may be defined by the logical OR of \ref ALT_FPGA_GPO_t
+ *              values.
+ *
+ * \param       value
+ *              The 32-bit aggregate GPO register value. Values for the
+ *              corressponding signal bits specified in the \e mask are written
+ *              to the FPGA signals.
+ *
+ * \retval      ALT_E_SUCCESS   Successful status.
+ * \retval      ALT_E_ERROR     The write failed.
+ */
+ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __ALT_FPGA_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h
new file mode 100644
index 0000000..d8a38f5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h
@@ -0,0 +1,1236 @@
+/*! \file
+ *  Altera - GPIO Module
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_GPIO_H__
+#define __ALT_GPIO_H__
+
+#include <stdint.h>
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+#define     ALT_GPIO_BITMASK                0x1FFFFFFF
+
+/* If the GPIO special test mode flag was not defined in the makefile,   */
+    /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that     */
+    /* the production code version of alt_gpio_port_data_read() is included. */
+    /* If the flag is defined as true in the makefile, then the test version */
+    /* located in the test code file is substituted instead of the version   */
+    /* in this file.                                                         */
+#ifndef     ALT_GPIO_DATAREAD_TEST_MODE
+#define     ALT_GPIO_DATAREAD_TEST_MODE     false
+#endif
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API
+ *
+ * This module defines the General Purpose Input/Output Manager API for 
+ * accessing, configuring, and controlling the General Purpose Input/Output 
+ * Manager resources. These include both the general-purpose GPIO signals and
+ * the input-only GPI signals that are shared with the DDR interface.\n \n
+ * The GPIO API presents two views or perspectives of the GPIO signals. The first
+ * is to view the GPIO signals in a traditional way, as separate GPIO ports
+ * each comprised of a number of GPIO bits. The second perspective is of a
+ * unified flat view that presents the GPIO and GPI signals as a set of indexed
+ * bits, a view that allows the programmer to mostly ignore the port and pin
+ * hardware configuration and read/write/configure the GPIO and GPI signals
+ * independently of the underlying hardware implementation.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * This functional group contains functions to control, configure and manage
+ * the general-purpose IO signals as individual signals or as groups of signals.
+ * This group of functions can operate on multiple bits within the same GPIO
+ * port and accepts a bit mask to specify which bits an operation will operate on.
+ * Other bits within the same GPIO port are not changed.
+ *
+ * This example shows how multiple drivers or applications can use this feature
+ * to easily prevent conflict while accessing the same GPIO port:
+ * \verbatim
+ #define DRIVER_0_GPIO_MSK   0x0010FF03;
+ #define DRIVER_1_GPIO_MSK   0x002000F8;
+ #define DRIVER_2_GPIO_MSK   0x03C00004;
+ #define DRIVER_3_GPIO_MSK   0x000F0000;
+
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2);
+    alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3);
+    alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1);
+ \endverbatim
+ *
+ *  @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the data direction (input or output) of 
+ * the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_DIR_e
+{
+    /*! # */
+    ALT_GPIO_PIN_INPUT,
+    /*! # */
+    ALT_GPIO_PIN_OUTPUT
+} ALT_GPIO_PIN_DIR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the type of interrupt source 
+ * (level-triggered or edge-triggered) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_TYPE_e
+{
+    /*! # */
+    ALT_GPIO_PIN_LEVEL_TRIG_INT,
+    /*! # */
+    ALT_GPIO_PIN_EDGE_TRIG_INT
+} ALT_GPIO_PIN_TYPE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the polarity of the interrupt sources 
+ * (falling-edge or rising-edge for edge-triggered interrupts, active-low or
+ * active-high for level-triggered interrupts) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_POL_e
+{
+    /*! Indicates active-low for level-triggered interrupts and
+     * falling-edge for edge-triggered interrupts */
+    ALT_GPIO_PIN_ACTIVE_LOW,
+
+    /*! Indicates active-high for level-triggered interrupts and
+     * rising-edge for edge-triggered interrupt */
+    ALT_GPIO_PIN_ACTIVE_HIGH
+} ALT_GPIO_PIN_POL_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not the debounce metastability
+ * flip-flops are inserted or not. These are used to debounce signals presented
+ * to the GPIO inputs. A signal must be steady for two periods of the
+ * gpio_db_clk clock before it is considered valid. The frequency of the
+ * gpio_db_clk clock may be set using the Clock Manager API.
+ */
+
+typedef enum ALT_GPIO_PIN_DEBOUNCE_e
+{
+    /*! # */
+    ALT_GPIO_PIN_NODEBOUNCE,
+    /*! # */
+    ALT_GPIO_PIN_DEBOUNCE
+} ALT_GPIO_PIN_DEBOUNCE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not level-sensitive interrupts
+ * are synchronized to the internal pclk_intr clock. It has no effect for GPIO
+ * signals that are selected as outputs, or if the interrupt is not enabled,
+ * or if the interrupt is set to be edge-triggered. This is a port-wide option.
+ */
+
+typedef enum ALT_GPIO_PIN_SYNC_e
+{
+    /*! # */
+    ALT_GPIO_PIN_NOSYNC,
+    /*! # */
+    ALT_GPIO_PIN_SYNC
+} ALT_GPIO_PIN_SYNC_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the possible data states of the GPIO bits.
+ */
+
+typedef enum ALT_GPIO_PIN_DATA_e
+{
+    /*! # */
+    ALT_GPIO_PIN_DATAZERO,
+    /*! # */
+    ALT_GPIO_PIN_DATAONE
+} ALT_GPIO_PIN_DATA_t;
+
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the GPIO ports that the GPIO manager 
+ * handles.
+ */
+
+typedef enum ALT_GPIO_PORT_e
+{
+    /*!
+     * \b Port \b A - 29-bit GPIO port A.
+     */
+    ALT_GPIO_PORTA,
+
+    /*!
+     * \b Port \b B - 29-bit GPIO port B.
+     */
+    ALT_GPIO_PORTB,
+    
+    /*!
+     * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals,
+     *                14 bits are used for GPI-only signals that are shared
+     *                with the DDR interface, 2 bits are not used. Some signals
+     *                may not be connected on some versions. See the relevant
+     *                pin mux data.
+     */
+    ALT_GPIO_PORTC,
+
+    /*!
+     * \b Unknown \b Port - Used to indicate an error.
+     */
+    ALT_GPIO_PORT_UNKNOWN
+} ALT_GPIO_PORT_t;
+
+    
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits within the GPIO ports
+ * used by the GPIO manager. The bit-ordering must match the hardware 
+ * bit-ordering. Since the ordering and packing of bitfields is not 
+ * standardized in C/C++, the following are defined as masks. \n
+ * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits
+ * had previously been set to outputs), the user could use the syntax: \par
+ * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b
+ * ALT_GPIO_BIT4);
+ */
+
+typedef enum ALT_GPIO_PORTBIT_e
+{
+    /*! # */
+    ALT_GPIO_BIT0 = ALT_TWO_TO_POW0,
+    /*! # */
+    ALT_GPIO_BIT1 = ALT_TWO_TO_POW1,
+    /*! # */
+    ALT_GPIO_BIT2 = ALT_TWO_TO_POW2,
+    /*! # */
+    ALT_GPIO_BIT3 = ALT_TWO_TO_POW3,
+    /*! # */
+    ALT_GPIO_BIT4 = ALT_TWO_TO_POW4,
+    /*! # */
+    ALT_GPIO_BIT5 = ALT_TWO_TO_POW5,
+    /*! # */
+    ALT_GPIO_BIT6 = ALT_TWO_TO_POW6,
+    /*! # */
+    ALT_GPIO_BIT7 = ALT_TWO_TO_POW7,
+    /*! #  */
+    ALT_GPIO_BIT8 = ALT_TWO_TO_POW8,
+    /*! # */
+    ALT_GPIO_BIT9 = ALT_TWO_TO_POW9,
+    /*! # */
+    ALT_GPIO_BIT10 = ALT_TWO_TO_POW10,
+    /*! # */
+    ALT_GPIO_BIT11 = ALT_TWO_TO_POW11,
+    /*! # */
+    ALT_GPIO_BIT12 = ALT_TWO_TO_POW12,
+    /*! # */
+    ALT_GPIO_BIT13 = ALT_TWO_TO_POW13,
+    /*! # */
+    ALT_GPIO_BIT14 = ALT_TWO_TO_POW14,
+    /*! # */
+    ALT_GPIO_BIT15 = ALT_TWO_TO_POW15,
+    /*! # */
+    ALT_GPIO_BIT16 = ALT_TWO_TO_POW16,
+    /*! # */
+    ALT_GPIO_BIT17 = ALT_TWO_TO_POW17,
+    /*! # */
+    ALT_GPIO_BIT18 = ALT_TWO_TO_POW18,
+    /*! # */
+    ALT_GPIO_BIT19 = ALT_TWO_TO_POW19,
+    /*! # */
+    ALT_GPIO_BIT20 = ALT_TWO_TO_POW20,
+    /*! # */
+    ALT_GPIO_BIT21 = ALT_TWO_TO_POW21,
+    /*! # */
+    ALT_GPIO_BIT22 = ALT_TWO_TO_POW22,
+    /*! # */
+    ALT_GPIO_BIT23 = ALT_TWO_TO_POW23,
+    /*! # */
+    ALT_GPIO_BIT24 = ALT_TWO_TO_POW24,
+    /*! # */
+    ALT_GPIO_BIT25 = ALT_TWO_TO_POW25,
+    /*! # */
+    ALT_GPIO_BIT26 = ALT_TWO_TO_POW26,
+    /*! # */
+    ALT_GPIO_BIT27 = ALT_TWO_TO_POW27,
+    /*! # */
+    ALT_GPIO_BIT28 = ALT_TWO_TO_POW28,
+    ALT_GPIO_BIT29 = ALT_TWO_TO_POW29,              /* Not currently used */
+    ALT_GPIO_BIT30 = ALT_TWO_TO_POW30,              /* Not currently used */
+    ALT_GPIO_BIT31 = (int32_t) (1UL<<31),           /* Not currently used */
+
+    ALT_GPIO_BITNUM_MAX = (28),
+    ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX),
+    ALT_END_OF_GPIO_PORT_SIGNALS = (32)
+} ALT_GPIO_PORTBIT_t;
+
+
+
+/******************************************************************************/
+/*!
+ * Sets the specified GPIO data bits to use the data direction(s) 
+ * specified.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are 
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure all data direction bits of the port.
+ * \param       config
+ *              The data-directions of the bits to be set in this operation.
+ *              Individual bits are: \n \b 0 - Use as an input (default). \n 
+ *              \b 1 - Use as an output.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the data direction configuration of selected bits of the 
+ * specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to read and
+ *              return. Other bits (where mask bits equal zero) are returned 
+ *              as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              return all data direction bits of the port.
+ *
+ * \retval      uint32_t \n Individual bits are: \n \b 0 - The signal is 
+ *              configured as an input.
+ *              \n \b 1 - The signal is configured as an output.
+ *
+ */
+uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the GPIO data outputs of the specified GPIO module to a logic one or
+ * zero. Outputs are only set if the data direction for those bits is also
+ * set to configure them as outputs.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (mask bits equal one) to apply this
+ *              operation to. Other bits (mask bits equal zero) are
+ *              not changed.
+ * \param       val
+ *              The 32-bit word to write to the GPIO outputs. Only the 29 LSBs 
+ *              are used. Setting the three MSBs causes an error.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the value of the data inputs of the specified GPIO module. This is
+ * the current logic value of the pin, whether set to be an input or an output.
+ * \n If a given signal is set to be an output, this input value can be read to
+ * determine if the pin is grounded, pulled high, or is floating.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of
+ *              the port.
+ *
+ * \retval      uint32_t   The current value of the GPIO module input signals.
+ */
+uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ * This functional group contains functions to control and manage the
+ * interrupts of the General-Purpose IO modules.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets edge-triggered or level-triggered interrupt configuration for the 
+ * specified signals of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure all interrupt type bits of the port.
+ * \param       config
+ *              The interrupt configuration to write. Individual bits 
+ *              are: \n \b 0 - Set the 
+ *              interrupt for this bit to be level-sensitive (default). \n \b 
+ *              1 - Set the interrupt for this bit to be edge-sensitive.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt configuration (edge-triggered or level-triggered) for 
+ * the specified bits of the specified GPIO module. 
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration
+ *              bits of the port.
+ * \retval      uint32_t
+ *              The current interrupt source configuration. Individual bits 
+ *              are: \n \b 0 - The interrupt for this bit is set to be 
+ *              level-sensitive. \n \b 1 - 
+ *              The interrupt for this bit is set to be edge-sensitive.
+ *
+ */
+uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the interrupt polarity of the signals of the specified GPIO register
+ * (when used as inputs) to active-high or active-low (for level-sensitive
+ * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts).
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed.
+ * \param       config
+ *              The interrupt polarity configuration to set. Individual bits 
+ *              are: \n \b 0 - Set the interrupt polarity for this bit to 
+ *              active-low or falling-edge mode (default). \n \b 1 - Set the
+ *              interrupt polarity for this bit to active-high or rising-edge mode.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the active-high or active-low polarity configuration for the 
+ * possible interrupt sources of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the
+ *              configuration bits of the port.
+ *                 
+ * \retval      uint32_t
+ *              The current polarity configuration. Individual bits are: \n 
+ *              \b 0 = The interrupt polarity for this bit is set to 
+ *              active-low or falling-edge mode. \n \b 1 = The interrupt
+ *              polarity for this bit is set to active-high or rising-edge mode.
+ *
+ */
+uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets the debounce configuration for input signals of the specified GPIO 
+ * module. If debounce is selected, metastability flip-flops are inserted to
+ * debounce signals presented to the GPIO inputs. A signal must be steady for
+ * two periods of the gpio_db_clk clock before it is considered valid. The
+ * frequency of the gpio_db_clk clock may be set using the Clock Manager API.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to apply this 
+ *              operation to. Other bits (where mask bits equal zero) are
+ *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ *              configure the debounce setting for all bits of the port.
+ * \param       config
+ *              The debounce configuration to set. Individual bits are: \n
+ *              \b 0 - Debounce is not selected for this signal (default). \n 
+ *              \b 1 - Debounce is selected for this signal.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the debounce configuration for the input signals of the specified
+ * GPIO register. If debounce is selected, metastability flip-flops are
+ * inserted to debounce signals presented to the GPIO inputs.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits (where mask bits equal one) to return. Other 
+ *              bits (where mask bits equal zero) are returned as zero. Specify 
+ *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce
+ *              configuration bits of the port.
+ *                 
+ * \retval      uint32_t
+ *              The current debounce configuration.Individual bits are: \n 
+ *              \b 0 - Debounce is not selected for this signal. \n \b 1 - 
+ *              Debounce is selected for this signal.
+ *
+ */
+uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the synchronization configuration for the signals of the specified 
+ * GPIO register. This allows for synchronizing level-sensitive interrupts to 
+ * an internal clock signal. This is a port-wide option that controls all
+ * level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              \n \b Any \b non-zero \b value - Synchronize to internal clock signal.
+ *              \n \b Zero - Do not synchronize to internal clock signal.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t config);
+
+/******************************************************************************/
+/*!
+ *
+ * Returns the synchronization configuration for the signals of the 
+ * specified GPIO register. This allows for synchronizing level-sensitive 
+ * interrupts to the internal clock signal. This is a port-wide option that
+ * controls all level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+
+
+ * \retval      ALT_E_TRUE      Synchronization to clock is enabled for
+ *                              level-sensitive interrupts.
+ * \retval      ALT_E_FALSE     Synchronization to clock is disabled for
+ *                              level-sensitive interrupts.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Configures a group of GPIO signals with identical setup parameters. Allows
+ * for configuring all parameters of a given port at one time.
+ * 
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              The group of bits to apply this operation to. Other bits (mask
+ *              set to zero) are not changed.
+ * \param       dir
+ *              Data direction.
+ * \param       type
+ *              Edge-triggered or level-triggered interrupts.
+ * \param       pol
+ *              Active-high or active-low polarity.
+ * \param       debounc
+ *              Debounce signals or not.
+ * \param       data
+ *              Set the data output to this value.
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
+        uint32_t data);
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ *  @{
+ */
+/******************************************************************************/
+/*!
+ * Enables the specified GPIO data input interrupts.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              Individual bit interrupt enables \n
+ *              \b 0 - Interrupt disabled. \n
+ *              \b 1 - Interrupt enabled.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Disables the specified GPIO data module interrupt.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       config
+ *              Individual bit interrupt enables \n
+ *              \b 0 - Interrupt disabled. \n
+ *              \b 1 - Interrupt enabled.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ *  Returns the current state of the specified GPIO port interrupts enables.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ * \retval      uint32_t
+ *              The interrupt enable configuration that was read. Individual bits
+ *              are: \n \b 0 = The interrupt for this bit is not enabled. \n \b
+ *              1 = The interrupt for this bit is enabled.
+ */
+uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Masks or unmasks selected interrupt source bits of the data register of
+ * the specified GPIO module. Uses a second bit mask to determine which
+ * signals may be changed by this call.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       mask
+ *              Which bits to change among the port \n \b 0 = 
+ *              Do not change this bit. \n \b 1 = Allow this bit to change.
+ * \param       val
+ *              The interrupt mask to write. Individual bits are: \n \b 0 = 
+ *              Do not mask the interrupt for this bit (default). \n \b 1 = 
+ *              Mask the interrupt for this bit.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt mask of the specified GPIO module.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *                 
+ * \retval      uint32_t
+ *              The interrupt mask that was read. Individual bits are: \n 
+ *              \b 0 = The interrupt for this bit is not masked. \n \b 1 = The 
+ *              interrupt for this bit is masked.
+ *
+ */
+uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt pending status of all signals of the specified GPIO 
+ * register.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ 
+ * \retval      uint32_t
+ *              The current interrupt pending status. Individual bits are: \n 
+ *              \b 0 - The interrupt for this bit is not pending. \n \b 1 - 
+ *              The interrupt for this bit is pending.
+ *
+ */
+uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Clear the interrupt pending status of selected signals of the 
+ * specified GPIO register.
+ *
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ * \param       clrmask
+ *              The interrupt bits to clear. Individual bits are: \n \b 0 - 
+ *              The interrupt for this bit will not be changed. \n \b 1 - 
+ *              The interrupt for this bit will be cleared.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
+        uint32_t clrmask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * This functional group presents a perspective of the General-Purpose IO
+ * signals as individual GPIO and GPI bits spread across a number of signals
+ * across several GPIO ports. This allows the programmer the freedom to generally
+ * ignore the underlying port and signal structure of the GPIO hardware if
+ * desired.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits as one flat array spread
+ * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering
+ * must match the hardware bit-ordering.
+ *
+ */
+typedef enum ALT_GPIO_1BIT_e
+{
+    /*! # */
+    ALT_GPIO_1BIT_0,
+    /*! # */
+    ALT_GPIO_1BIT_1,
+    /*! # */
+    ALT_GPIO_1BIT_2,
+    /*! # */
+    ALT_GPIO_1BIT_3,
+    /*! # */
+    ALT_GPIO_1BIT_4,
+    /*! # */
+    ALT_GPIO_1BIT_5,
+    /*! # */
+    ALT_GPIO_1BIT_6,
+    /*! # */
+    ALT_GPIO_1BIT_7,
+    /*! # */
+    ALT_GPIO_1BIT_8,
+    /*! # */
+    ALT_GPIO_1BIT_9,
+    /*! # */
+    ALT_GPIO_1BIT_10,
+    /*! # */
+    ALT_GPIO_1BIT_11,
+    /*! # */
+    ALT_GPIO_1BIT_12,
+    /*! # */
+    ALT_GPIO_1BIT_13,
+    /*! # */
+    ALT_GPIO_1BIT_14,
+    /*! # */
+    ALT_GPIO_1BIT_15,
+    /*! # */
+    ALT_GPIO_1BIT_16,
+    /*! # */
+    ALT_GPIO_1BIT_17,
+    /*! # */
+    ALT_GPIO_1BIT_18,
+    /*! # */
+    ALT_GPIO_1BIT_19,
+    /*! # */
+    ALT_GPIO_1BIT_20,
+    /*! # */
+    ALT_GPIO_1BIT_21,
+    /*! # */
+    ALT_GPIO_1BIT_22,
+    /*! # */
+    ALT_GPIO_1BIT_23,
+    /*! # */
+    ALT_GPIO_1BIT_24,
+    /*! # */
+    ALT_GPIO_1BIT_25,
+    /*! # */
+    ALT_GPIO_1BIT_26,
+    /*! # */
+    ALT_GPIO_1BIT_27,
+    /*! # */
+    ALT_GPIO_1BIT_28,
+    /*! # */
+    ALT_GPIO_1BIT_29,
+    /*! # */
+    ALT_GPIO_1BIT_30,
+    /*! # */
+    ALT_GPIO_1BIT_31,
+    /*! # */
+    ALT_GPIO_1BIT_32,
+    /*! # */
+    ALT_GPIO_1BIT_33,
+    /*! # */
+    ALT_GPIO_1BIT_34,
+    /*! # */
+    ALT_GPIO_1BIT_35,
+    /*! # */
+    ALT_GPIO_1BIT_36,
+    /*! # */
+    ALT_GPIO_1BIT_37,
+    /*! # */
+    ALT_GPIO_1BIT_38,
+    /*! # */
+    ALT_GPIO_1BIT_39,
+    /*! # */
+    ALT_GPIO_1BIT_40,
+    /*! # */
+    ALT_GPIO_1BIT_41,
+    /*! # */
+    ALT_GPIO_1BIT_42,
+    /*! # */
+    ALT_GPIO_1BIT_43,
+    /*! # */
+    ALT_GPIO_1BIT_44,
+    /*! # */
+    ALT_GPIO_1BIT_45,
+    /*! # */
+    ALT_GPIO_1BIT_46,
+    /*! # */
+    ALT_GPIO_1BIT_47,
+    /*! # */
+    ALT_GPIO_1BIT_48,
+    /*! # */
+    ALT_GPIO_1BIT_49,
+    /*! # */
+    ALT_GPIO_1BIT_50,
+    /*! # */
+    ALT_GPIO_1BIT_51,
+    /*! # */
+    ALT_GPIO_1BIT_52,
+    /*! # */
+    ALT_GPIO_1BIT_53,
+    /*! # */
+    ALT_GPIO_1BIT_54,
+    /*! # */
+    ALT_GPIO_1BIT_55,
+    /*! # */
+    ALT_GPIO_1BIT_56,
+    /*! # */
+    ALT_GPIO_1BIT_57,
+    /*! # */
+    ALT_GPIO_1BIT_58,
+    /*! # */
+    ALT_GPIO_1BIT_59,
+    /*! # */
+    ALT_GPIO_1BIT_60,
+    /*! # */
+    ALT_GPIO_1BIT_61,
+    /*! # */
+    ALT_GPIO_1BIT_62,
+    /*! # */
+    ALT_GPIO_1BIT_63,
+    /*! # */
+    ALT_GPIO_1BIT_64,
+    /*! # */
+    ALT_GPIO_1BIT_65,
+    /*! # */
+    ALT_GPIO_1BIT_66,
+    /*! # */
+    ALT_GPIO_1BIT_67,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_GPIO_1BIT_68,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_GPIO_1BIT_69,        /* Not bonded out on some versions */
+
+    /*! The last of the input/output bits */
+    ALT_GPIO_1BIT_70,        /* Not bonded out on some versions */
+
+
+    /*! This and the following signals are not present on all SoCs. \n
+     * If present, the selection between their use as 14 General-purpose inputs or
+     * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift
+     * Register) and software to make this selection is in the IO Manager API. If
+     * they are present, they are restricted to using the same power supply voltage
+     * as the SDRAM module.*/
+    ALT_HLGPI_0,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_1,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_2,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_3,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_4,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_5,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_6,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_7,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_8,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_9,        /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_10,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_11,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_12,       /* Not bonded out on some versions */
+    /*! # */
+    ALT_HLGPI_13,       /* Not bonded out on some versions */
+
+    ALT_HLGPI_14,       /* Not bonded out */
+
+    ALT_HLGPI_15,       /* Not bonded out */
+
+    ALT_GPIO_INVALID,
+    ALT_END_OF_GPIO_SIGNALS = -1,
+    ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15
+} ALT_GPIO_1BIT_t;
+
+
+/******************************************************************************/
+/*!
+ * This configuration record definition is used for configuring bits and
+ * groups of bits of the GPIO interface.
+ */
+typedef struct ALT_GPIO_CONFIG_RECORD_s
+{
+    /*!
+     * The index number of the signal to configure. */
+    ALT_GPIO_1BIT_t             signal_number;
+    /*!
+     * The data direction of the signal. */
+    ALT_GPIO_PIN_DIR_t          direction;
+    /*!
+     * Edge-triggered or level triggered interrupts. */
+    ALT_GPIO_PIN_TYPE_t         type;
+    /*!
+     * Active-high or active-low trigger for the interrupt. */
+    ALT_GPIO_PIN_POL_t          polarity;
+    /*!
+     * Enable or disable GPIO debounce capability. */
+    ALT_GPIO_PIN_DEBOUNCE_t     debounce;
+    /*!
+     * If the signal is an output, the data value to be output. */
+    ALT_GPIO_PIN_DATA_t         data;
+} ALT_GPIO_CONFIG_RECORD_t;
+
+/******************************************************************************/
+/*!
+ * This pin record type definition is comprised of the signal index and
+ * associated input or output data.
+ */
+typedef struct ALT_GPIO_PIN_RECORD_s
+{
+    /*!
+     * The index number of the signal. */
+    ALT_GPIO_1BIT_t         signal_number;
+    /*!
+     * Data - zero or one. */
+    ALT_GPIO_PIN_DATA_t     val;
+} ALT_GPIO_PIN_RECORD_t;
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Configures all parameters for one bit (signal) of the GPIO ports.
+ * 
+ * \param       signal_num
+ *              The GPIO port signal index.
+ * \param       dir
+ *              The data direction for this signal.
+ * \param       type
+ *              Edge-triggered or Level-triggered interrupt for this signal.
+ * \param       pol
+ *              Active-high or active-low interrupt polarity for this signal.
+ * \param       debounce
+ *              Enable the debounce flip-flops for this signal or not.
+ * \param       data
+ *              If the GPIO signal is set to be an output, set it to
+ *              this value
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
+        ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
+        ALT_GPIO_PIN_DATA_t data);
+
+/******************************************************************************/
+/*!
+ * Returns the configuration parameters of a given GPIO bit.
+ * 
+ * \param       signal_num
+ *              The GPIO port signal index.
+ * \param       config
+ *              Pointer to a single GPIO_CONFIG_RECORD_s configuration record.
+ *              The fields of this configuration record are filled in
+ *              by the function.         
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
+        ALT_GPIO_CONFIG_RECORD_t *config);
+
+/******************************************************************************/
+/*!
+ * Configures a list of GPIO bits. The GPIO bits do not have to be 
+ * configured the same, as was the case for the mask version of this function, 
+ * alt_gpio_port_config(). Each bit may be configured differently and bits may
+ * be listed in any order.
+ * 
+ * \param       config_array
+ *              Pointer to an array of GPIO_CONFIG_RECORD_s configuration
+ *              records. These definitions contain all the parameters
+ *              needed to set up the listed pins. All or 
+ *              any subset of the GPIO signals can be configured. Signals do 
+ *              not have to be listed in numerical order or be unique. If a 
+ *              signal number is listed multiple times, the last configuration 
+ *              listed is used. \n Configuration terminates either when \b len
+ *              signals have been configured or if the next signal number index
+ *              in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ *              
+ * \param       len
+ *              Length of array to configure. 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array,
+        uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration 
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals.
+ *  
+ * \param       config_array
+ *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ *              records. Only the signal indices in the first field of each
+ *              configuration record need be filled in. This function will
+ *              fill in all the other fields of the configuration record,
+ *              returning all configuration parameters in the array.
+ *              Signals do not have to be listed in numerical order or be 
+ *              unique. If a signal number is listed multiple times, the 
+ *              configuration record will contain multiple entries for
+ *              that signal. \n Configuration reading terminates either when
+ *              \b len signal configurations have been read or if the next
+ *              signal number index in the array is equal to
+ *              \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param       len
+ *              Length of configuration array to read and return. 
+ *                 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+        
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
+        uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals. The difference between this version and
+ * alt_gpio_group_config_get() is this version follows a separate list of
+ * signal indices instead of having the signal list provided in the first
+ * field of the configuration records in the array.
+ *                
+ * \param       pinid_array
+ *              Pointer to a list of signal index numbers. These indices
+ *              are copied to the first field of each configuration record
+ *              in the returned array.
+ * \param       config_array
+ *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ *              records. This function will fill in the fields of the 
+ *              configuration record, returning all configuration parameters 
+ *              in the array. Signals do not have to be listed in numerical 
+ *              order or be unique. If a signal number is listed multiple 
+ *              times, the configuration record array will contain multiple 
+ *              identical entries for that signal. \n Configuration reading
+ *              terminates either when \b len signal configurations have been
+ *              read or if the next signal number index in the array is equal
+ *              to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param       len
+ *              Length of configuration array to read. 
+ *                 
+ *                 
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ *         
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
+        ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions
+ *
+ * These are useful utility functions for the general-purpose input & output
+ * module.
+ *
+ * @{ */
+/******************************************************************************/
+/*!
+ * Returns the ID code of the specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ *
+ * \retval      uint32_t    The component code of the module, GPIO_MODULE_IDCODE.
+ */
+uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the version code of the specified GPIO module.
+ *
+ * \param       gpio_pid
+ *              The GPIO port identifier.
+ *
+ *
+ * \retval      uint32_t      The encoded revision number of the module.
+ */
+uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO port ID from the supplied GPIO Signal Index Number.
+ */
+ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index
+ * Number.
+ *  */
+ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num);
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and 
+ * signal mask. If passed a bitmask composed of more than one signal, the 
+ * signal number of the lowest bit in the bitmask presented is returned.
+ * 
+ */
+ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
+        uint32_t bitmask);
+
+
+/*! @} */
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_GPIO_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_globaltmr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_globaltmr.h
new file mode 100644
index 0000000..235cca2
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_globaltmr.h
@@ -0,0 +1,458 @@
+/*! \file
+ *  Altera - Module Description
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_GBLTMR_H__
+#define __ALT_GBLTMR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************/
+/*! \addtogroup GBLTMR_MGR The Global Timer Manager API
+ *
+ * This functional group handles setting and reading various parameters of the 
+ * global 64-bit incrementing counter. There is one 64-bit continuously 
+ * incrementing counter for all CPU cores and it is clocked by PERIPHCLK. 
+ * This section manages the comparator value, compare enable, 
+ * auto-increment value, auto-increment enable, and interrupt enable for the 
+ * CPU that this code is running on (referenced as \b CPU_GLOBAL_TMR).
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Stops the global timer counter compare function for this CPU and disables 
+ * its interrupt. It does
+ * not stop the global timer itself. This function is identical to calling 
+ * \b alt_gpt_tmr_stop() with a tmr_id of \b CPU_GLOBAL_TMR.
+ * 
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_globaltmr_stop(void);
+
+/******************************************************************************/
+/*!
+ * Starts the global timer compare function for this CPU, enables its interrupt 
+ * function and, if free-running mode is selected also enables its 
+ * auto-increment function. If the global timer is not yet running, it starts 
+ * the timer. This function is identical to calling \b alt_gpt_tmr_start() 
+ * with a tmr_id of \b CPU_GLOBAL_TMR.
+ * 
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_globaltmr_start(void);
+
+/******************************************************************************/
+/*!
+ * Returns the current counter value of the 64-bit global timer. 
+ * 
+ * 
+ * \param       highword
+ *              Location used to return the most significant 32-bit word of 
+ *              the current global timer count.
+ * \param       lowword
+ *              Location used to return the least significant 32-bit word 
+ *              of the current global timer count.
+ *
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_get(uint32_t* highword, uint32_t* lowword);
+
+/******************************************************************************/
+/*!
+ * Returns the current counter value of the 64-bit global timer. This function
+ * is identical to alt_globaltmr_get() except that the value is returned as a
+ * 64-bit unsigned integer rather than as two 32-bit words.
+ * 
+ * 
+ *
+ * \retval      uint64_t
+ *              The current value of the 64-bit counter.
+ */
+uint64_t alt_globaltmr_get64(void);
+
+/******************************************************************************/
+/*!
+ * Returns the 32 low-order bits of the global timer. This
+ * is identical to calling \b alt_gpt_counter_get() with a tmr_id equal 
+ * to \b CPU_GLOBAL_TMR. Use alt_globaltmr_get()  or alt_globaltmr_get64() to
+ * obtain the full 64-bit timer value.
+ *
+ *
+ *
+ * \retval      uint32_t The current 32-bit counter value. 
+ */
+uint32_t alt_globaltmr_counter_get_low32(void);
+
+/******************************************************************************/
+/*!
+ * Returns the 32 higher-order bits of the global timer. Use alt_globaltmr_get()
+ * or alt_globaltmr_get64() to obtain the full 64-bit timer value.
+ *
+ *
+ *
+ * \retval      uint32_t The current 32-bit counter value. 
+ */
+uint32_t alt_globaltmr_counter_get_hi32(void);
+
+/******************************************************************************/
+/*!
+ * Sets the value of the 64-bit global timer comparator for this CPU. The 
+ * global timer increments its count and when it reaches this value or above, 
+ * it triggers the following actions. If the interrupt is enabled, it forwards 
+ * an interrupt request to the core. If free-run mode is selected, it adds the
+ * auto-increment value to the value of the global counter and the resulting 
+ * sum is saved as the new comparator value.
+ *
+ * 
+ * \param       highword
+ *              The 32 MSBits of the new comparator value.
+ * \param       loword
+ *              The 32 LSBits of the new comparator value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_comp_set(uint32_t highword, uint32_t loword);
+
+/******************************************************************************/
+/*!
+ * Sets the value of the 64-bit global timer comparator for this CPU. The 
+ * global timer increments its count and when it reaches this value or above, 
+ * it triggers the following actions. If the interrupt is enabled, it forwards 
+ * an interrupt request to the core. If free-run mode is selected, it adds the
+ * auto-increment value to the value of the global counter and the resulting 
+ * sum is saved as the new comparator value.
+ *
+ * 
+ * \param       compval
+ *              The new comparator value to set.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_comp_set64(uint64_t compval);
+
+/******************************************************************************/
+/*!
+ * Returns the current 64-bit global timer comparator value  for this CPU. The 
+ * global timer increments its count and when it reaches this value or above, 
+ * it triggers the following actions. If the interrupt is enabled, it forwards 
+ * an interrupt request to the core. If free-run mode is selected, it adds the
+ * auto-increment value to the value of the global counter and the resulting 
+ * sum is saved as the new comparator value. This value will increase by the 
+ * auto-increment value each time the global timer reaches the comparator 
+ * value.
+ *
+ * 
+ * \param       highword
+ *              Pointer to location to store the 32 MSBits of the comparator value.
+ * \param       lowword
+ *              Pointer to location to store the 32 LSBits of the comparator value.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_comp_get(uint32_t *highword, uint32_t *lowword);
+
+/******************************************************************************/
+/*!
+ * Returns the current 64-bit global timer comparator value  for this CPU. The 
+ * global timer increments its count and when it reaches this value or above, 
+ * it triggers the following actions. If the interrupt is enabled, it forwards 
+ * an interrupt request to the core. If free-run mode is selected, it adds the
+ * auto-increment value to the value of the global counter and the resulting 
+ * sum is saved as the new comparator value. This value will increase by the 
+ * auto-increment value each time the global timer reaches the comparator 
+ * value. This function is identical to alt_globaltmr_comp_get() except that the
+ * value is returned in a 64-bit unsigned integer rather than as two 32-bit 
+ * words.
+ * 
+ *
+ * \retval      uint64_t
+ *              The 64-bit value of the global timer comparator.
+ */
+uint64_t alt_globaltmr_comp_get64(void);
+
+/******************************************************************************/
+/*!
+ * Enables the comparison function of the global timer for this CPU.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_comp_mode_start(void);
+
+/******************************************************************************/
+/*!
+ * Disables the comparison function of the global timer for this CPU.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_comp_mode_stop(void);
+
+/******************************************************************************/
+/*!
+ * Returns the comparison mode selection of the global 
+ * timer for this CPU.
+ * 
+ *
+ * \retval      FALSE           Comparison mode is not enabled.
+ * \retval      TRUE            Comparison mode is enabled.
+ */
+bool alt_globaltmr_is_comp_mode(void);
+
+
+/******************************************************************************/
+/*!
+ * Returns the clock prescaler value of the global timer.
+ *
+ *
+ * \retval      uint32_t    The prescaler value. Valid range is 0-255.
+ *                          Actual clock divisor ratio is this number plus one.
+ */
+uint32_t alt_globaltmr_prescaler_get(void);
+
+
+/******************************************************************************/
+/*!
+ * Sets the clock prescaler value of the global timer.
+ *
+ *
+ * \param       val
+ *              The 8-bit prescaler value to load. Valid range is 0-255.
+ *              Actual clock divisor ratio is this number plus one.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_prescaler_set(uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Sets a 32-bit global timer auto-increment value in the global
+ * timer block for this CPU. The global timer continually increments its count 
+ * and when it reaches the value set in the comparator register or above, if 
+ * both comparison and free-run modes are selected, it adds the value set by this 
+ * function to the comparator value and saves it as the new comparator value. 
+ * This count then sets the time delay until the next global timer compare 
+ * value is reached.
+ *
+ * 
+ * \param       inc
+ *              Auto-increment value to set.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_autoinc_set(uint32_t inc);
+
+/******************************************************************************/
+/*!
+ * Returns the global timer auto-increment value for this CPU. When the global 
+ * timer reaches the comparator value, if both comparison and free-run modes 
+ * are selected this value is added to the previous comparator value and saved 
+ * as the new comparator value.
+ *
+ *
+ * \retval      uint32_t
+ *              The current comparator auto-increment value.
+ */
+uint32_t alt_globaltmr_autoinc_get(void);
+
+/******************************************************************************/
+/*!
+ * Enables the auto-increment function of the global timer for this CPU.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_autoinc_mode_start(void);
+
+/******************************************************************************/
+/*!
+ * Disables the auto-increment function of the global timer for this CPU.
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_autoinc_mode_stop(void);
+
+/******************************************************************************/
+/*!
+ * Returns the auto-increment selection of the global timer for this CPU.
+ * 
+ *
+ * \retval      FALSE           Auto-increment mode is not enabled.
+ * \retval      TRUE            Auto-increment mode is enabled.
+ */
+bool alt_globaltmr_is_autoinc_mode(void);
+
+/******************************************************************************/
+/*!
+ * Returns the maximum counter value available for \b CPU_GLOBAL_TMR. \n
+ * The value returned does not factor in the value of the clock prescaler.
+ *
+ *
+ *
+ *
+ * \retval      uint32_t    The maximum counter value available for this timer.
+ * \retval      0           An error occurred.
+ *
+ */
+uint32_t alt_globaltmr_maxcounter_get(void);
+
+/******************************************************************************/
+/*!
+ * Disables the interrupt from the global timer module. Identical to calling
+ * alt_gpt_int_disable() with tmr_id of \b CPU_GLOBAL_TMR.
+ *
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_int_disable(void);
+
+/******************************************************************************/
+
+/*!
+ *
+ * Enables the interrupt of the global timer
+ * module. Identical to calling alt_gpt_int_enable() with tmr_id of
+ * \b CPU_GLOBAL_TMR. If global timer is not already running, this function
+ * attempts to start it.
+ * 
+ * 
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_globaltmr_int_enable(void);
+
+/******************************************************************************/
+/*!
+ * Return \b TRUE if the interrupt of the global timer module is enabled 
+ * and \b FALSE if the interrupt is disabled or masked. Identical to calling 
+ * alt_gpt_int_is_enabled() with tmr_id of 
+ * \b CPU_GLOBAL_TMR.
+ *
+ * \internal - note that there's more to this than just enabling the
+ * interrupt and clearing the status.
+ * \endinternal
+ * 
+ *
+ * \retval      TRUE            The timer interrupt is currently enabled.
+ * \retval      FALSE           The timer interrupt is currently disabled.
+ */
+bool alt_globaltmr_int_is_enabled(void);
+
+/******************************************************************************/
+/*!
+ * Clear the pending interrupt status of the global timer module. Identical to 
+ * calling alt_gpt_int_clear_pending() with tmr_id of 
+ * \b CPU_GLOBAL_TMR.
+ *
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_globaltmr_int_clear_pending(void);
+
+/******************************************************************************/
+/*!
+ * Read the state (pending or not) of the interrupt of the global timer 
+ * module without changing the interrupt state. Identical to 
+ * calling alt_gpt_int_is_pending() with tmr_id of 
+ * \b CPU_GLOBAL_TMR.
+ *
+ *
+ *
+ * \retval      TRUE            The timer interrupt is currently pending.
+ * \retval      FALSE           The timer interrupt is not currently pending.
+ */
+bool alt_globaltmr_int_is_pending(void);
+
+/******************************************************************************/
+/*!
+ * Read the state of the interrupt of the global timer 
+ * module and if the interrupt is set, clear it. Identical to 
+ * calling alt_gpt_int_is_pending_and_clear()  with tmr_id of 
+ * \b CPU_GLOBAL_TMR.
+ *
+ *
+ *
+ * \retval      TRUE            The timer interrupt was pending.
+ * \retval      FALSE           The timer interrupt was not pending.
+ */
+bool alt_globaltmr_int_if_pending_clear(void);
+
+/*! @} */
+/*! @} */
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_GBLTMR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h
new file mode 100644
index 0000000..57f0f0d
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_HWLIBS_VER_H__
+
+/***********************************************************************
+ *
+ * Set of macros to provide version information
+ *
+ ***********************************************************************/
+
+/* This is the major revision of the Altera ACDS Release    */
+#define ALTERA_ACDS_MAJOR_REV           13
+
+/* This is the minor revision of the Altera ACDS Release    */
+#define ALTERA_ACDS_MINOR_REV            0
+
+/* This is an internal HwLibs revision control code.        */
+/* End-users should NOT depend upon the value of this field */
+#define ALTERA_HWLIBS_REV                0
+
+/* This is a text string containing the current release and service pack IDs */
+#define ALTERA_ACDS_REV_STR             "13.0SP1"
+
+#endif   /* __ALT_HWLIBS_VER_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h
new file mode 100644
index 0000000..db1e6dd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_INT_COMMON_H__
+#define __ALT_INT_COMMON_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup INT_COMMON Interrupt Controller Common Definitions
+ *
+ * This module contains the definitions common to the Interrupt Controller
+ * Low-Level API and Interrupt Controller Manager Interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates all the interrupt identification types.
+ */
+typedef enum ALT_INT_INTERRUPT_e
+{
+    ALT_INT_INTERRUPT_SGI0  =  0, /*!< # */
+    ALT_INT_INTERRUPT_SGI1  =  1, /*!< # */
+    ALT_INT_INTERRUPT_SGI2  =  2, /*!< # */
+    ALT_INT_INTERRUPT_SGI3  =  3, /*!< # */
+    ALT_INT_INTERRUPT_SGI4  =  4, /*!< # */
+    ALT_INT_INTERRUPT_SGI5  =  5, /*!< # */
+    ALT_INT_INTERRUPT_SGI6  =  6, /*!< # */
+    ALT_INT_INTERRUPT_SGI7  =  7, /*!< # */
+    ALT_INT_INTERRUPT_SGI8  =  8, /*!< # */
+    ALT_INT_INTERRUPT_SGI9  =  9, /*!< # */
+    ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
+    ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
+    ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
+    ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
+    ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
+    ALT_INT_INTERRUPT_SGI15 = 15,
+    /*!<
+     * Software Generated Interrupts (SGI), 0 - 15.
+     *  * All interrupts in this group are software triggered.
+     */
+
+    ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL   = 27, /*!< # */
+    ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE  = 29, /*!< # */
+    ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
+    /*!<
+     * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
+     * private timer, and watchdog timer.
+     *  * All interrupts in this group are edge triggered.
+     */
+
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL         = 32, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC    = 33, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB     = 34, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG   = 35, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA  = 36, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB     = 37, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG   = 39, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA  = 40, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS0           = 41, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS1           = 42, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS2           = 43, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS3           = 44, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS4           = 45, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS5           = 46, /*!< # */
+    ALT_INT_INTERRUPT_CPU0_DEFLAGS6           = 47,
+    /*!<
+     * Interrupts sourced from CPU0.
+     *
+     * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
+     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+     * for CPU0.
+     *
+     *  * PARITYFAIL interrupts in this group are edge triggered.
+     *  * DEFFLAGS interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL         = 48, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC    = 49, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB     = 50, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG   = 51, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA  = 52, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB     = 53, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG   = 55, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA  = 56, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS0           = 57, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS1           = 58, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS2           = 59, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS3           = 60, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS4           = 61, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS5           = 62, /*!< # */
+    ALT_INT_INTERRUPT_CPU1_DEFLAGS6           = 63,
+    /*!<
+     * Interrupts sourced from CPU1.
+     *
+     * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
+     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+     * for CPU1.
+     *
+     *  * PARITYFAIL interrupts in this group are edge triggered.
+     *  * DEFFLAGS interrupts in this group are level triggered.
+     */
+    
+    ALT_INT_INTERRUPT_SCU_PARITYFAIL0 =  64, /*!< # */
+    ALT_INT_INTERRUPT_SCU_PARITYFAIL1 =  65, /*!< # */
+    ALT_INT_INTERRUPT_SCU_EV_ABORT    =  66,
+    /*!<
+     * Interrupts sourced from the Snoop Control Unit (SCU).
+     *  * All interrupts in this group are edge triggered.
+     */
+    
+    ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ     = 67, /*!< # */
+    ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ   = 68, /*!< # */
+    ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
+    ALT_INT_INTERRUPT_L2_COMBINED_IRQ        = 70,
+    /*!<
+     * Interrupts sourced from the L2 Cache Controller.
+     *
+     * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
+     * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
+     * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
+     * Consult the L2C documentation for information on these interrupts.
+     *
+     *  * ECC interrupts in this group are edge triggered.
+     *  * Other interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ =  71,
+    /*!<
+     * Interrupts sourced from the SDRAM Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ0  =  72, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ1  =  73, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ2  =  74, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ3  =  75, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ4  =  76, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ5  =  77, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ6  =  78, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ7  =  79, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ8  =  80, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ9  =  81, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 =  82, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 =  83, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 =  84, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 =  85, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 =  86, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 =  87, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 =  88, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 =  89, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 =  90, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 =  91, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 =  92, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 =  93, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 =  94, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 =  95, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 =  96, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 =  97, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 =  98, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 =  99, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
+    ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
+    /*!<
+     * Interrupt request from the FPGA logic, 0 - 63.
+     *  * Trigger type depends on the implementation in the FPGA.
+     */
+
+    ALT_INT_INTERRUPT_DMA_IRQ0                = 136, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ1                = 137, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ2                = 138, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ3                = 139, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ4                = 140, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ5                = 141, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ6                = 142, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ7                = 143, /*!< # */
+    ALT_INT_INTERRUPT_DMA_IRQ_ABORT           = 144, /*!< # */
+    ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ   = 145, /*!< # */
+    ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
+    /*!<
+     * Interrupts sourced from the DMA Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_EMAC0_IRQ                    = 147, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ   = 148, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ   = 150, /*!< # */
+    ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
+    /*!<
+     * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_EMAC1_IRQ                    = 152, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ   = 153, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ   = 155, /*!< # */
+    ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
+    /*!<
+     * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_USB0_IRQ             = 157, /*!< # */
+    ALT_INT_INTERRUPT_USB0_ECC_CORRECTED   = 158, /*!< # */
+    ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
+    /*!<
+     * Interrupts sourced from the USB OTG 0.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_USB1_IRQ             = 160, /*!< # */
+    ALT_INT_INTERRUPT_USB1_ECC_CORRECTED   = 161, /*!< # */
+    ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
+    /*!<
+     * Interrupts sourced from the USB OTG 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CAN0_STS_IRQ             = 163, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_MO_IRQ              = 164, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ   = 165, /*!< # */
+    ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
+    /*!<
+     * Interrupts sourced from the CAN Controller 0.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CAN1_STS_IRQ             = 167, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_MO_IRQ              = 168, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ   = 169, /*!< # */
+    ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
+    /*!<
+     * Interrupts sourced from the CAN Controller 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_SDMMC_IRQ                   = 171, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED   = 172, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED   = 174, /*!< # */
+    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
+    /*!<
+     * Interrupts sourced from the SDMMC Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_NAND_IRQ                  = 176, /*!< # */
+    ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ   = 177, /*!< # */
+    ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
+    ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ   = 179, /*!< # */
+    ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
+    ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ   = 181, /*!< # */
+    ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
+    /*!<
+     * Interrupts sourced from the NAND Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_QSPI_IRQ                 = 183, /*!< # */
+    ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ   = 184, /*!< # */
+    ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
+    /*!<
+     * Interrupts sourced from the QSPI Controller.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
+    ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
+    ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
+    ALT_INT_INTERRUPT_SPI3_IRQ = 189,
+    /*!<
+     * Interrupts sourced from the SPI Controllers 0 - 3.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
+    ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
+    ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
+    ALT_INT_INTERRUPT_I2C3_IRQ = 193,
+    /*!<
+     * Interrupts sourced from the I2C Controllers 0 - 3.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
+    ALT_INT_INTERRUPT_UART1 = 195,
+    /*!<
+     * Interrupts sourced from the UARTs 0 - 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
+    ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
+    ALT_INT_INTERRUPT_GPIO2 = 198,
+    /*!<
+     * Interrupts sourced from the GPIO 0 - 2.
+     *  * All interrupts in this group are level triggered.
+     */
+    
+    ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
+    ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
+    /*!<
+     * Interrupts sourced from the Timer controllers.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
+    ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
+    /*!<
+     * Interrupts sourced from the Watchdog Timers 0 - 1.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
+    /*!<
+     * Interrupts sourced from the Clock Manager.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
+    /*!<
+     * Interrupts sourced from the Clock Manager MPU Wakeup.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
+    /*!<
+     * Interrupts sourced from the FPGA Manager.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
+    ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
+    /*!<
+     * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
+     *  * All interrupts in this group are level triggered.
+     */
+
+    ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ   = 210, /*!< # */
+    ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
+    /*!<
+     * Interrupts sourced from the On-chip RAM.
+     *  * All interrupts in this group are level triggered.
+     */
+
+} ALT_INT_INTERRUPT_t;
+
+/*!
+ * This is the CPU target type. It is used to specify a set of CPUs on the
+ * system. If only bit 0 is set then it specifies a set of CPUs containing
+ * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
+ * up to the number of CPUs on the system.
+ */
+typedef uint32_t alt_int_cpu_target_t;
+
+/*!
+ * This type definition enumerates all the interrupt trigger types.
+ */
+typedef enum ALT_INT_TRIGGER_e
+{
+    /*!
+     * Edge triggered interrupt. This applies to Private Peripheral Interrupts
+     * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
+     * 16 - 1019.
+     */
+    ALT_INT_TRIGGER_EDGE,
+
+    /*!
+     * Level triggered interrupt. This applies to Private Peripheral
+     * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
+     * interrupt IDs 16 - 1019.
+     */
+    ALT_INT_TRIGGER_LEVEL,
+
+    /*!
+     * Software triggered interrupt. This applies to Software Generated
+     * Interrupts (SGI) only, with interrupt IDs 0 - 15.
+     */
+    ALT_INT_TRIGGER_SOFTWARE,
+
+    /*!
+     * All triggering types except for those in the Shared Peripheral Interrupts
+     * (SPI) F2S FPGA family interrupts can be determined by the system
+     * automatically. In all functions which ask for the triggering type, the
+     * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
+     * type for all non F2S interrupt types.
+     */
+    ALT_INT_TRIGGER_AUTODETECT,
+
+    /*!
+     * The interrupt triggering information is not applicable. This is possibly
+     * due to querying an invalid interrupt identifier.
+     */
+    ALT_INT_TRIGGER_NA
+}
+ALT_INT_TRIGGER_t;
+
+/*!
+ * This type definition enumerates all the target list filter options. This is
+ * used by the trigger Software Generated Interrupt (SGI) feature to issue a
+ * SGI to the specified processor(s) in the system. Depending on the target
+ * list filter and the target list, interrupts can be routed to any
+ * combinations of CPUs.
+ */
+typedef enum ALT_INT_SGI_TARGET_e
+{
+    /*!
+     * This filter list uses the target list parameter to specify which CPUs
+     * to send the interrupt to. If target list is 0, no interrupts are sent.
+     */
+    ALT_INT_SGI_TARGET_LIST,
+
+    /*!
+     * This filter list sends the interrupt all CPUs except the current CPU.
+     * The target list parameter is ignored.
+     */
+    ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
+
+    /*!
+     * This filter list sends the interrupt to the current CPU only. The
+     * target list parameter is ignored.
+     */
+    ALT_INT_SGI_TARGET_SENDER_ONLY
+}
+ALT_INT_SGI_TARGET_t;
+
+/*!
+ * Extracts the CPUID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_CPUID_GET(icciar)    ((icciar >> 10) & 0x7)
+
+/*!
+ * Extracts the ACKINTID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
+
+/*!
+ * The callback to use when an interrupt needs to be serviced.
+ *
+ * \param       icciar          The Interrupt Controller CPU Interrupt
+ *                              Acknowledgement Register value (ICCIAR) value
+ *                              corresponding to the current interrupt.
+ *
+ * \param       context         The user provided context.
+ */
+typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_INT_COMMON_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h
new file mode 100644
index 0000000..2ead15d
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h
@@ -0,0 +1,156 @@
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_MPUSCU_H__
+#define __ALT_MPUSCU_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/************************************************************************************************************/
+/*                                alt_mpuscu.h                                                                 */
+/*                                                                                                            */
+/*  Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog         */
+/*  Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor.    */
+/*                                                                                                            */
+/************************************************************************************************************/
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR 0x00
+#endif
+
+
+/*     ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h            */
+/*    and is the address of the base of the Snoop Control Unit (SCU)                                */
+#define GLOBALTMR_BASE                      (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
+#define CPU_WDTGPT_TMR_BASE                 (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
+#define CPU_PRIVATE_TMR_BASE                (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
+#define CPU_INT_CTRL_BASE                   (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
+#define CPU_INT_DIST_BASE                   (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
+
+
+            /* offsets */
+        /* Global Timer offsets */
+#define GLOBALTMR_MODULE_BASE_OFFSET        0x00000200
+#define GLOBALTMR_CNTR_LO_REG_OFFSET        0x00000000
+#define GLOBALTMR_CNTR_HI_REG_OFFSET        0x00000004
+#define GLOBALTMR_CTRL_REG_OFFSET           0x00000008
+#define GLOBALTMR_INT_STAT_REG_OFFSET       0x0000000C
+#define GLOBALTMR_COMP_LO_REG_OFFSET        0x00000010
+#define GLOBALTMR_COMP_HI_REG_OFFSET        0x00000014
+#define GLOBALTMR_AUTOINC_REG_OFFSET        0x00000018
+
+/* Global Timer bitmasks */
+#define GLOBALTMR_ENABLE_BIT                0x00000001
+#define GLOBALTMR_COMP_ENABLE_BIT           0x00000002
+#define GLOBALTMR_INT_ENABLE_BIT            0x00000004
+#define GLOBALTMR_AUTOINC_ENABLE_BIT        0x00000008
+#define GLOBALTMR_PS_MASK                   0x0000FF00
+#define GLOBALTMR_PS_SHIFT                  8
+#define GLOBALTMR_INT_STATUS_BIT            0x00000001
+
+/* Global timer constants */
+#define GLOBALTMR_MAX                       0xFFFFFFFF
+#define GLOBALTMR_PS_MAX                    0x000000FF
+
+
+/* Private timer offsets */
+#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET   0x00000600
+#define CPU_PRIV_TMR_LOAD_REG_OFFSET        0x00000000
+#define CPU_PRIV_TMR_CNTR_REG_OFFSET        0x00000004
+#define CPU_PRIV_TMR_CTRL_REG_OFFSET        0x00000008
+#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET  0x0000000C
+
+/* Private timer bitmasks */
+#define CPU_PRIV_TMR_ENABLE                 0x00000001
+#define CPU_PRIV_TMR_AUTO_RELOAD            0x00000002
+#define CPU_PRIV_TMR_INT_EN                 0x00000004
+#define CPU_PRIV_TMR_PS_MASK                0x0000FF00
+#define CPU_PRIV_TMR_PS_SHIFT               8
+#define CPU_PRIV_TMR_INT_STATUS             0x00000001
+
+/* Private timer constants */
+#define CPU_PRIV_TMR_MAX                    0xFFFFFFFF
+#define CPU_PRIV_TMR_PS_MAX                 0x000000FF
+
+
+
+    /* Watchdog timer offsets */
+#define WDOG_TIMER_MODULE_BASE_OFFSET       0x00000620
+#define WDOG_LOAD_REG_OFFSET                0x00000000
+#define WDOG_CNTR_REG_OFFSET                0x00000004
+#define WDOG_CTRL_REG_OFFSET                0x00000008
+#define WDOG_INTSTAT_REG_OFFSET             0x0000000C
+#define WDOG_RSTSTAT_REG_OFFSET             0x00000010
+#define WDOG_DISABLE_REG_OFFSET             0x00000014
+
+    /* Watchdog timer bitmasks : */
+    /* Control Register bitmasks */
+#define WDOG_TMR_ENABLE                     0x00000001
+#define WDOG_AUTO_RELOAD                    0x00000002
+#define WDOG_INT_EN                         0x00000004
+#define WDOG_WDT_MODE                       0x00000008
+#define WDOG_PS_MASK                        0x0000FF00
+#define WDOG_PS_SHIFT                       8
+    /* Interrupt Status Register bitmasks */
+#define WDOG_INT_STAT_BIT                   0x00000001
+    /* Reset Status Register bitmasks */
+#define WDOG_RST_STAT_BIT                   0x00000001
+
+    /* Watchdog timer constants */
+#define WDOG_TMR_MAX                        UINT32_MAX
+#define WDOG_PS_MAX                         UINT8_MAX
+#define WDOG_DISABLE_VAL0                   0x12345678
+#define WDOG_DISABLE_VAL1                   0x87654321
+
+
+
+    /* Interrupt Manager offsets */
+/*   <Add definitions here> */
+#define INT_CONTROLLER_MODULE_BASE_OFFSET   0x00000100
+#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET  0x00001000
+#define INT_DIST_TYPE_REG                   0x00000004
+
+
+/*  Upper bound of the MPUSCU address space  */
+#define MPUSCU_MAX                          0x00001FFF
+
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* __ALT_MPUSCU_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h
new file mode 100644
index 0000000..7b0da34
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h
@@ -0,0 +1,249 @@
+/*! \file
+ *  Altera - SoC Reset Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_RESET_MGR_H__
+#define __ALT_RESET_MGR_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*! \addtogroup RST_MGR The Reset Manager
+ *
+ * The Reset Manager API defines functions for accessing, configuring, and
+ * controlling the HPS reset behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_STATUS Reset Status
+ *
+ * This functional group provides information on various aspects of SoC reset
+ * status and timeout events.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the set of reset causes and timeout events as
+ * register mask values.
+ */
+typedef enum ALT_RESET_EVENT_e
+{
+    /*! Power-On Voltage Detector Cold Reset */
+    ALT_RESET_EVENT_PORVOLTRST          = 0x00000001,
+
+    /*! nPOR Pin Cold Reset                  */
+    ALT_RESET_EVENT_NPORPINRST          = 0x00000002,
+
+    /*! FPGA Core Cold Reset                 */
+    ALT_RESET_EVENT_FPGACOLDRST         = 0x00000004,
+
+    /*! CONFIG_IO Cold Reset                 */
+    ALT_RESET_EVENT_CONFIGIOCOLDRST     = 0x00000008,
+
+    /*! Software Cold Reset                  */
+    ALT_RESET_EVENT_SWCOLDRST           = 0x00000010,
+
+    /*! nRST Pin Warm Reset                  */
+    ALT_RESET_EVENT_NRSTPINRST          = 0x00000100,
+
+    /*! FPGA Core Warm Reset                 */
+    ALT_RESET_EVENT_FPGAWARMRST         = 0x00000200,
+
+    /*! Software Warm Reset                  */
+    ALT_RESET_EVENT_SWWARMRST           = 0x00000400,
+
+    /*! MPU Watchdog 0 Warm Reset            */
+    ALT_RESET_EVENT_MPUWD0RST           = 0x00001000,
+
+    /*! MPU Watchdog 1 Warm Reset            */
+    ALT_RESET_EVENT_MPUWD1RST           = 0x00002000,
+
+    /*! L4 Watchdog 0 Warm Reset             */
+    ALT_RESET_EVENT_L4WD0RST            = 0x00004000,
+
+    /*! L4 Watchdog 1 Warm Reset             */
+    ALT_RESET_EVENT_L4WD1RST            = 0x00008000,
+
+    /*! FPGA Core Debug Reset                */
+    ALT_RESET_EVENT_FPGADBGRST          = 0x00040000,
+
+    /*! DAP Debug Reset                      */
+    ALT_RESET_EVENT_CDBGREQRST          = 0x00080000,
+
+    /*! SDRAM Self-Refresh Timeout           */
+    ALT_RESET_EVENT_SDRSELFREFTIMEOUT   = 0x01000000,
+
+    /*! FPGA manager handshake Timeout       */
+    ALT_RESET_EVENT_FPGAMGRHSTIMEOUT    = 0x02000000,
+
+    /*! SCAN manager handshake Timeout       */
+    ALT_RESET_EVENT_SCANHSTIMEOUT       = 0x04000000,
+
+    /*! FPGA handshake Timeout               */
+    ALT_RESET_EVENT_FPGAHSTIMEOUT       = 0x08000000,
+
+    /*! ETR Stall Timeout                    */
+    ALT_RESET_EVENT_ETRSTALLTIMEOUT     = 0x10000000
+} ALT_RESET_EVENT_t;
+
+/******************************************************************************/
+/*!
+ * Gets the reset and timeout events that caused the last reset.
+ *
+ * The ALT_RESET_EVENT_t enumeration values should be used to selectively
+ * examine the returned reset cause(s).
+ *
+ * \returns     A mask of the reset and/or timeout events that caused the last
+ *              reset.
+ */
+uint32_t alt_reset_event_get(void);
+
+/******************************************************************************/
+/*!
+ * Clears the reset and timeout events that caused the last reset.
+ *
+ * \param       event_mask
+ *              A mask of the selected reset and timeout events to clear in the
+ *              Reset Manager \e stat register. The mask selection can be formed
+ *              using the ALT_RESET_EVENT_t enumeration values.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_CTRL Reset Control
+ *
+ * This functional group provides global and selective reset control for the SoC
+ * and its constituent modules.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Initiate a cold reset of the SoC.
+ *
+ * If this function is successful, then it should never return.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_cold_reset(void);
+
+/******************************************************************************/
+/*!
+ * Initiate a warm reset of the SoC.
+ *
+ * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
+ * reset handshake with certain modules can optionally be requested in an
+ * attempt to ensure an orderly reset transition.
+ *
+ * \param       warm_reset_delay
+ *              Specifies the number of cycles after the Reset Manager releases
+ *              the Clock Manager reset before releasing any other hardware
+ *              controlled resets. Value must be greater than 16 and less than
+ *              256.
+ *
+ * \param       nRST_pin_clk_assertion
+ *              Specifies that number of clock cycles (osc1_clk?) to externally
+ *              assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
+ *              (2**20 - 1). A value of 0 prevents any assertion of nRST.
+ *
+ * \param       sdram_refresh
+ *              Controls whether the contents of SDRAM survive a hardware
+ *              sequenced warm reset. The reset manager requests the SDRAM
+ *              controller to put SDRAM devices into self-refresh mode before
+ *              asserting warm reset signals. An argument value of \b true
+ *              enables the option, \b false disables the option.
+ *
+ * \param       fpga_mgr_handshake
+ *              Controls whether a handshake between the reset manager and FPGA
+ *              manager occurs before a warm reset. The handshake is used to
+ *              warn the FPGA manager that a warm reset is imminent so it can
+ *              prepare for it by driving its output clock to a quiescent state
+ *              to avoid glitches. An argument value of \b true enables the
+ *              option, \b false disables the option.
+ *
+ * \param       scan_mgr_handshake
+ *              Controls whether a handshake between the reset manager and scan
+ *              manager occurs before a warm reset. The handshake is used to
+ *              warn the scan manager that a warm reset is imminent so it can
+ *              prepare for it by driving its output clock to a quiescent state
+ *              to avoid glitches. An argument value of \b true enables the
+ *              option, \b false disables the option.
+ *
+ * \param       fpga_handshake
+ *              Controls whether a handshake between the reset manager and the
+ *              FPGA occurs before a warm reset. The handshake is used to warn
+ *              the FPGA that a warm reset is imminent so that the FPGA prepare
+ *              for the reset event in soft IP. An argument value of \b true
+ *              enables the option, \b false disables the option.
+ *
+ * \param       etr_stall
+ *              Controls whether the ETR is requested to idle its AXI master
+ *              interface (i.e. finish outstanding transactions and not initiate
+ *              any more) to the L3 Interconnect before a warm reset. An
+ *              argument value of \b true enables the option, \b false disables
+ *              the option.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
+                                     uint32_t nRST_pin_clk_assertion,
+                                     bool sdram_refresh,
+                                     bool fpga_mgr_handshake,
+                                     bool scan_mgr_handshake,
+                                     bool fpga_handshake,
+                                     bool etr_stall);
+
+/*! @} */
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_RESET_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_system_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_system_manager.h
new file mode 100644
index 0000000..921dee6
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_system_manager.h
@@ -0,0 +1,209 @@
+/*! \file
+ *  Altera - SoC FPGA System Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_SYS_MGR_H__
+#define __ALT_SYS_MGR_H__
+
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************/
+/*! \addtogroup SYS_MGR The System Manager
+ *
+ * The System Manager API defines functions for control of system operation and
+ * for other modules requiring external control as part of system integration.
+ * 
+ * The major functional APIs include:
+ * * HPS I/O configuration and pin muxing
+ * * External control of other modules
+ * * Control and status of ECC
+ * * Fault injection for ECC and parity errors.
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup SYS_MGR_FPGA_INTERFACE FPGA Interface Group
+ *
+ * These functions provide enable/disable control and operational status of the
+ * signal interfaces between the FPGA and HPS.  Selective enabling/disabling of
+ * interfaces may be required under the following scenarios:
+ * * Interfaces that are associated with an HPS module but that are not disabled
+ *   when the HPS module associated with the interface is put into reset.
+ * * An HPS module accepts signals from the FPGA and those signals might
+ *   otherwise interfere with the normal operation of the HPS module.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the FPGA to HPS signal interfaces controlled
+ * by the functions in this API group.
+ */
+typedef enum ALT_FPGA_INTERFACE_e
+{
+    ALT_FPGA_INTERFACE_GLOBAL,      /*!< All interfaces between the FPGA and
+                                     *   HPS. If ALT_FPGA_INTERFACE_ALL is disabled
+                                     *   then all of the individual and module
+                                     *   interfaces between the FPGA and HPS are
+                                     *   disabled regardless of their separate
+                                     *   enable/disable settings. If
+                                     *   ALT_FPGA_INTERFACE_ALL is enabled then each
+                                     *   individual and module interface between
+                                     *   the FPGA and HPS may be separately
+                                     *   enabled/disabled.
+                                     */
+    ALT_FPGA_INTERFACE_RESET_REQ,   /*!< The reset request interface. This
+                                     *   interface allows logic in the FPGA to
+                                     *   request HPS resets. The following reset
+                                     *   request signals from the FPGA fabric to
+                                     *   HPS are part of this interface:
+                                     *   * \b f2h_cold_rst_req_n - Triggers a HPS cold reset
+                                     *   * \b f2h_warm_rst_req_n - Triggers a HPS warm reset
+                                     *   * \b f2h_dbg_rst_req_n - Triggers a HPS debug reset
+                                     */
+    ALT_FPGA_INTERFACE_JTAG_ENABLE, /*!< The JTAG enable interface. This
+                                     *   interface allows logic in the FPGA
+                                     *   fabric to disable the HPS JTAG
+                                     *   operation.
+                                     */
+    ALT_FPGA_INTERFACE_CONFIG_IO,   /*!< The CONFIG_IO interface. This interface
+                                     *   allows the FPGA JTAG TAP controller to
+                                     *   execute the CONFIG_IO instruction and
+                                     *   configure all device I/O (FPGA and
+                                     *   HPS).
+                                     */
+    ALT_FPGA_INTERFACE_BSCAN,       /*!< The boundary-scan interface. This
+                                     *   interface allows the FPGA JTAG TAP
+                                     *   controller to execute boundary-scan
+                                     *   instructions.
+                                     */
+    ALT_FPGA_INTERFACE_TRACE,       /*!< The trace interface. This interface
+                                     *   allows the HPS debug logic to send
+                                     *   trace data to logic in the FPGA.
+                                     */
+    ALT_FPGA_INTERFACE_DBG_APB,     /*!< (Private) The debug APB interface. This
+                                     *   interface allows the HPS debug logic to
+                                     *   communicate with debug APB slaves in
+                                     *   the FPGA fabric.
+                                     */
+    ALT_FPGA_INTERFACE_STM,         /*!< The STM event interface. This interface
+                                     *   allows logic in the FPGA to trigger
+                                     *   events to the HPS STM debug module.
+                                     */
+    ALT_FPGA_INTERFACE_CTI,         /*!< The Cross Trigger Interface (CTI). This
+                                     *   interface allows logic in the FPGA to
+                                     *   send triggers to HPS debug logic. Note
+                                     *   that this does not prevent the HPS
+                                     *   debug logic from sending triggers to
+                                     *   the FPGA.
+                                     */
+    ALT_FPGA_INTERFACE_EMAC0,       /*!< Signal interface from the FPGA to the
+                                     *   EMAC0 module.
+                                     */
+    ALT_FPGA_INTERFACE_EMAC1,       /*!< Signal interface from the FPGA to the
+                                     *   EMAC1 module.
+                                     */
+    ALT_FPGA_INTERFACE_SPIM0,       /*!< (Private) Signal interface from the
+                                     *   FPGA to the SPI Master 0 module.
+                                     */
+    ALT_FPGA_INTERFACE_SPIM1,       /*!< (Private) Signal interface from the
+                                     *   FPGA to the SPI Master 0 module.
+                                     */
+    ALT_FPGA_INTERFACE_NAND,        /*!< (Private) Signal interface from the
+                                     *   FPGA to the NAND Flash Controller
+                                     *   module.
+                                     */
+    ALT_FPGA_INTERFACE_SDMMC        /*!< (Private) Signal interface from the
+                                     *   FPGA to the SD/MMC Controller module.
+                                     */
+} ALT_FPGA_INTERFACE_t;
+
+/******************************************************************************/
+/*!
+ * Disables the specified FPGA to HPS signal interface.
+ *
+ * Isolates and disables the designated FPGA/HPS signal interface. User is
+ * responsible for determining that the interface is inactive before disabling
+ * it.
+ *
+ * \param       intfc
+ *              The interface to disable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e intfc argument designates an invalid
+ *                              FPGA/HPS signal interface.
+ */
+ALT_STATUS_CODE alt_fpga_interface_disable(ALT_FPGA_INTERFACE_t intfc);
+
+/******************************************************************************/
+/*!
+ * Enables the specified FPGA to HPS signal interface.
+ *
+ * \param       intfc
+ *              The interface to enable.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was succesful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   The \e intfc argument designates an invalid
+ *                              FPGA/HPS signal interface.
+ */
+ALT_STATUS_CODE alt_fpga_interface_enable(ALT_FPGA_INTERFACE_t intfc);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified FPGA/HPS signal interface is enabled or not.
+ *
+ * \param       intfc
+ *              The interface to enable.
+ *
+ * \retval      ALT_E_TRUE      The interface is enabled.
+ * \retval      ALT_E_FALSE     The interface is not enabled.
+ * \retval      ALT_E_BAD_ARG   The \e intfc argument designates an invalid
+ *                              FPGA/HPS signal interface.
+ */
+ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc);
+
+/*! @} */
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_SYS_MGR_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_timers.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_timers.h
new file mode 100644
index 0000000..b605195
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_timers.h
@@ -0,0 +1,677 @@
+/*! \file
+ *  Altera - Module Description
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_GPT_H__
+#define __ALT_GPT_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************/
+/*! \addtogroup GPT_MGR The General Purpose Timer Manager API
+ *
+ *  There are nine on-chip general purpose timers. Seven timers are available
+ *  to each CPU.\n\n
+ *  There are four types of timers available:
+ *     - Four general-purpose countdown timers available to CPU0, CPU1, or the
+ *     FPGA.\n
+ *     - Each CPU has a private GP countdown timer available only to itself.\n
+ *     - Each CPU has a watchdog timer  available only to itself that can work in
+ *     GP timer countdown mode.\n
+ *     - One continuous-countup global timer with compare capabilities available to
+ *     both CPUs and the FPGA.\n\n
+ *     Each type has a somewhat different HW interface This API presents the same
+ *     external interface for each.
+ * 
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the names of the timers  
+ * managed by the General Purpose Timers Manager.
+ */
+typedef enum ALT_GPT_TIMER_e
+{
+     /*!
+      * \b CPU_GLOBAL_TMR - CPU Core Global timer - There is one 64-bit 
+      * continuously incrementing counter for all CPU cores that is clocked 
+      * by PERIPHCLK. CPU_GLOBAL_TMR selects the comparator value, compare 
+      * enable, autoincrement value, autoincrement enable, and interrupt 
+      * enable for the CPU this code is running on.
+      */
+    ALT_GPT_CPU_GLOBAL_TMR,
+
+    /*!
+     * \b CPU_PRIVATE_TMR - CPU Core 32-bit Private Timer - The private timer
+     * for the CPU this code is running on. Clocked by PERIPHCLK. Counts 
+     * down to zero and can either stop or restart.
+     */
+    ALT_GPT_CPU_PRIVATE_TMR,
+
+    /*!
+     * \b CPU_WDTGPT_TMR - CPU Core 32-bit Watchdog Timer - The watchdog 
+     * timer can be used as a general-purpose timer by calling 
+     * alt_wdt_response_mode_set() to put the watchdog timer in general-purpose 
+     * timer mode. It is recommended that programmers use the other available 
+     * timers first before using the watchdog timer as there is more software 
+     * overhead involved in using the watchdog timer in this mode. This enum is 
+     * for the core watchdog timer of the CPU this code is running on. Counts 
+     * down to zero and can either stop or restart.
+     */
+    ALT_GPT_CPU_WDTGPT_TMR,
+
+    /* Peripheral Timers */
+    /* OSC1 Clock Group */
+    /*!
+     * \b osc1_timer0 - 32-bit timer connected to the L4_OSC1 bus clocked by 
+     * osc1_clk. Counts down to zero and can either stop or restart.
+     */
+    ALT_GPT_OSC1_TMR0,
+    
+    /*!
+     * \b osc1_timer1 - 32-bit timer connected to the L4_OSC1 bus clocked by 
+     * osc1_clk. Counts down to zero and can either stop or restart.
+     */
+    ALT_GPT_OSC1_TMR1,
+    
+    /* L4_SP Clock Group */
+    /*!
+     * \b sp_timer0 - 32-bit timer connected to the L4_SP bus clocked by 
+     * l4_sp_clk. Counts down to zero and can either stop or restart.
+     */
+    ALT_GPT_SP_TMR0,
+    
+    /*!
+     * \b sp_timer1 - 32-bit timer connected to the L4_SP bus clocked by 
+     * l4_sp_clk. Counts down to zero and can either stop or restart.
+     */
+    ALT_GPT_SP_TMR1
+
+}  ALT_GPT_TIMER_t;
+  
+    
+/*!
+ * This type definition enumerates the possible rollover or restart modes 
+ * of the general purpose timers.
+ */
+typedef enum ALT_GPT_RESTART_MODE_e
+{
+     /*!
+     * \b ONE-SHOT \b MODE - \b CPU_PRIVATE_TMR,  
+     * \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1
+     * count down from the value set with alt_gpt_counter_set() to 
+     * zero, trigger an interrupt and stop.\n
+     * The global timer \b CPU_GLOBAL_TMR counts up to the next compare value 
+     * set by the compare value, triggers an interrupt and stops 
+     * comparing.
+     */
+     ALT_GPT_RESTART_MODE_ONESHOT,
+
+    /*!
+     * \b USER-SUPPLIED \b COUNT - For \b CPU_PRIVATE_TMR,  \b OSC1_TMR0, 
+     * \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1, the timer counts down 
+     * to zero and then resets to a value previously set using 
+     * alt_gpt_counter_set() and continues counting.\n 
+     * \b CPU_GLOBAL_TMR counts up to the comparator value, then adds 
+     * the value set in alt_gpt_counter_set() to the comparator value and 
+     * continues counting.
+     */
+     ALT_GPT_RESTART_MODE_PERIODIC
+
+} ALT_GPT_RESTART_MODE_t;
+
+
+/******************************************************************************/
+/*! \addtogroup GPT_STATUS Enable, Disable, and Status
+ * 
+ * This functional group handles enabling, disabling, and reading the
+ * current enable state of the general purpose timers and the global timer.
+ * 
+ * @{  
+ */    
+/******************************************************************************/
+/*!
+ * Stop and disable the specified general purpose timer or global timer.
+ *
+ * 
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to stop an invalid timer.
+ */
+ALT_STATUS_CODE alt_gpt_tmr_stop(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Enable and start the specified general purpose timer or global timer.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to start an invalid timer.
+ */
+ALT_STATUS_CODE alt_gpt_tmr_start(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns whether the specified timer is currently running or not.
+ * For the free-running 64-bit global timer, returns whether its comparison 
+ * mode is enabled or not.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_TRUE      The timer is currently enabled and running.
+ * \retval      ALT_E_FALSE     The timer is currently disabled and stopped.
+ * \retval      ALT_E_BAD_ARG   Tried to access an invalid timer.
+ */
+ALT_STATUS_CODE alt_gpt_tmr_is_running(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Restarts the specified general purpose timer with its original value. If 
+ * used for the global timer, it updates the comparator value with the sum of
+ * the auto-increment value and the current global timer value and enables
+ * comparison mode.
+ *
+ *  
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to access an invalid timer.
+ */
+ALT_STATUS_CODE alt_gpt_tmr_reset(ALT_GPT_TIMER_t tmr_id);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup GPT_COUNTER Counters Interface
+ * 
+ * This functional group handles setting and reading the general purpose 
+ * timer counters and the global timer.
+ *
+ * @{  
+ * */
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b 
+ * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, sets the countdown value of the 
+ * specified timer and the value that the counter will reset to (in rollover 
+ * mode) or if restarted (in one-shot mode). It does not automatically start
+ * the counter. \n For tmr_id = \b CPU_GLOBAL_TMR, 
+ * this function sets the auto-increment value instead, which is similar in
+ * function to setting the reset value of the other timers. The effect of this 
+ * function is identical to using alt_globaltmr_autoinc_set().
+ *
+ *  
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \param       val
+ *              The 32-bit counter value to load.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_counter_set(ALT_GPT_TIMER_t tmr_id,
+        uint32_t val);
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b 
+ * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the current counter value of 
+ * the specified timer. \n For tmr_id = \b CPU_GLOBAL_TMR, returns the 32 
+ * low-order bits of the counter and is identical to the result returned by 
+ * alt_globaltmr_counter_get_low32(). Use alt_globaltmr_get() to obtain the full
+ * 64-bit timer value.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t     The current 32-bit counter value.
+ */
+uint32_t alt_gpt_counter_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b 
+ * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the counter value that is 
+ * set to be reloaded when the specified timer hits zero. \n
+ * For tmr_id =  \b CPU_GLOBAL_TMR, returns the value that will 
+ * autoincrement the comparator value, which defines the time until the next 
+ * comparator interrupt is triggered.  This is similar in function to the
+ * reset value of the other timers. It is identical to the result returned by
+ * alt_globaltmr_autoinc_get(). \n The value returned does not take into
+ * CPU_PRIVATE_TMR and  \b CPU_GLOBAL_TMR. The prescaler value may be obtained 
+ * with alt_gpt_prescaler_get().
+ * 
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t    The reset counter value currently set.
+ * \retval      0           An error occurred. 
+ */
+uint32_t alt_gpt_reset_value_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the maximum counter value available for the specified 
+ * timer. Valid for \b CPU_PRIVATE_TMR, \b OSC1_TMR0, 
+ * \b OSC1_TMR1, \b SP_TMR0, \b SP_TMR1, and \b CPU_GLOBAL_TMR. \n
+ * The value returned does not factor in the value of the clock prescaler 
+ * available for \b CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR.
+ *   
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t    The maximum counter value available for this timer.
+ * \retval      0           An error occurred. 
+ *
+ */
+uint32_t alt_gpt_maxcounter_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Sets the clock prescaler value of the specified timer. Valid for \b
+ * CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns an error 
+ * if called with a tmr_id of \b OSC1_TMR0, 
+ * \b OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \param       val
+ *              The 32-bit prescaler value to load. Valid range is 1-256.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_prescaler_set(ALT_GPT_TIMER_t tmr_id,
+        uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the clock prescaler value of the specified timer. Valid for \b
+ * CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns one if
+ * called with a tmr_id of \b OSC1_TMR0, \b 
+ * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler.
+ *
+ *  
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t    The prescaler value. Valid range is 1-256.
+ *                             Zero indicates an error.
+ */
+uint32_t alt_gpt_prescaler_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the integer portion of the current countdown frequency of the
+ * specified timer.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      unint32_t    The integer portion of the repeat frequency of the
+ *                             given timer, measured in Hertz (cycles per second).
+ */
+uint32_t alt_gpt_freq_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the current period of the specified timer measured in seconds.
+ * If the result is less than 64, alt_gpt_millisecs_get() will give a more
+ * precise result.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The current period of the given timer, measured
+ *                         in seconds.
+ */
+uint32_t alt_gpt_time_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the current period of the specified timer measured in milliseconds.
+ *
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The current period of the given timer, measured
+ *                         in milliseconds. Returns 0 if result cannot fit
+ *                         in 32 bits. alt_gpt_time_get() can be used to
+ *                         obtain measurements of longer periods.
+ *                         alt_gpt_microsecs_get() can be used to obtain
+ *                         more precise measurements of shorter periods.
+ */
+uint32_t alt_gpt_time_millisecs_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the current period of the specified timer measured in milliseconds.
+ *
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The current period of the given timer, measured
+ *                         in microseconds. Returns 0 if result cannot fit
+ *                         in 32 bits. alt_gpt_millisecs_get() and
+ *                         alt_gpt_time_get() can be used to obtain
+ *                         measurements of longer periods.
+ */
+uint32_t alt_gpt_time_microsecs_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0,
+ * or \b SP_TMR1, returns the current time until the specified timer counts
+ * down to zero, measured in seconds. \n Returns zero for tmr_id = \b
+ * CPU_GLOBAL_TMR.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t     The current 32-bit counter value.
+ */
+uint32_t alt_gpt_curtime_get(ALT_GPT_TIMER_t tmr_id);
+
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0,
+ * or \b SP_TMR1, returns the current time until the specified timer counts
+ * down to zero, measured in milliseconds. \n Returns 0xFFFFFFFF if the value
+ * is too large to be expressed in 32 bits. \n Returns zero for tmr_id = \b
+ * CPU_GLOBAL_TMR.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t     The current 32-bit counter value.
+ */
+uint32_t alt_gpt_curtime_millisecs_get(ALT_GPT_TIMER_t tmr_id);
+
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0,
+ * or \b SP_TMR1, returns the current time until the specified timer counts
+ * down to zero, measured in microseconds. \n Returns  0xFFFFFFFF if the value
+ * is too large to be expressed in 32 bits. \n Returns zero for tmr_id = \b
+ * CPU_GLOBAL_TMR.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t     The current 32-bit counter value.
+ */
+uint32_t alt_gpt_curtime_microsecs_get(ALT_GPT_TIMER_t tmr_id);
+
+
+/******************************************************************************/
+/*!
+ * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0,
+ * or \b SP_TMR1, returns the current time until the specified timer counts
+ * down to zero, measured in nanoseconds. \n Returns  0xFFFFFFFF if the value
+ * is too large to be expressed in 32 bits. \n Returns zero for tmr_id = \b
+ * CPU_GLOBAL_TMR.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t     The current 32-bit counter value.
+ */
+uint32_t alt_gpt_curtime_nanosecs_get(ALT_GPT_TIMER_t tmr_id);
+
+
+/******************************************************************************/
+/*!
+ * Returns the maximum available period of the specified
+ * timer measured in seconds.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The maximum period of the given timer, measured
+ *                         in seconds. Returns 0 if result cannot fit
+ *                         in 32 bits.
+ */
+uint32_t alt_gpt_maxtime_get(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the maximum available period of the specified
+ * timer measured in milliseconds.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The maximum period of the given timer, measured
+ *                         in milliseconds. Returns 0 if result cannot fit
+ *                         in 32 bits.
+ */
+uint32_t alt_gpt_maxtime_millisecs_get(ALT_GPT_TIMER_t tmr_id);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup GPT_INT Interrupts
+ * This functional group handles managing, setting, clearing, and disabling 
+ * the interrupts of the general purpose timers and the global timer.
+ * @{  */
+/******************************************************************************/
+/*!
+ * Disables the interrupt from the specified general purpose timer or
+ * global timer module.
+ *
+ * 
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_int_disable(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Enables the interrupt of the specified general purpose timer or global 
+ * timer module. 
+ * 
+ * 
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_int_enable(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Return \b TRUE if the interrupt of the specified timer module is enabled 
+ * and \b FALSE if the interrupt is disabled or masked. 
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      TRUE            The timer interrupt is currently enabled.
+ * \retval      FALSE           The timer interrupt is currently disabled.
+ */
+bool alt_gpt_int_is_enabled(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Clear the pending interrupt status of the specified timer module.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_int_clear_pending(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Read the state (pending or not) of the interrupt of the specified timer 
+ * module without changing the interrupt state.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_TRUE            The timer interrupt is currently pending.
+ * \retval      ALT_E_FALSE           The timer interrupt is not currently pending.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_int_is_pending(ALT_GPT_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Read the state of the interrupt of the specified general purpose timer 
+ * module and if the interrupt is set, clear it.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_TRUE            The timer interrupt is currently pending.
+ * \retval      ALT_E_FALSE           The timer interrupt is not currently pending.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_int_if_pending_clear(ALT_GPT_TIMER_t tmr_id);
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup GPT_MODE Mode Control
+ * This functional group handles setting and reading the operational mode of 
+ * the general purpose timers. The module version ID read function is also 
+ * located here.
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets the mode of the specified timer, the behavior that occurs when either 
+ * the general-purpose timer counts down to zero or when the the global timer
+ * reaches its comparator value.
+ * 
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \param       mode
+ *              \b GPT_RESTART_MODE_ONESHOT - To select one-shot mode for
+ *              the timer. 
+ * \n           \b GPT_RESTART_MODE_PERIODIC - To select free-run mode for
+ *              the timer.
+ *
+ * \internal
+ *   The HHP HPS Timer NPP states that the value of the counter (Timer1LoadCount 
+ *   register) must be set to 0xFFFFFFFF before changing this setting to free-
+ *   running mode (and timer must be disabled). The relevent L4 peripheral 
+ *   document does not mention the requirement to write 0xFFFFFFFF to the 
+ *   Timer1LoadCount register though.
+ * \endinternal
+ *
+ *   
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpt_mode_set(ALT_GPT_TIMER_t tmr_id,
+        ALT_GPT_RESTART_MODE_t mode);
+
+/******************************************************************************/
+/*!
+ * Reads the mode of the specified timer. 
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      GPT_RESTART_MODE_ONESHOT    Timer is set to one-shot mode.
+ * \retval      GPT_RESTART_MODE_PERIODIC   Counter value is set to a 
+ *                                              user-defined value.
+ * \retval      ALT_E_BAD_ARG               Invalid input argument.
+ */
+int32_t alt_gpt_mode_get(ALT_GPT_TIMER_t tmr_id);
+
+/*! @} */
+/*! @} */
+/*! @} */
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_GPT_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_watchdog.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_watchdog.h
new file mode 100644
index 0000000..0d4b9ad
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_watchdog.h
@@ -0,0 +1,779 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __ALT_WDOG_H__
+#define __ALT_WDOG_H__
+
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /* __cplusplus */
+
+/*! \addtogroup WDOG_MGR The Watchdog Timer Manager API
+ *
+ * This module defines the Watchdog Timer Manager API for accessing, configuring, and
+ * controlling the HPS Watchdog Timer resources.
+ *
+ *
+A typical initialization might be:
+\verbatim
+ALT_STATUS_CODE ret;
+ret = alt_wdog_int_clear(ALT_CPU_WATCHDOG);
+if (ret == ALT_E_SUCCESS) {ret = alt_wdog_counter_set(ALT_CPU_WATCHDOG, 0x7FFFFFFF); }
+if (ret == ALT_E_SUCCESS) {ret = alt_wdog_core_prescaler_set(0x80); }
+if (ret == ALT_E_SUCCESS) {ret = alt_wdog_response_mode_set(ALT_CPU_WATCHDOG, ALT_WDOG_TIMER_MODE_FREERUN); }
+if (ret == ALT_E_SUCCESS) {ret = alt_wdog_int_enable(ALT_CPU_WATCHDOG); }
+if (ret == ALT_E_SUCCESS) {ret = alt_wdog_start(ALT_CPU_WATCHDOG); }
+\endverbatim
+
+Then periodically (before it runs out) call this function to restart the watchdog:
+\verbatim
+alt_wdog_reset(ALT_CPU_WATCHDOG);
+\endverbatim
+
+If the interrupt is enabled in the interrupt manager and is triggered, it can be
+cleared like this:
+\verbatim
+alt_wdog_int_clear(ALT_CPU_WATCHDOG);
+\endverbatim
+
+
+If the interrupt is not enabled in the interrupt manager, you can still poll to
+see if it hit zero and clear any pending interrupts like this:
+\verbatim
+alt_wdog_int_if_pending_clear(ALT_CPU_WATCHDOG);
+\endverbatim
+ *
+ * @{
+ */
+/******************************************************************************/
+
+/*!
+ * This type definition enumerates the names of the timers managed by 
+ * the Watchdog Timers Manager.
+ */
+typedef enum ALT_WDOG_TIMER_e {
+    /* OSC1 Clock Group */
+    /*!
+     * \b ALT_CPU_WATCHDOG - Each CPU core has its own watchdog timer, which is
+     * clocked by PERIPHCLK. Can be loaded with any 32-bit counter 
+     * value, not limited to powers of two, and it has an 8-bit prescaler.
+     * This timer also has a pause-enable input that can allow other HW
+     * to freeze the countdown.
+     */
+    ALT_WDOG_CPU,
+
+    /* OSC1 Clock Group */
+    /*!
+     * \b watchdog_timer0 - Connected to the L4_OSC1 bus clocked by osc1_clk.
+     * Counter values are limited to powers of two between 15 and 31
+     * and there is no prescaler.
+     */
+    ALT_WDOG0,
+
+    /*!
+     * \b watchdog_timer1 - Connected to the L4_OSC1 bus clocked by osc1_clk.
+     * Counter values are limited to powers of two between 15 and 31
+     * and there is no prescaler.
+     */
+    ALT_WDOG1,
+
+    /*!
+     * \b watchdog_init_timer0 - This is for the initial timout only (not 
+     * necessarily immediately after system restart), watchdog_timer0 is then 
+     * used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked 
+     * by osc1_clk.
+     * Counter values are limited to powers of two between 15 and 31 and 
+     * there is no prescaler.
+     */
+    ALT_WDOG0_INIT,
+
+    /*!
+     * \b watchdog_init_timer1 - This is for the initial timout only (not 
+     * necessarily immediately after system restart), watchdog_timer1 is then 
+     * used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked 
+     * by osc1_clk.
+     * Counter values are limited to powers of two  between 15 and 31 and 
+     * there is no prescaler.
+     */
+    ALT_WDOG1_INIT
+} ALT_WDOG_TIMER_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the encoded countdown values that \b
+ * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL
+ * can be set to use.
+ */
+typedef enum ALT_WDOG_TIMEOUT_e {
+    /*!
+     * \b ALT_WDOG_TIMEOUT64K - Timeout = 65,536 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT64K,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT128K - Timeout = 131,072 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT128K,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT256K - Timeout = 262,144 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT256K,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT512K - Timeout = 524,288 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT512K,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT1M - Timeout = 1,048,576 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT1M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT2M - Timeout = 2,097,152 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT2M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT4M - Timeout = 4,194,304 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT4M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT8M - Timeout = 8,388,608 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT8M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT16M - Timeout = 16,777,216 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT16M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT32M - Timeout = 33,554,432 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT32M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT64M - Timeout = 67,108,864 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT64M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT128M - Timeout = 134,217,728 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT128M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT256M - Timeout = 268,435,456 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT256M,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT512M - Timeout = 536,870,912 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT512M,
+
+    /*!
+     * 
+     * \b ALT_WDOG_TIMEOUT1G - Timeout = 1,073,741,824 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT1G,
+
+    /*!
+     * \b ALT_WDOG_TIMEOUT2G - Timeout = 2,147,483,648 osc1_clk periods.
+     */
+    ALT_WDOG_TIMEOUT2G
+} ALT_WDOG_TIMEOUT_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the reset types that the watchdog 
+ * timers can be set to trigger.
+ */
+typedef enum ALT_WDOG_RESET_TYPE_e {
+    /*!
+     * \b Reset -  For \b  ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL,
+     * and \b ALT_WATCHDOG1_INITIAL, if the counter reaches zero without being
+     * reset, generate a system-wide warm reset request. 
+     * This is the default mode out of reset. \n For \b ALT_CPU_WATCHDOG, no
+     * interrupt is triggered and a reset request is asserted. The response 
+     * to the reset request is set in the reset controller block and may 
+     * not automatically trigger a system reset.
+     */
+    ALT_WDOG_WARM_RESET,
+
+    /*!
+     * \b Interrupt_First - When the counter reaches zero without being 
+     * reset, generate an interrupt. For \b ALT_WATCHDOG0, \b
+     * ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL, if the
+     * interrupt is not cleared by the time a second timeout occurs, then 
+     * generate a system warm reset request. \n For \b ALT_CPU_WATCHDOG, the
+     * interrupt is triggered and a \b WDRESETREQ
+     * reset request is asserted. The response to the interrupt and the reset 
+     * request is set in the interrupt and reset controller blocks and may 
+     * not automatically trigger a system reset.
+     */
+    ALT_WDOG_INT_THEN_RESET,
+    
+    /*!
+     * \b Timer_mode_oneshot - The \b ALT_CPU_WATCHDOG timer has the capability
+     * to not only operate as a watchdog timer, but also to operate as a 
+     * general-purpose countdown timer. This selection specifies the \b 
+     * ALT_CPU_WATCHDOG runs
+     * in one-shot timer mode, and can optionally trigger an interrupt when 
+     * the counter reaches zero without being reset. This
+     * is the default selection for \b ALT_CPU_WATCHDOG out of reset. \n
+     * This selection has no meaning for \b  ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
+     * ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL.
+     */
+    ALT_WDOG_TIMER_MODE_ONESHOT,
+    
+    /*!
+     * \b Timer_mode_freerun - The \b ALT_CPU_WATCHDOG timer has the capability
+     * to not only operate as a watchdog timer, but also to operate as a 
+     * general-purpose countdown timer. This selection specifies the \b 
+     * ALT_CPU_WATCHDOG in
+     * free-run or wraparound timer mode, and can optionally trigger an 
+     * interrupt when the counter reaches zero without being reset. \n 
+     * This selection has no meaning for \b  
+     * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL.
+     */
+    ALT_WDOG_TIMER_MODE_FREERUN
+} ALT_WDOG_RESET_TYPE_t;
+
+/******************************************************************************/
+/*! \addtogroup WDOG_STATUS Watchdog Timer Enable, Disable, Restart, Status
+ *
+ * This functional group contains the basic functions to control and manage
+ * the watchdog timers.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Stop the specified watchdog timer. \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
+ *  ALT_WATCHDOG0_INITIAL and \b ALT_WATCHDOG1_INITIAL cannot be stopped
+ *  once started.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to stop an invalid watchdog timer.
+ */
+ALT_STATUS_CODE alt_wdog_stop(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Start the specified watchdog timer.
+ *
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to enable an invalid watchdog timer.
+ */
+ALT_STATUS_CODE alt_wdog_start(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns whether the specified watchdog timer is currently running or not.
+ *
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      TRUE            The timer is currently running.
+ * \retval      FALSE           The timer is currently not running.
+ */
+bool alt_wdog_tmr_is_enabled(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Reloads the counter countdown value, clears the timer interrupt, and
+ * restarts the watchdog timer. User can reset the timer at any time before
+ * timeout. This is also known as kicking, petting, feeding, waking, or
+ * walking the watchdog. \n If the timer is reset while stopped, it remains
+ * stopped, the timer reset value is reloaded and the countdown will start
+ * from there when it is started. The timer configuration is retained.
+ *
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to reset an invalid watchdog timer.
+ */
+ALT_STATUS_CODE alt_wdog_reset(ALT_WDOG_TIMER_t tmr_id);
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup WDOG_COUNTERS Watchdog Timer Counter Configuration
+ *
+ *
+ * This functional group implements setting, configuring and reading
+ * the counters of the watchdog timers.
+ *
+ * @{ 
+ */
+/******************************************************************************/
+/*! Sets the countdown value of the specified timer. This is a regular value
+ *  for \b ALT_CPU_WATCHDOG. For tmr_id = \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
+ *  ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL however, this is an encoded
+ *  power-of-two value such that 2**(16 + val). \n
+ *  If this value is set before the watchdog timer is started, then this
+ *  value is used from the start. If this value is set after the timer
+ *  has been started, it takes effect when the timer rolls over or the next
+ *  time it is started.
+ *  
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \param       val
+ *              The counter value to load.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Tried to write an invalid watchdog timer or
+ *                                 timeout value.
+ */
+ALT_STATUS_CODE alt_wdog_counter_set(ALT_WDOG_TIMER_t tmr_id,
+        uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the current counter value of the specified timer.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ *
+ * \retval      uint32_t   The current 32-bit counter value.
+ */
+uint32_t alt_wdog_counter_get_current(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the current counter value of the specified timer, as measured in 
+ * milliseconds. For \b ALT_CPU_WATCHDOG, this includes the effects of the
+ * prescaler setting.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ *
+ * \retval      uint32_t   The current 32-bit counter value (in milliseconds).
+ */
+uint32_t alt_wdog_counter_get_curtime_millisecs(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the initial counter value of the specified timer as a 32-bit
+ * integer value. This is the value that will be reloaded when the timer 
+ * is reset or restarted. For the timers where this value is set as an 
+ * encoded powers-of-two between 15 and 31, the value is converted into the 
+ * equivalent binary value before returning it. \n For \b ALT_CPU_WATCHDOG,
+ * the returned value does not include the effects of the prescaler setting.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint32_t   The current 32-bit counter value.
+ *              0           Indicates an error.
+ */
+uint32_t alt_wdog_counter_get_init(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the initial value of the specified timer in nanoseconds.
+ * This is the value that will be reloaded when the timer is reset or
+ * restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the
+ * prescaler setting. This call returns a more precise result than
+ * alt_wdog_counter_get_inittime_millisecs(), but as an unsigned 64-bit
+ * integer.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint64_t   The currently-selected watchdog delay time (in 
+ *              nanoseconds).
+ */
+uint64_t alt_wdog_counter_get_inittime_nanosecs(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the initialized value of the specified timer in milliseconds.
+ * This is the value that will be reloaded when the timer is reset or
+ * restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the
+ * prescaler setting. This call returns a 32-bit unsigned integer, though is
+ * less precise than alt_wdog_counter_get_inittime_nanosecs().
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint32_t   The currently-selected watchdog delay time (in 
+ *              milliseconds).
+ *              0           Indicates an error.
+*/
+uint32_t alt_wdog_counter_get_inittime_millisecs(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Sets the value of the CPU watchdog timer \b ALT_CPU_WATCHDOG prescaler.
+ * Must be set before the watchdog timer is enabled.
+ *  
+ *
+ * \param       val
+ *              The eight-bit prescaler value to load (maximum 255).
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_BAD_ARG   Bad prescaler value specified.
+ */
+ALT_STATUS_CODE alt_wdog_core_prescaler_set(uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the value of the prescaler of the CPU core watchdog timer 
+ * \b ALT_CPU_WATCHDOG.
+ *
+ * \retval         val 
+ *                 The eight-bit prescaler value.
+ *                 
+ */
+uint32_t alt_wdog_core_prescaler_get(void);
+
+/******************************************************************************/
+/*!
+ * Returns the maximum possible counter value of the specified timer as a 
+ * 32-bit value. For the timers where this value is encoded (as 
+ * powers-of-two between 15 and 31), the encoded value is converted into the 
+ * equivalent binary value before returning it. This does not include the
+ * effects of the prescaler available for \b ALT_CPU_WATCHDOG.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint32_t   The current 32-bit counter value.
+ */
+uint32_t alt_wdog_counter_get_max(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the maximum possible delay time of the specified timer specified in
+ * nanoseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting.
+ * This call returns a more precise reading of the counter than
+ * alt_wdog_counter_get_max_millisecs(), though in an unsigned 64-bit integer.
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint64_t   The maximum delay time before timeout (in 
+ *              nanoseconds).
+ */
+uint64_t alt_wdog_counter_get_max_nanosecs(ALT_WDOG_TIMER_t tmr_id);
+
+
+/******************************************************************************/
+/*!
+ * Returns the maximum possible delay time of the specified timer specified in
+ * milliseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting.
+ * This call returns a 32-bit unsigned integer, though is less precise than
+ * alt_wdog_counter_get_max_nanosecs().
+ *
+ * \param       tmr_id
+ *              The watchdog timer identifier.
+ *
+ * \retval      uint32_t   The maximum delay time before timeout (in 
+ *              milliseconds).
+ */
+uint32_t alt_wdog_counter_get_max_millisecs(ALT_WDOG_TIMER_t tmr_id);
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup WDOG_INTS Watchdog Timer Interrupt Management
+ *
+ *
+ * This functional group implements management of the interrupts
+ *  of the watchdog timers.
+ *
+ * @{ 
+ */
+/******************************************************************************/
+/*!
+ * Disables the interrupt of the specified watchdog timer module.
+ * If the watchdog timer is one of the watchdog timers that can be used in
+ * general-purpose mode, and if the timer is in general-purpose timer mode,
+ * disable the interrupt.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Specified an incorrect timer.
+  */
+ALT_STATUS_CODE alt_wdog_int_disable(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Sets/enables the interrupt of the specified watchdog timer module.
+ * If the watchdog timer is one of the watchdog timers that can be used in
+ * general-purpose mode, and if the timer is in general-purpose timer mode,
+ * enable the interrupt.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Specified an incorrect timer.
+  */
+ALT_STATUS_CODE alt_wdog_int_enable(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the status of the interrupt of the specified watchdog timer module 
+ * but does not clear it. Return \b TRUE if the interrupt of the specified 
+ * general purpose timer module is pending and \b FALSE otherwise.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      TRUE            The timer interrupt is currently pending.
+ * \retval      FALSE           The timer interrupt is not currently pending.
+ */
+bool alt_wdog_int_is_pending(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the state of the interrupt of the specified watchdog timer module.
+ * If the watchdog timer is one of the watchdog timers that can be used in
+ * general-purpose mode, and if the timer is in general-purpose timer mode,
+ * returns \b TRUE if the interrupt of the specified general purpose timer
+ * module is enabled and \b FALSE if disabled. If the timer is not in
+ * general-purpose timer mode, returns /b TRUE, as watchdog interrupts are
+ * always enabled.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      TRUE            The timer interrupt is currently pending.
+ * \retval      FALSE           The timer interrupt is not currently pending.
+ */
+bool alt_wdog_int_is_enabled(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Clears the pending status of the interrupt of the specified watchdog
+ *  timer module.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ */
+ALT_STATUS_CODE alt_wdog_int_clear(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the status of the interrupt of the specified watchdog timer module 
+ * and also clears it. Return \b TRUE if the interrupt of the specified 
+ * general purpose timer module is pending and \b FALSE otherwise.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      TRUE            The timer interrupt was pending.
+ * \retval      FALSE           The timer interrupt was not pending.
+ */
+bool alt_wdog_int_if_pending_clear(ALT_WDOG_TIMER_t tmr_id);
+
+/*! @} */
+#if ALTERA_INTERNAL_ONLY_DOCS
+/******************************************************************************/
+/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration
+ *
+ * This functional group implements setting and reading the current
+ * timer mode as well as reading the module component code and version code.
+ *
+ * @{ 
+ */
+#else
+/******************************************************************************/
+/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration
+ *
+ * This functional group implements setting and reading the current
+ * timer mode.
+ *
+ * @{
+ */
+#endif
+/******************************************************************************/
+/*!
+ * Sets the timeout response mode of the specified watchdog timer. For \b 
+ * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, the
+ * options are to generate a system reset or to generate an interrupt and then 
+ * generate a system reset if the interrupt is not cleared by the next time 
+ * the watchdog timer counter rolls over.\n
+ * For \b ALT_CPU_WATCHDOG, the options are to trigger an interrupt request (with
+ * the result set in the interrupt manager) or a reset request (with the 
+ * result set in the reset manager) plus two more options available
+ * when it is used as a general-purpose timer.
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \param       type
+ *              \b ALT_WDOG_WARM_RESET - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
+ *              ALT_WATCHDOG0_INITIAL or \b  ALT_WATCHDOG1_INITIAL, reset the core
+ *              immediately. \n For \b ALT_CPU_WATCHDOG, the action is
+ *              determined by the current setting in the reset manager.\n\n
+ *              \b ALT_WDOG_INT_THEN_RESET -  For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b
+ *              ALT_WATCHDOG0_INITIAL or \b  ALT_WATCHDOG1_INITIAL, raise an interrupt.
+ *              If the interrupt is not cleared before the timer counts down 
+ *              to zero again, reset the CPU cores. \n For \b ALT_CPU_WATCHDOG,
+ *              raise an interrupt. \n\n \b ALT_WDOG_TIMER_MODE_ONESHOT - For \b
+ *              ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and one-shot
+ *              operation is selected.\n\n \b ALT_WDOG_TIMER_MODE_FREERUN - For \b
+ *              ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and free-run
+ *              operation is selected.
+ *   
+ * \retval      ALT_E_SUCCESS   The operation was successful.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Specified an incorrect timer or an unsupported 
+ *                              response mode for the specified timer.
+ */
+ALT_STATUS_CODE alt_wdog_response_mode_set(ALT_WDOG_TIMER_t tmr_id,
+                                           ALT_WDOG_RESET_TYPE_t type);
+
+/******************************************************************************/
+/*!
+ * Returns the response mode of the specified timer.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      ALT_WDOG_WARM_RESET
+ *              For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
+ *              ALT_WATCHDOG1_INITIAL, reset the core immediately. \n For \b
+ *              ALT_CPU_WATCHDOG, the action is determined by the current setting
+ *              in the reset manager.
+ * \retval      ALT_WDOG_INT_THEN_RESET Raise an interrupt. For \b ALT_WATCHDOG0, \b
+ *              ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, if
+ *              the interrupt is not cleared before timer wraps around again, 
+ *              reset the CPU cores. \n For \b ALT_CPU_WATCHDOG, the action is
+ *              determined by the current setting in the interrupt manager.
+ * \retval      ALT_WDOG_TIMER_MODE_ONESHOT    Core watchdog timer is set to timer
+ *              mode and one-shot operation is selected.
+ * \retval      ALT_WDOG_TIMER_MODE_FREERUN    Core watchdog timer is set to timer
+ *              mode and free-run operation is selected.
+ * \retval      ALT_E_ERROR     The operation failed.
+ * \retval      ALT_E_BAD_ARG   Specified an invalid timer. 
+ */
+int32_t alt_wdog_response_mode_get(ALT_WDOG_TIMER_t tmr_id);
+
+
+#if ALTERA_INTERNAL_ONLY_DOCS
+
+/******************************************************************************/
+/*!
+ * Returns the component code of the watchdog timer module. \n Only valid
+ * for \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
+ * ALT_WATCHDOG1_INITIAL.
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ * \retval      uint32_t      The component code of the module.
+ *                             It should be 0x44570120.
+ *
+ * \note    This is an Altera Internal Only function
+ *
+ */
+uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/*!
+ * Returns the version code of the watchdog timer module. \n Only valid for
+ * \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b
+ * ALT_WATCHDOG1_INITIAL.
+ *
+ *
+ * \param       tmr_id
+ *              The timer identifier.
+ *
+ *
+ * \retval      uint32_t      The encoded revision number of the module.
+ *
+ * \note    This is an Altera Internal Only function
+ *
+ */
+uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id);
+
+#else
+
+/******************************************************************************/
+/* Returns the component code of the watchdog timer module. Only valid
+ * for ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL.
+ *
+ *   This is an Altera Internal Only function
+ */
+
+uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id);
+
+/******************************************************************************/
+/* Returns the version code of the watchdog timer module. Only valid for
+ * ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL.
+ *
+ * This is an Altera Internal Only function
+ */
+
+uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id);
+
+#endif      /* ALTERA_INTERNAL_ONLY_DOCS */
+
+/******************************************************************************/
+
+/*! @} */
+/*! @} */
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALT_WDOG_H__ */
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h
new file mode 100644
index 0000000..7a3bbfd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* 
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+* 
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+* 
+******************************************************************************/
+
+#ifndef __HWLIB_H__
+#define __HWLIB_H__
+
+#ifdef __cplusplus
+#include <cstddef>
+#include <cstdbool>
+#include <cstdint>
+#else   /* __cplusplus */
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#endif  /* __cplusplus */
+
+#include "alt_hwlibs_ver.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*!
+ * The type definition for status codes returned by the HWLIB.
+ */
+typedef int32_t             ALT_STATUS_CODE;
+
+/*! Definitions of status codes returned by the HWLIB. */
+
+/*! The operation was successful. */
+#define ALT_E_SUCCESS               0
+
+/*! The operation failed. */
+#define ALT_E_ERROR                 (-1)
+/*! FPGA configuration error detected.*/
+#define ALT_E_FPGA_CFG              (-2)
+/*! FPGA CRC error detected. */
+#define ALT_E_FPGA_CRC              (-3)
+/*! An error occurred on the FPGA configuration bitstream input source. */
+#define ALT_E_FPGA_CFG_STM          (-4)
+/*! The FPGA is powered off. */
+#define ALT_E_FPGA_PWR_OFF          (-5)
+/*! The SoC does not currently control the FPGA. */
+#define ALT_E_FPGA_NO_SOC_CTRL      (-6)
+/*! The FPGA is not in USER mode. */
+#define ALT_E_FPGA_NOT_USER_MODE    (-7)
+/*! An argument violates a range constraint. */
+#define ALT_E_ARG_RANGE             (-8)
+/*! A bad argument value was passed. */
+#define ALT_E_BAD_ARG               (-9)
+/*! The operation is invalid or illegal. */
+#define ALT_E_BAD_OPERATION         (-10)
+/*! An invalid option was selected. */
+#define ALT_E_INV_OPTION            (-11)
+/*! An operation or response timeout period expired. */
+#define ALT_E_TMO                   (-12)
+/*! The argument value is reserved or unavailable. */
+#define ALT_E_RESERVED              (-13)
+/*! A clock is not enabled or violates an operational constraint. */
+#define ALT_E_BAD_CLK               (-14)
+/*! The version ID is invalid. */
+#define ALT_E_BAD_VERSION           (-15)
+/*! The buffer does not contain enough free space for the operation. */
+#define ALT_E_BUF_OVF               (-20)
+
+
+/*!
+ * Indicates a FALSE condition.
+ */
+#define ALT_E_FALSE                 (0)
+/*!
+ * Indicates a TRUE condition.
+ */
+#define ALT_E_TRUE                  (1)
+
+/* Note, additional positive status codes may be defined to return
+ * a TRUE condition with additional information */
+
+
+/* Some other useful definitions */
+
+/*!
+ * Specifies the current major and minor revision of the HWLibs. The
+ * MS four decimal digits specify the Altera ACDS release number, the
+ * LS two decimal digits specify minor revisions of the HWLibs, if any.
+ *
+ * A typical use is:
+ * \code
+ * #if  ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
+ * \endcode
+ *     for a dependency on the major or minor ACDS revision
+ *   or
+ * \code
+ * #if  ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
+ * \endcode
+ *     for a dependency on the hwlibs revision
+ *
+ */
+#define ALT_HWLIBS_VERSION(a,b,c)   (((a)*10000)+((b)*100)+(c))
+
+#define ALTERA_HWLIBS_VERSION_CODE   ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
+                                    ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
+
+/*!
+ * Allow some parts of the documentation to be hidden by setting to zero
+ */
+#define ALTERA_INTERNAL_ONLY_DOCS   1
+
+
+/*!
+ * Provide base address of MPU address space
+ */
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR            0
+#endif
+
+/*!
+ * These constants are sometimes useful:
+ */
+#define ALT_MILLISECS_IN_A_SEC      1000
+#define ALT_MICROSECS_IN_A_SEC      1000000
+#define ALT_NANOSECS_IN_A_SEC       1000000000
+
+#define ALT_TWO_TO_POW0             (1)
+#define ALT_TWO_TO_POW1             (1<<1)
+#define ALT_TWO_TO_POW2             (1<<2)
+#define ALT_TWO_TO_POW3             (1<<3)
+#define ALT_TWO_TO_POW4             (1<<4)
+#define ALT_TWO_TO_POW5             (1<<5)
+#define ALT_TWO_TO_POW6             (1<<6)
+#define ALT_TWO_TO_POW7             (1<<7)
+#define ALT_TWO_TO_POW8             (1<<8)
+#define ALT_TWO_TO_POW9             (1<<9)
+#define ALT_TWO_TO_POW10            (1<<10)
+#define ALT_TWO_TO_POW11            (1<<11)
+#define ALT_TWO_TO_POW12            (1<<12)
+#define ALT_TWO_TO_POW13            (1<<13)
+#define ALT_TWO_TO_POW14            (1<<14)
+#define ALT_TWO_TO_POW15            (1<<15)
+#define ALT_TWO_TO_POW16            (1<<16)
+#define ALT_TWO_TO_POW17            (1<<17)
+#define ALT_TWO_TO_POW18            (1<<18)
+#define ALT_TWO_TO_POW19            (1<<19)
+#define ALT_TWO_TO_POW20            (1<<20)
+#define ALT_TWO_TO_POW21            (1<<21)
+#define ALT_TWO_TO_POW22            (1<<22)
+#define ALT_TWO_TO_POW23            (1<<23)
+#define ALT_TWO_TO_POW24            (1<<24)
+#define ALT_TWO_TO_POW25            (1<<25)
+#define ALT_TWO_TO_POW26            (1<<26)
+#define ALT_TWO_TO_POW27            (1<<27)
+#define ALT_TWO_TO_POW28            (1<<28)
+#define ALT_TWO_TO_POW29            (1<<29)
+#define ALT_TWO_TO_POW30            (1<<30)
+#define ALT_TWO_TO_POW31            (1<<31)
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __HWLIB_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h
new file mode 100644
index 0000000..3a6bf0f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h
@@ -0,0 +1,3569 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_ACPIDMAP */
+
+#ifndef __ALTERA_ALT_ACPIDMAP_H__
+#define __ALTERA_ALT_ACPIDMAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : ACP ID Mapper Registers - ALT_ACPIDMAP
+ * ACP ID Mapper Registers
+ * 
+ * Registers in the ACP ID Mapper module
+ * 
+ */
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                 
+ * :--------|:-------|:------|:-----------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*                 
+ *  [8:4]   | RW     | 0x1   | ARUSER value to SCU for ID=2
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*                 
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder     
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*                 
+ *  [27:16] | RW     | 0x4   | Remap Master ID = DAP ID    
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*                 
+ *  [31]    | RW     | 0x1   | Force Mapping for ID=2      
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU for ID=2 - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_RESET      0x4
+/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID2RD.
+ */
+struct ALT_ACPIDMAP_VID2RD_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* ARUSER value to SCU for ID=2 */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID = DAP ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping for ID=2 */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */
+typedef volatile struct ALT_ACPIDMAP_VID2RD_s  ALT_ACPIDMAP_VID2RD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2RD_OFST        0x0
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                 
+ * :--------|:-------|:------|:-----------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*                 
+ *  [8:4]   | RW     | 0x1   | AWUSER value to SCU for ID=2
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*                 
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder     
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*                 
+ *  [27:16] | RW     | 0x4   | Remap Master ID = DAP ID    
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*                 
+ *  [31]    | RW     | 0x1   | Force Mapping for ID=2      
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU for ID=2 - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_RESET      0x4
+/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID2WR.
+ */
+struct ALT_ACPIDMAP_VID2WR_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* AWUSER value to SCU for ID=2 */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID = DAP ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping for ID=2 */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */
+typedef volatile struct ALT_ACPIDMAP_VID2WR_s  ALT_ACPIDMAP_VID2WR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2WR_OFST        0x4
+
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | ARUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID3RD.
+ */
+struct ALT_ACPIDMAP_VID3RD_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* ARUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */
+typedef volatile struct ALT_ACPIDMAP_VID3RD_s  ALT_ACPIDMAP_VID3RD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID3RD_OFST        0x8
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | AWUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */
+#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */
+#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */
+#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */
+#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID3WR.
+ */
+struct ALT_ACPIDMAP_VID3WR_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* AWUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */
+typedef volatile struct ALT_ACPIDMAP_VID3WR_s  ALT_ACPIDMAP_VID3WR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID3WR_OFST        0xc
+
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | ARUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */
+#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */
+#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */
+#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */
+#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID4RD.
+ */
+struct ALT_ACPIDMAP_VID4RD_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* ARUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */
+typedef volatile struct ALT_ACPIDMAP_VID4RD_s  ALT_ACPIDMAP_VID4RD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID4RD_OFST        0x10
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | AWUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */
+#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */
+#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */
+#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */
+#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID4WR.
+ */
+struct ALT_ACPIDMAP_VID4WR_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* AWUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */
+typedef volatile struct ALT_ACPIDMAP_VID4WR_s  ALT_ACPIDMAP_VID4WR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID4WR_OFST        0x14
+
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | ARUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */
+#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */
+#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */
+#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */
+#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID5RD.
+ */
+struct ALT_ACPIDMAP_VID5RD_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* ARUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */
+typedef volatile struct ALT_ACPIDMAP_VID5RD_s  ALT_ACPIDMAP_VID5RD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID5RD_OFST        0x18
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | AWUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */
+#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */
+#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */
+#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */
+#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID5WR.
+ */
+struct ALT_ACPIDMAP_VID5WR_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* AWUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */
+typedef volatile struct ALT_ACPIDMAP_VID5WR_s  ALT_ACPIDMAP_VID5WR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID5WR_OFST        0x1c
+
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | ARUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */
+#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */
+#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */
+#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */
+#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID6RD.
+ */
+struct ALT_ACPIDMAP_VID6RD_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* ARUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */
+typedef volatile struct ALT_ACPIDMAP_VID6RD_s  ALT_ACPIDMAP_VID6RD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID6RD_OFST        0x20
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | AWUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder
+ *  [15:14] | ???    | 0x0   | *UNDEFINED*            
+ *  [27:16] | RW     | 0x0   | Remap Master ID        
+ *  [30:28] | ???    | 0x0   | *UNDEFINED*            
+ *  [31]    | RW     | 0x0   | Force Mapping          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */
+#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */
+#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */
+#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */
+#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID6WR.
+ */
+struct ALT_ACPIDMAP_VID6WR_s
+{
+    uint32_t        :  4;  /* *UNDEFINED* */
+    uint32_t  user  :  5;  /* AWUSER value to SCU */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t        :  2;  /* *UNDEFINED* */
+    uint32_t  mid   : 12;  /* Remap Master ID */
+    uint32_t        :  3;  /* *UNDEFINED* */
+    uint32_t  force :  1;  /* Force Mapping */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */
+typedef volatile struct ALT_ACPIDMAP_VID6WR_s  ALT_ACPIDMAP_VID6WR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID6WR_OFST        0x24
+
+/*
+ * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd
+ * 
+ * The Read AXI Master Mapping Register contains the USER, and ADDR page signals
+ * mapping values for transaction that dynamically remapped to one of the available
+ * 3-bit virtual IDs.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | ARUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | ARADDR 1GB Page Decoder
+ *  [31:14] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */
+#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */
+#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */
+#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_DYNRD.
+ */
+struct ALT_ACPIDMAP_DYNRD_s
+{
+    uint32_t       :  4;  /* *UNDEFINED* */
+    uint32_t  user :  5;  /* ARUSER value to SCU */
+    uint32_t       :  3;  /* *UNDEFINED* */
+    uint32_t  page :  2;  /* ARADDR 1GB Page Decoder */
+    uint32_t       : 18;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */
+typedef volatile struct ALT_ACPIDMAP_DYNRD_s  ALT_ACPIDMAP_DYNRD_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */
+#define ALT_ACPIDMAP_DYNRD_OFST        0x28
+
+/*
+ * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr
+ * 
+ * The Write AXI Master Mapping Register contains the USER, and ADDR page signals
+ * mapping values for transaction that dynamically remapped to one of the available
+ * 3-bit virtual IDs.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description            
+ * :--------|:-------|:------|:------------------------
+ *  [3:0]   | ???    | 0x0   | *UNDEFINED*            
+ *  [8:4]   | RW     | 0x0   | AWUSER value to SCU    
+ *  [11:9]  | ???    | 0x0   | *UNDEFINED*            
+ *  [13:12] | RW     | 0x0   | AWADDR 1GB Page Decoder
+ *  [31:14] | ???    | 0x0   | *UNDEFINED*            
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */
+#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */
+#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */
+#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_DYNWR.
+ */
+struct ALT_ACPIDMAP_DYNWR_s
+{
+    uint32_t       :  4;  /* *UNDEFINED* */
+    uint32_t  user :  5;  /* AWUSER value to SCU */
+    uint32_t       :  3;  /* *UNDEFINED* */
+    uint32_t  page :  2;  /* AWADDR 1GB Page Decoder */
+    uint32_t       : 18;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */
+typedef volatile struct ALT_ACPIDMAP_DYNWR_s  ALT_ACPIDMAP_DYNWR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */
+#define ALT_ACPIDMAP_DYNWR_OFST        0x2c
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                          
+ * :--------|:-------|:--------|:--------------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                          
+ *  [8:4]   | R      | 0x1     | ARUSER value to SCU for ID=2 (Status)
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                          
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)     
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                          
+ *  [27:16] | R      | 0x4     | Remap Master ID = DAP ID (Status)    
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                          
+ *  [31]    | R      | 0x1     | Force Mapping for ID=2 (Status)      
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU for ID=2 (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_RESET      0x4
+/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID2RD_S.
+ */
+struct ALT_ACPIDMAP_VID2RD_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* ARUSER value to SCU for ID=2 (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID = DAP ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping for ID=2 (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */
+typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s  ALT_ACPIDMAP_VID2RD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2RD_S_OFST        0x30
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                          
+ * :--------|:-------|:--------|:--------------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                          
+ *  [8:4]   | R      | 0x1     | AWUSER value to SCU for ID=2 (Status)
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                          
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)     
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                          
+ *  [27:16] | R      | 0x4     | Remap Master ID = DAP ID (Status)    
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                          
+ *  [31]    | R      | 0x1     | Force Mapping for ID=2 (Status)      
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU for ID=2 (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_RESET      0x4
+/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET      0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID2WR_S.
+ */
+struct ALT_ACPIDMAP_VID2WR_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* AWUSER value to SCU for ID=2 (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID = DAP ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping for ID=2 (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */
+typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s  ALT_ACPIDMAP_VID2WR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2WR_S_OFST        0x34
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | ARUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID3RD_S.
+ */
+struct ALT_ACPIDMAP_VID3RD_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* ARUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */
+typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s  ALT_ACPIDMAP_VID3RD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID3RD_S_OFST        0x38
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | AWUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID3WR_S.
+ */
+struct ALT_ACPIDMAP_VID3WR_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* AWUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */
+typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s  ALT_ACPIDMAP_VID3WR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID3WR_S_OFST        0x3c
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | ARUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID4RD_S.
+ */
+struct ALT_ACPIDMAP_VID4RD_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* ARUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */
+typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s  ALT_ACPIDMAP_VID4RD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID4RD_S_OFST        0x40
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | AWUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID4WR_S.
+ */
+struct ALT_ACPIDMAP_VID4WR_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* AWUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */
+typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s  ALT_ACPIDMAP_VID4WR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID4WR_S_OFST        0x44
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | ARUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID5RD_S.
+ */
+struct ALT_ACPIDMAP_VID5RD_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* ARUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */
+typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s  ALT_ACPIDMAP_VID5RD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID5RD_S_OFST        0x48
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | AWUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID5WR_S.
+ */
+struct ALT_ACPIDMAP_VID5WR_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* AWUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */
+typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s  ALT_ACPIDMAP_VID5WR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID5WR_S_OFST        0x4c
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | ARUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID6RD_S.
+ */
+struct ALT_ACPIDMAP_VID6RD_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* ARUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */
+typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s  ALT_ACPIDMAP_VID6RD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID6RD_S_OFST        0x50
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, ADDR
+ * page, and ID signals mapping values for particular transaction with 12-bit ID
+ * which locks the fixed 3-bit virtual ID.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | AWUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)
+ *  [15:14] | ???    | 0x0     | *UNDEFINED*                     
+ *  [27:16] | R      | Unknown | Remap Master ID (Status)        
+ *  [30:28] | ???    | 0x0     | *UNDEFINED*                     
+ *  [31]    | R      | Unknown | Force Mapping (Status)          
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID (Status) - mid
+ * 
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_MSB        27
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH      12
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK    0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK    0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping (Status) - force
+ * 
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB        31
+/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH      1
+/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK    0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_VID6WR_S.
+ */
+struct ALT_ACPIDMAP_VID6WR_S_s
+{
+    uint32_t              :  4;  /* *UNDEFINED* */
+    const uint32_t  user  :  5;  /* AWUSER value to SCU (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  page  :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t              :  2;  /* *UNDEFINED* */
+    const uint32_t  mid   : 12;  /* Remap Master ID (Status) */
+    uint32_t              :  3;  /* *UNDEFINED* */
+    const uint32_t  force :  1;  /* Force Mapping (Status) */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */
+typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s  ALT_ACPIDMAP_VID6WR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID6WR_S_OFST        0x54
+
+/*
+ * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s
+ * 
+ * The Read AXI Master Mapping Status Register contains the configured USER, and
+ * ADDR page signals mapping values for transaction that dynamically remapped to
+ * one of the available 3-bit virtual IDs.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | ARUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | ARADDR 1GB Page Decoder (Status)
+ *  [31:14] | ???    | 0x0     | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : ARUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as ARUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder (Status) - page
+ * 
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_DYNRD_S.
+ */
+struct ALT_ACPIDMAP_DYNRD_S_s
+{
+    uint32_t             :  4;  /* *UNDEFINED* */
+    const uint32_t  user :  5;  /* ARUSER value to SCU (Status) */
+    uint32_t             :  3;  /* *UNDEFINED* */
+    const uint32_t  page :  2;  /* ARADDR 1GB Page Decoder (Status) */
+    uint32_t             : 18;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */
+typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s  ALT_ACPIDMAP_DYNRD_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_DYNRD_S_OFST        0x58
+
+/*
+ * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s
+ * 
+ * The Write AXI Master Mapping Status Register contains the configured USER, and
+ * ADDR page signals mapping values for transaction that dynamically remapped to
+ * one of the available 3-bit virtual IDs.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset   | Description                     
+ * :--------|:-------|:--------|:---------------------------------
+ *  [3:0]   | ???    | 0x0     | *UNDEFINED*                     
+ *  [8:4]   | R      | Unknown | AWUSER value to SCU (Status)    
+ *  [11:9]  | ???    | 0x0     | *UNDEFINED*                     
+ *  [13:12] | R      | Unknown | AWADDR 1GB Page Decoder (Status)
+ *  [31:14] | ???    | 0x0     | *UNDEFINED*                     
+ * 
+ */
+/*
+ * Field : AWUSER value to SCU (Status) - user
+ * 
+ * This value is propagated to SCU as AWUSERS.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_MSB        8
+/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH      5
+/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK    0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK    0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder (Status) - page
+ * 
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB        13
+/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH      2
+/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK    0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK    0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET      0x0
+/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_ACPIDMAP_DYNWR_S.
+ */
+struct ALT_ACPIDMAP_DYNWR_S_s
+{
+    uint32_t             :  4;  /* *UNDEFINED* */
+    const uint32_t  user :  5;  /* AWUSER value to SCU (Status) */
+    uint32_t             :  3;  /* *UNDEFINED* */
+    const uint32_t  page :  2;  /* AWADDR 1GB Page Decoder (Status) */
+    uint32_t             : 18;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */
+typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s  ALT_ACPIDMAP_DYNWR_S_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */
+#define ALT_ACPIDMAP_DYNWR_S_OFST        0x5c
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_ACPIDMAP.
+ */
+struct ALT_ACPIDMAP_s
+{
+    volatile ALT_ACPIDMAP_VID2RD_t    vid2rd;                  /* ALT_ACPIDMAP_VID2RD */
+    volatile ALT_ACPIDMAP_VID2WR_t    vid2wr;                  /* ALT_ACPIDMAP_VID2WR */
+    volatile ALT_ACPIDMAP_VID3RD_t    vid3rd;                  /* ALT_ACPIDMAP_VID3RD */
+    volatile ALT_ACPIDMAP_VID3WR_t    vid3wr;                  /* ALT_ACPIDMAP_VID3WR */
+    volatile ALT_ACPIDMAP_VID4RD_t    vid4rd;                  /* ALT_ACPIDMAP_VID4RD */
+    volatile ALT_ACPIDMAP_VID4WR_t    vid4wr;                  /* ALT_ACPIDMAP_VID4WR */
+    volatile ALT_ACPIDMAP_VID5RD_t    vid5rd;                  /* ALT_ACPIDMAP_VID5RD */
+    volatile ALT_ACPIDMAP_VID5WR_t    vid5wr;                  /* ALT_ACPIDMAP_VID5WR */
+    volatile ALT_ACPIDMAP_VID6RD_t    vid6rd;                  /* ALT_ACPIDMAP_VID6RD */
+    volatile ALT_ACPIDMAP_VID6WR_t    vid6wr;                  /* ALT_ACPIDMAP_VID6WR */
+    volatile ALT_ACPIDMAP_DYNRD_t     dynrd;                   /* ALT_ACPIDMAP_DYNRD */
+    volatile ALT_ACPIDMAP_DYNWR_t     dynwr;                   /* ALT_ACPIDMAP_DYNWR */
+    volatile ALT_ACPIDMAP_VID2RD_S_t  vid2rd_s;                /* ALT_ACPIDMAP_VID2RD_S */
+    volatile ALT_ACPIDMAP_VID2WR_S_t  vid2wr_s;                /* ALT_ACPIDMAP_VID2WR_S */
+    volatile ALT_ACPIDMAP_VID3RD_S_t  vid3rd_s;                /* ALT_ACPIDMAP_VID3RD_S */
+    volatile ALT_ACPIDMAP_VID3WR_S_t  vid3wr_s;                /* ALT_ACPIDMAP_VID3WR_S */
+    volatile ALT_ACPIDMAP_VID4RD_S_t  vid4rd_s;                /* ALT_ACPIDMAP_VID4RD_S */
+    volatile ALT_ACPIDMAP_VID4WR_S_t  vid4wr_s;                /* ALT_ACPIDMAP_VID4WR_S */
+    volatile ALT_ACPIDMAP_VID5RD_S_t  vid5rd_s;                /* ALT_ACPIDMAP_VID5RD_S */
+    volatile ALT_ACPIDMAP_VID5WR_S_t  vid5wr_s;                /* ALT_ACPIDMAP_VID5WR_S */
+    volatile ALT_ACPIDMAP_VID6RD_S_t  vid6rd_s;                /* ALT_ACPIDMAP_VID6RD_S */
+    volatile ALT_ACPIDMAP_VID6WR_S_t  vid6wr_s;                /* ALT_ACPIDMAP_VID6WR_S */
+    volatile ALT_ACPIDMAP_DYNRD_S_t   dynrd_s;                 /* ALT_ACPIDMAP_DYNRD_S */
+    volatile ALT_ACPIDMAP_DYNWR_S_t   dynwr_s;                 /* ALT_ACPIDMAP_DYNWR_S */
+    volatile uint32_t                 _pad_0x60_0x1000[1000];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register group ALT_ACPIDMAP. */
+typedef volatile struct ALT_ACPIDMAP_s  ALT_ACPIDMAP_t;
+/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */
+struct ALT_ACPIDMAP_raw_s
+{
+    volatile uint32_t  vid2rd;                  /* ALT_ACPIDMAP_VID2RD */
+    volatile uint32_t  vid2wr;                  /* ALT_ACPIDMAP_VID2WR */
+    volatile uint32_t  vid3rd;                  /* ALT_ACPIDMAP_VID3RD */
+    volatile uint32_t  vid3wr;                  /* ALT_ACPIDMAP_VID3WR */
+    volatile uint32_t  vid4rd;                  /* ALT_ACPIDMAP_VID4RD */
+    volatile uint32_t  vid4wr;                  /* ALT_ACPIDMAP_VID4WR */
+    volatile uint32_t  vid5rd;                  /* ALT_ACPIDMAP_VID5RD */
+    volatile uint32_t  vid5wr;                  /* ALT_ACPIDMAP_VID5WR */
+    volatile uint32_t  vid6rd;                  /* ALT_ACPIDMAP_VID6RD */
+    volatile uint32_t  vid6wr;                  /* ALT_ACPIDMAP_VID6WR */
+    volatile uint32_t  dynrd;                   /* ALT_ACPIDMAP_DYNRD */
+    volatile uint32_t  dynwr;                   /* ALT_ACPIDMAP_DYNWR */
+    volatile uint32_t  vid2rd_s;                /* ALT_ACPIDMAP_VID2RD_S */
+    volatile uint32_t  vid2wr_s;                /* ALT_ACPIDMAP_VID2WR_S */
+    volatile uint32_t  vid3rd_s;                /* ALT_ACPIDMAP_VID3RD_S */
+    volatile uint32_t  vid3wr_s;                /* ALT_ACPIDMAP_VID3WR_S */
+    volatile uint32_t  vid4rd_s;                /* ALT_ACPIDMAP_VID4RD_S */
+    volatile uint32_t  vid4wr_s;                /* ALT_ACPIDMAP_VID4WR_S */
+    volatile uint32_t  vid5rd_s;                /* ALT_ACPIDMAP_VID5RD_S */
+    volatile uint32_t  vid5wr_s;                /* ALT_ACPIDMAP_VID5WR_S */
+    volatile uint32_t  vid6rd_s;                /* ALT_ACPIDMAP_VID6RD_S */
+    volatile uint32_t  vid6wr_s;                /* ALT_ACPIDMAP_VID6WR_S */
+    volatile uint32_t  dynrd_s;                 /* ALT_ACPIDMAP_DYNRD_S */
+    volatile uint32_t  dynwr_s;                 /* ALT_ACPIDMAP_DYNWR_S */
+    volatile uint32_t  _pad_0x60_0x1000[1000];  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */
+typedef volatile struct ALT_ACPIDMAP_raw_s  ALT_ACPIDMAP_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+#endif  /* __ALTERA_ALT_ACPIDMAP_H__ */
+
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_can.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_can.h
new file mode 100644
index 0000000..861efa1
--- /dev/null
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_can.h
@@ -0,0 +1,36873 @@
+/*******************************************************************************
+*                                                                              *
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
+*                                                                              *
+* Redistribution and use in source and binary forms, with or without           *
+* modification, are permitted provided that the following conditions are met:  *
+*                                                                              *
+* 1. Redistributions of source code must retain the above copyright notice,    *
+*    this list of conditions and the following disclaimer.                     *
+*                                                                              *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+*    this list of conditions and the following disclaimer in the documentation *
+*    and/or other materials provided with the distribution.                    *
+*                                                                              *
+* 3. The name of the author may not be used to endorse or promote products     *
+*    derived from this software without specific prior written permission.     *
+*                                                                              *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
+*                                                                              *
+*******************************************************************************/
+
+/* Altera - ALT_CAN */
+
+#ifndef __ALTERA_ALT_CAN_H__
+#define __ALTERA_ALT_CAN_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/*
+ * Component : CAN Controller Module - ALT_CAN
+ * CAN Controller Module
+ * 
+ * Registers in the CAN Controller module
+ * 
+ */
+/*
+ * Register Group : Protocol Group - ALT_CAN_PROTO
+ * Protocol Group
+ * 
+ * These registers are related to the CAN protocol controller in the CAN Core. They
+ * control the operating modes and the configuration of the CAN bit timing and
+ * provide status information.
+ * 
+ */
+/*
+ * Register : Control Register - CCTRL
+ * 
+ * Control Register
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                         
+ * :--------|:-------|:------|:-------------------------------------
+ *  [0]     | RW     | 0x1   | Initialization                      
+ *  [1]     | RW     | 0x0   | Module Interrupt Line Enable        
+ *  [2]     | RW     | 0x0   | Status Interrupt Enable             
+ *  [3]     | RW     | 0x0   | Error Interrupt Enable              
+ *  [4]     | ???    | 0x0   | *UNDEFINED*                         
+ *  [5]     | RW     | 0x0   | Disable Automatic Retransmission    
+ *  [6]     | RW     | 0x0   | Configuration Change Enable         
+ *  [7]     | RW     | 0x0   | Test Mode Enable                    
+ *  [16:8]  | ???    | 0x0   | *UNDEFINED*                         
+ *  [17]    | RW     | 0x0   | Message Object Interrupt Line Enable
+ *  [18]    | RW     | 0x0   | DMA Enable for IF1                  
+ *  [19]    | RW     | 0x0   | DMA Enable for IF2                  
+ *  [31:20] | ???    | 0x0   | *UNDEFINED*                         
+ * 
+ */
+/*
+ * Field : Initialization - Init
+ * 
+ * Initialization
+ * 
+ * Note: Due to the synchronization mechanism between the two clock domains, there
+ * may be a delay until the value written to CCTRL.Init can be read back. Therefore
+ * the programmer has to assure that the previous value written to CCTRL.Init has
+ * been accepted by reading CCTRL.Init before setting CCTRL.Init to a new value.\n
+ * 
+ * Note: The Bus_Off recovery sequence (see CAN Specification Rev. 2.0) cannot be
+ * shortened by setting or resetting CCTRL.Init. If the device goes Bus_Off, it
+ * will set CCTRL.Init of its own accord, stopping all bus activities. Once
+ * CCTRL.Init has been cleared by the CPU, the device will then wait for 129
+ * occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming
+ * normal operations. At the end of the Bus_Off recovery sequence, the Error
+ * Management Counters will be reset. During the waiting time after the resetting
+ * of CCTRL.Init, each time a sequence of 11 recessive bits has been monitored, a
+ * Bit0Error code is written to the Status Register, enabling the CPU to readily
+ * check up whether the CAN bus is stuck at dominant or continuously disturbed and
+ * to monitor the proceeding of the us_Off recovery sequence.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description               
+ * :---------------------------------|:------|:---------------------------
+ *  ALT_CAN_PROTO_CCTL_INIT_E_NORMAL | 0x0   | Normal Operation.         
+ *  ALT_CAN_PROTO_CCTL_INIT_E_START  | 0x1   | Initialization is started.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_INIT
+ * 
+ * Normal Operation.
+ */
+#define ALT_CAN_PROTO_CCTL_INIT_E_NORMAL    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_INIT
+ * 
+ * Initialization is started.
+ */
+#define ALT_CAN_PROTO_CCTL_INIT_E_START     0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_INIT register field. */
+#define ALT_CAN_PROTO_CCTL_INIT_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_INIT register field. */
+#define ALT_CAN_PROTO_CCTL_INIT_MSB        0
+/* The width in bits of the ALT_CAN_PROTO_CCTL_INIT register field. */
+#define ALT_CAN_PROTO_CCTL_INIT_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_INIT register field value. */
+#define ALT_CAN_PROTO_CCTL_INIT_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_INIT register field value. */
+#define ALT_CAN_PROTO_CCTL_INIT_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_PROTO_CCTL_INIT register field. */
+#define ALT_CAN_PROTO_CCTL_INIT_RESET      0x1
+/* Extracts the ALT_CAN_PROTO_CCTL_INIT field value from a register. */
+#define ALT_CAN_PROTO_CCTL_INIT_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_PROTO_CCTL_INIT register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_INIT_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Module Interrupt Line Enable - ILE
+ * 
+ * Module Interrupt Line Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                    
+ * :------------------------------|:------|:------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_ILE_E_DISD | 0x0   | Module Interrupt Line CAN_INT_STATUS is always 
+ * :                              |       | LOW.                                           
+ *  ALT_CAN_PROTO_CCTL_ILE_E_END  | 0x1   | Error and status interrupts (if CCTRL.EIE=1 and
+ * :                              |       | CCTRL.SIE=1) will set line CAN_INT_STATUS to   
+ * :                              |       | one, signal remains one until all pending      
+ * :                              |       | interrupts are processed. If MIL is disabled,  
+ * :                              |       | the message object interrupts will also affect 
+ * :                              |       | this interrupt line.                           
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_ILE
+ * 
+ * Module Interrupt Line CAN_INT_STATUS is always LOW.
+ */
+#define ALT_CAN_PROTO_CCTL_ILE_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_ILE
+ * 
+ * Error and status interrupts (if CCTRL.EIE=1 and CCTRL.SIE=1) will set line
+ * CAN_INT_STATUS to one, signal remains one until all pending interrupts are
+ * processed. If MIL is disabled, the message object interrupts will also affect
+ * this interrupt line.
+ */
+#define ALT_CAN_PROTO_CCTL_ILE_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_ILE register field. */
+#define ALT_CAN_PROTO_CCTL_ILE_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_ILE register field. */
+#define ALT_CAN_PROTO_CCTL_ILE_MSB        1
+/* The width in bits of the ALT_CAN_PROTO_CCTL_ILE register field. */
+#define ALT_CAN_PROTO_CCTL_ILE_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_ILE register field value. */
+#define ALT_CAN_PROTO_CCTL_ILE_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_ILE register field value. */
+#define ALT_CAN_PROTO_CCTL_ILE_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_PROTO_CCTL_ILE register field. */
+#define ALT_CAN_PROTO_CCTL_ILE_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_ILE field value from a register. */
+#define ALT_CAN_PROTO_CCTL_ILE_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_PROTO_CCTL_ILE register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_ILE_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Status Interrupt Enable - SIE
+ * 
+ * Status Interrupt Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                     
+ * :------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_SIE_E_DISD | 0x0   | CSTS.RxOk, CSTS.TxOk and CSTS.LEC will still be 
+ * :                              |       | updated, but without affecting interrupt line   
+ * :                              |       | CAN_INT_STATUS and Interrupt register CIR.      
+ *  ALT_CAN_PROTO_CCTL_SIE_E_END  | 0x1   | When a message transfer is successfully         
+ * :                              |       | completed or a CAN bus error is detected,       
+ * :                              |       | indicated by flags CSTS.RxOk, CSTS.TxOk and     
+ * :                              |       | CSTS.LEC, the interrupt line CAN_INT_STATUS gets
+ * :                              |       | active (if ILE=1) and CIR.StatusInt is set.     
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_SIE
+ * 
+ * CSTS.RxOk, CSTS.TxOk and CSTS.LEC will still be updated, but without affecting
+ * interrupt line CAN_INT_STATUS and Interrupt register CIR.
+ */
+#define ALT_CAN_PROTO_CCTL_SIE_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_SIE
+ * 
+ * When a message transfer is successfully completed or a CAN bus error is
+ * detected, indicated by flags CSTS.RxOk, CSTS.TxOk and CSTS.LEC, the interrupt
+ * line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set.
+ */
+#define ALT_CAN_PROTO_CCTL_SIE_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_SIE register field. */
+#define ALT_CAN_PROTO_CCTL_SIE_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_SIE register field. */
+#define ALT_CAN_PROTO_CCTL_SIE_MSB        2
+/* The width in bits of the ALT_CAN_PROTO_CCTL_SIE register field. */
+#define ALT_CAN_PROTO_CCTL_SIE_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_SIE register field value. */
+#define ALT_CAN_PROTO_CCTL_SIE_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_SIE register field value. */
+#define ALT_CAN_PROTO_CCTL_SIE_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_PROTO_CCTL_SIE register field. */
+#define ALT_CAN_PROTO_CCTL_SIE_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_SIE field value from a register. */
+#define ALT_CAN_PROTO_CCTL_SIE_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_PROTO_CCTL_SIE register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_SIE_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : Error Interrupt Enable - EIE
+ * 
+ * Error Interrupt Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                  
+ * :------------------------------|:------|:----------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_EIE_E_DISD | 0x0   | CSTS.PER, CSTS.BOff and CSTS.EWarn flags will
+ * :                              |       | still be updated, but without affecting      
+ * :                              |       | interrupt line CAN_INT_STATUS and Interrupt  
+ * :                              |       | register CIR                                 
+ *  ALT_CAN_PROTO_CCTL_EIE_E_END  | 0x1   | If CSTS.PER flag is one, or CSTS.BOff or     
+ * :                              |       | CSTS.EWarn are changed, the interrupt line   
+ * :                              |       | CAN_INT_STATUS gets active (if ILE=1) and    
+ * :                              |       | CIR.StatusInt is set.                        
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_EIE
+ * 
+ * CSTS.PER, CSTS.BOff and CSTS.EWarn flags will still be updated, but without
+ * affecting interrupt line CAN_INT_STATUS and Interrupt register CIR
+ */
+#define ALT_CAN_PROTO_CCTL_EIE_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_EIE
+ * 
+ * If CSTS.PER flag is one, or CSTS.BOff or CSTS.EWarn are changed, the interrupt
+ * line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set.
+ */
+#define ALT_CAN_PROTO_CCTL_EIE_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_EIE register field. */
+#define ALT_CAN_PROTO_CCTL_EIE_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_EIE register field. */
+#define ALT_CAN_PROTO_CCTL_EIE_MSB        3
+/* The width in bits of the ALT_CAN_PROTO_CCTL_EIE register field. */
+#define ALT_CAN_PROTO_CCTL_EIE_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_EIE register field value. */
+#define ALT_CAN_PROTO_CCTL_EIE_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_EIE register field value. */
+#define ALT_CAN_PROTO_CCTL_EIE_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_PROTO_CCTL_EIE register field. */
+#define ALT_CAN_PROTO_CCTL_EIE_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_EIE field value from a register. */
+#define ALT_CAN_PROTO_CCTL_EIE_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_PROTO_CCTL_EIE register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_EIE_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Disable Automatic Retransmission - DAR
+ * 
+ * Disable Automatic Retransmission
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                               
+ * :------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_DAR_E_END  | 0x0   | Automatic Retransmission of not successful
+ * :                              |       | messages enabled.                         
+ *  ALT_CAN_PROTO_CCTL_DAR_E_DISD | 0x1   | Automatic Retransmission disabled.        
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DAR
+ * 
+ * Automatic Retransmission of not successful messages enabled.
+ */
+#define ALT_CAN_PROTO_CCTL_DAR_E_END    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DAR
+ * 
+ * Automatic Retransmission disabled.
+ */
+#define ALT_CAN_PROTO_CCTL_DAR_E_DISD   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DAR register field. */
+#define ALT_CAN_PROTO_CCTL_DAR_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DAR register field. */
+#define ALT_CAN_PROTO_CCTL_DAR_MSB        5
+/* The width in bits of the ALT_CAN_PROTO_CCTL_DAR register field. */
+#define ALT_CAN_PROTO_CCTL_DAR_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_DAR register field value. */
+#define ALT_CAN_PROTO_CCTL_DAR_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_DAR register field value. */
+#define ALT_CAN_PROTO_CCTL_DAR_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_PROTO_CCTL_DAR register field. */
+#define ALT_CAN_PROTO_CCTL_DAR_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_DAR field value from a register. */
+#define ALT_CAN_PROTO_CCTL_DAR_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_PROTO_CCTL_DAR register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_DAR_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : Configuration Change Enable - CCE
+ * 
+ * Configuration Change Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                     
+ * :---------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_CCE_E_NOWRACC | 0x0   | The CPU has no write access to the configuration
+ * :                                 |       | registers.                                      
+ *  ALT_CAN_PROTO_CCTL_CCE_E_WRACC   | 0x1   | The CPU has write access to the Bit Timing      
+ * :                                 |       | Register CBT (while CCTRL.Init = 1).            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_CCE
+ * 
+ * The CPU has no write access to the configuration registers.
+ */
+#define ALT_CAN_PROTO_CCTL_CCE_E_NOWRACC    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_CCE
+ * 
+ * The CPU has write access to the Bit Timing Register CBT (while CCTRL.Init = 1).
+ */
+#define ALT_CAN_PROTO_CCTL_CCE_E_WRACC      0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_CCE register field. */
+#define ALT_CAN_PROTO_CCTL_CCE_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_CCE register field. */
+#define ALT_CAN_PROTO_CCTL_CCE_MSB        6
+/* The width in bits of the ALT_CAN_PROTO_CCTL_CCE register field. */
+#define ALT_CAN_PROTO_CCTL_CCE_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_CCE register field value. */
+#define ALT_CAN_PROTO_CCTL_CCE_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_CCE register field value. */
+#define ALT_CAN_PROTO_CCTL_CCE_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_PROTO_CCTL_CCE register field. */
+#define ALT_CAN_PROTO_CCTL_CCE_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_CCE field value from a register. */
+#define ALT_CAN_PROTO_CCTL_CCE_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_PROTO_CCTL_CCE register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_CCE_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : Test Mode Enable - Test
+ * 
+ * Test Mode Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description                                
+ * :----------------------------------|:------|:--------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_TEST_E_DISD    | 0x0   | Normal Operation.                          
+ *  ALT_CAN_PROTO_CCTL_TEST_E_TESTMOD | 0x1   | Test Mode. Enables the write access to Test
+ * :                                  |       | Register CTR.                              
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_TEST
+ * 
+ * Normal Operation.
+ */
+#define ALT_CAN_PROTO_CCTL_TEST_E_DISD      0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_TEST
+ * 
+ * Test Mode. Enables the write access to Test Register CTR.
+ */
+#define ALT_CAN_PROTO_CCTL_TEST_E_TESTMOD   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_TEST register field. */
+#define ALT_CAN_PROTO_CCTL_TEST_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_TEST register field. */
+#define ALT_CAN_PROTO_CCTL_TEST_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CCTL_TEST register field. */
+#define ALT_CAN_PROTO_CCTL_TEST_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_TEST register field value. */
+#define ALT_CAN_PROTO_CCTL_TEST_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_TEST register field value. */
+#define ALT_CAN_PROTO_CCTL_TEST_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_PROTO_CCTL_TEST register field. */
+#define ALT_CAN_PROTO_CCTL_TEST_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_TEST field value from a register. */
+#define ALT_CAN_PROTO_CCTL_TEST_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_PROTO_CCTL_TEST register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_TEST_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : Message Object Interrupt Line Enable - MIL
+ * 
+ * Message Object Interrupt Line Enable
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                     
+ * :------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_MIL_E_DISD | 0x0   | Message Object Interrupt CAN_INT_MO is always   
+ * :                              |       | LOW. If CCTRL.ILE is enabled all message object 
+ * :                              |       | interrupts are routed to line CAN_INT_STATUS    
+ * :                              |       | otherwise no message object interrupt will be   
+ * :                              |       | visible.                                        
+ *  ALT_CAN_PROTO_CCTL_MIL_E_END  | 0x1   | Message object interrupts will set CAN_INT_MO to
+ * :                              |       | one, signal remains one until all pending       
+ * :                              |       | interrupts are processed.                       
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_MIL
+ * 
+ * Message Object Interrupt CAN_INT_MO is always LOW. If CCTRL.ILE is enabled all
+ * message object interrupts are routed to line CAN_INT_STATUS otherwise no message
+ * object interrupt will be visible.
+ */
+#define ALT_CAN_PROTO_CCTL_MIL_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_MIL
+ * 
+ * Message object interrupts will set CAN_INT_MO to one, signal remains one until
+ * all pending interrupts are processed.
+ */
+#define ALT_CAN_PROTO_CCTL_MIL_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_MIL register field. */
+#define ALT_CAN_PROTO_CCTL_MIL_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_MIL register field. */
+#define ALT_CAN_PROTO_CCTL_MIL_MSB        17
+/* The width in bits of the ALT_CAN_PROTO_CCTL_MIL register field. */
+#define ALT_CAN_PROTO_CCTL_MIL_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_MIL register field value. */
+#define ALT_CAN_PROTO_CCTL_MIL_SET_MSK    0x00020000
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_MIL register field value. */
+#define ALT_CAN_PROTO_CCTL_MIL_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_CAN_PROTO_CCTL_MIL register field. */
+#define ALT_CAN_PROTO_CCTL_MIL_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_MIL field value from a register. */
+#define ALT_CAN_PROTO_CCTL_MIL_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_CAN_PROTO_CCTL_MIL register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_MIL_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : DMA Enable for IF1 - DE1
+ * 
+ * DMA Enable for IF1
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                     
+ * :------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_DE1_E_DISD | 0x0   | Module DMA output port CAN_IF1DMA is always LOW.
+ *  ALT_CAN_PROTO_CCTL_DE1_E_END  | 0x1   | Requesting a message object transfer from IF1 to
+ * :                              |       | Message RAM or vice versa with IF1CMR.DMAactive 
+ * :                              |       | enabled the end of the transfer will be marked  
+ * :                              |       | with setting port CAN_IF1DMA to one. The port   
+ * :                              |       | remains one until first access to one of the IF1
+ * :                              |       | registers.                                      
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE1
+ * 
+ * Module DMA output port CAN_IF1DMA is always LOW.
+ */
+#define ALT_CAN_PROTO_CCTL_DE1_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE1
+ * 
+ * Requesting a message object transfer from IF1 to Message RAM or vice versa with
+ * IF1CMR.DMAactive enabled the end of the transfer will be marked with setting
+ * port CAN_IF1DMA to one. The port remains one until first access to one of the
+ * IF1 registers.
+ */
+#define ALT_CAN_PROTO_CCTL_DE1_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DE1 register field. */
+#define ALT_CAN_PROTO_CCTL_DE1_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DE1 register field. */
+#define ALT_CAN_PROTO_CCTL_DE1_MSB        18
+/* The width in bits of the ALT_CAN_PROTO_CCTL_DE1 register field. */
+#define ALT_CAN_PROTO_CCTL_DE1_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_DE1 register field value. */
+#define ALT_CAN_PROTO_CCTL_DE1_SET_MSK    0x00040000
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_DE1 register field value. */
+#define ALT_CAN_PROTO_CCTL_DE1_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_CAN_PROTO_CCTL_DE1 register field. */
+#define ALT_CAN_PROTO_CCTL_DE1_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_DE1 field value from a register. */
+#define ALT_CAN_PROTO_CCTL_DE1_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_CAN_PROTO_CCTL_DE1 register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_DE1_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : DMA Enable for IF2 - DE2
+ * 
+ * DMA Enable for IF2
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                          | Value | Description                                     
+ * :------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CCTL_DE2_E_DISD | 0x0   | Module DMA output port CAN_IF2DMA is always LOW.
+ *  ALT_CAN_PROTO_CCTL_DE2_E_END  | 0x1   | Requesting a message object transfer from IF2 to
+ * :                              |       | Message RAM or vice versa with IF2CMR.DMAactive 
+ * :                              |       | enabled the end of the transfer will be marked  
+ * :                              |       | with setting port CAN_IF2DMA to one. The port   
+ * :                              |       | remains one until first access to one of the IF2
+ * :                              |       | registers.                                      
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE2
+ * 
+ * Module DMA output port CAN_IF2DMA is always LOW.
+ */
+#define ALT_CAN_PROTO_CCTL_DE2_E_DISD   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE2
+ * 
+ * Requesting a message object transfer from IF2 to Message RAM or vice versa with
+ * IF2CMR.DMAactive enabled the end of the transfer will be marked with setting
+ * port CAN_IF2DMA to one. The port remains one until first access to one of the
+ * IF2 registers.
+ */
+#define ALT_CAN_PROTO_CCTL_DE2_E_END    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DE2 register field. */
+#define ALT_CAN_PROTO_CCTL_DE2_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DE2 register field. */
+#define ALT_CAN_PROTO_CCTL_DE2_MSB        19
+/* The width in bits of the ALT_CAN_PROTO_CCTL_DE2 register field. */
+#define ALT_CAN_PROTO_CCTL_DE2_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CCTL_DE2 register field value. */
+#define ALT_CAN_PROTO_CCTL_DE2_SET_MSK    0x00080000
+/* The mask used to clear the ALT_CAN_PROTO_CCTL_DE2 register field value. */
+#define ALT_CAN_PROTO_CCTL_DE2_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_CAN_PROTO_CCTL_DE2 register field. */
+#define ALT_CAN_PROTO_CCTL_DE2_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CCTL_DE2 field value from a register. */
+#define ALT_CAN_PROTO_CCTL_DE2_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_CAN_PROTO_CCTL_DE2 register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CCTL_DE2_SET(value) (((value) << 19) & 0x00080000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CCTL.
+ */
+struct ALT_CAN_PROTO_CCTL_s
+{
+    uint32_t  Init :  1;  /* Initialization */
+    uint32_t  ILE  :  1;  /* Module Interrupt Line Enable */
+    uint32_t  SIE  :  1;  /* Status Interrupt Enable */
+    uint32_t  EIE  :  1;  /* Error Interrupt Enable */
+    uint32_t       :  1;  /* *UNDEFINED* */
+    uint32_t  DAR  :  1;  /* Disable Automatic Retransmission */
+    uint32_t  CCE  :  1;  /* Configuration Change Enable */
+    uint32_t  Test :  1;  /* Test Mode Enable */
+    uint32_t       :  9;  /* *UNDEFINED* */
+    uint32_t  MIL  :  1;  /* Message Object Interrupt Line Enable */
+    uint32_t  DE1  :  1;  /* DMA Enable for IF1 */
+    uint32_t  DE2  :  1;  /* DMA Enable for IF2 */
+    uint32_t       : 12;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CCTL. */
+typedef volatile struct ALT_CAN_PROTO_CCTL_s  ALT_CAN_PROTO_CCTL_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CCTL register from the beginning of the component. */
+#define ALT_CAN_PROTO_CCTL_OFST        0x0
+/* The address of the ALT_CAN_PROTO_CCTL register. */
+#define ALT_CAN_PROTO_CCTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CCTL_OFST))
+
+/*
+ * Register : Status Register - CSTS
+ * 
+ * Status Register
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                       
+ * :-------|:-------|:------|:-----------------------------------
+ *  [2:0]  | R      | 0x7   | Last Error Code                   
+ *  [3]    | R      | 0x0   | Transmitted a Message Successfully
+ *  [4]    | R      | 0x0   | Received a Message Successfully   
+ *  [5]    | R      | 0x0   | Error Passive                     
+ *  [6]    | R      | 0x0   | Warning Status                    
+ *  [7]    | R      | 0x0   | Bus_Off Status                    
+ *  [8]    | R      | 0x0   | Parity Error Detected             
+ *  [31:9] | ???    | 0x0   | *UNDEFINED*                       
+ * 
+ */
+/*
+ * Field : Last Error Code - LEC
+ * 
+ * The LEC field holds a code which indicates the type of the last error to occur
+ * on the CAN bus. This field will be cleared to 0 when a message has been
+ * transferred (reception or transmission) without error.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                                     
+ * :------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_LEC_E_NOERROR    | 0x0   | Set together with CSTS.RxOK or CSTS.TxOK.       
+ *  ALT_CAN_PROTO_CSTS_LEC_E_STUFFERROR | 0x1   | More than 5 equal bits in a sequence have       
+ * :                                    |       | occurred in a part of a received message where  
+ * :                                    |       | this is not allowed.                            
+ *  ALT_CAN_PROTO_CSTS_LEC_E_FORMERROR  | 0x2   | A fixed format part of a received frame has the 
+ * :                                    |       | wrong format.                                   
+ *  ALT_CAN_PROTO_CSTS_LEC_E_ACKERROR   | 0x3   | The message this CAN Core transmitted was not   
+ * :                                    |       | acknowledged by another node.                   
+ *  ALT_CAN_PROTO_CSTS_LEC_E_BIT1ERROR  | 0x4   | During the transmission of a message (with the  
+ * :                                    |       | exception of the arbitration field), the device 
+ * :                                    |       | wanted to send a recessive level (bit of logical
+ * :                                    |       | value 1), but the monitored bus value was       
+ * :                                    |       | dominant.                                       
+ *  ALT_CAN_PROTO_CSTS_LEC_E_BIT0ERROR  | 0x5   | During the transmission of a message (or        
+ * :                                    |       | acknowledge bit, or active error flag, or       
+ * :                                    |       | overload flag), the device wanted to send a     
+ * :                                    |       | dominant level (data or identifier bit logical  
+ * :                                    |       | value 0), but the monitored bus value was       
+ * :                                    |       | recessive. During Bus_Off recovery this status  
+ * :                                    |       | is set each time a sequence of 11 recessive bits
+ * :                                    |       | has been monitored. This enables the CPU to     
+ * :                                    |       | monitor the proceeding of the Bus_Off recovery  
+ * :                                    |       | sequence (indicating the bus is not stuck at    
+ * :                                    |       | dominant or continuously disturbed).            
+ *  ALT_CAN_PROTO_CSTS_LEC_E_CRCERROR   | 0x6   | The CRC checksum was incorrect in the message   
+ * :                                    |       | received, the CRC received for an incoming      
+ * :                                    |       | message does not match with the calculated CRC  
+ * :                                    |       | for the received data.                          
+ *  ALT_CAN_PROTO_CSTS_LEC_E_NOCHANGE   | 0x7   | Any read access to the Status Register re       
+ * :                                    |       | initializes the LEC to 7. When the LEC shows the
+ * :                                    |       | value 7, no CAN bus event was detected since the
+ * :                                    |       | last CPU read access to the Status Register.    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * Set together with CSTS.RxOK or CSTS.TxOK.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_NOERROR    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * More than 5 equal bits in a sequence have occurred in a part of a received
+ * message where this is not allowed.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_STUFFERROR 0x1
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * A fixed format part of a received frame has the wrong format.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_FORMERROR  0x2
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * The message this CAN Core transmitted was not acknowledged by another node.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_ACKERROR   0x3
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * During the transmission of a message (with the exception of the arbitration
+ * field), the device wanted to send a recessive level (bit of logical value 1),
+ * but the monitored bus value was dominant.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_BIT1ERROR  0x4
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * During the transmission of a message (or acknowledge bit, or active error flag,
+ * or overload flag), the device wanted to send a dominant level (data or
+ * identifier bit logical value 0), but the monitored bus value was recessive.
+ * During Bus_Off recovery this status is set each time a sequence of 11 recessive
+ * bits has been monitored. This enables the CPU to monitor the proceeding of the
+ * Bus_Off recovery sequence (indicating the bus is not stuck at dominant or
+ * continuously disturbed).
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_BIT0ERROR  0x5
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * The CRC checksum was incorrect in the message received, the CRC received for an
+ * incoming message does not match with the calculated CRC for the received data.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_CRCERROR   0x6
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC
+ * 
+ * Any read access to the Status Register re initializes the LEC to 7. When the LEC
+ * shows the value 7, no CAN bus event was detected since the last CPU read access
+ * to the Status Register.
+ */
+#define ALT_CAN_PROTO_CSTS_LEC_E_NOCHANGE   0x7
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_LEC register field. */
+#define ALT_CAN_PROTO_CSTS_LEC_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_LEC register field. */
+#define ALT_CAN_PROTO_CSTS_LEC_MSB        2
+/* The width in bits of the ALT_CAN_PROTO_CSTS_LEC register field. */
+#define ALT_CAN_PROTO_CSTS_LEC_WIDTH      3
+/* The mask used to set the ALT_CAN_PROTO_CSTS_LEC register field value. */
+#define ALT_CAN_PROTO_CSTS_LEC_SET_MSK    0x00000007
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_LEC register field value. */
+#define ALT_CAN_PROTO_CSTS_LEC_CLR_MSK    0xfffffff8
+/* The reset value of the ALT_CAN_PROTO_CSTS_LEC register field. */
+#define ALT_CAN_PROTO_CSTS_LEC_RESET      0x7
+/* Extracts the ALT_CAN_PROTO_CSTS_LEC field value from a register. */
+#define ALT_CAN_PROTO_CSTS_LEC_GET(value) (((value) & 0x00000007) >> 0)
+/* Produces a ALT_CAN_PROTO_CSTS_LEC register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_LEC_SET(value) (((value) << 0) & 0x00000007)
+
+/*
+ * Field : Transmitted a Message Successfully - TxOK
+ * 
+ * Transmitted a Message Successfully
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                    
+ * :---------------------------------|:------|:------------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_TXOK_E_NOTXOK | 0x0   | Since this bit was last read by the CPU, no    
+ * :                                 |       | message has been successfully transmitted. This
+ * :                                 |       | bit is never reset by CAN internal events.     
+ *  ALT_CAN_PROTO_CSTS_TXOK_E_TXOK   | 0x1   | Since this bit was last reset by a read access 
+ * :                                 |       | of the CPU, a message has been successfully    
+ * :                                 |       | (error free and acknowledged by at least one   
+ * :                                 |       | other node) transmitted. This bit will be reset
+ * :                                 |       | by reading the Status Register.                
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_TXOK
+ * 
+ * Since this bit was last read by the CPU, no message has been successfully
+ * transmitted. This bit is never reset by CAN internal events.
+ */
+#define ALT_CAN_PROTO_CSTS_TXOK_E_NOTXOK    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_TXOK
+ * 
+ * Since this bit was last reset by a read access of the CPU, a message has been
+ * successfully (error free and acknowledged by at least one other node)
+ * transmitted. This bit will be reset by reading the Status Register.
+ */
+#define ALT_CAN_PROTO_CSTS_TXOK_E_TXOK      0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_TXOK register field. */
+#define ALT_CAN_PROTO_CSTS_TXOK_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_TXOK register field. */
+#define ALT_CAN_PROTO_CSTS_TXOK_MSB        3
+/* The width in bits of the ALT_CAN_PROTO_CSTS_TXOK register field. */
+#define ALT_CAN_PROTO_CSTS_TXOK_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_TXOK register field value. */
+#define ALT_CAN_PROTO_CSTS_TXOK_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_TXOK register field value. */
+#define ALT_CAN_PROTO_CSTS_TXOK_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_PROTO_CSTS_TXOK register field. */
+#define ALT_CAN_PROTO_CSTS_TXOK_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_TXOK field value from a register. */
+#define ALT_CAN_PROTO_CSTS_TXOK_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_PROTO_CSTS_TXOK register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_TXOK_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Received a Message Successfully - RxOK
+ * 
+ * Received a Message Successfully
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                     
+ * :---------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_RXOK_E_NORXOK | 0x0   | Since this bit was read by the CPU, no message  
+ * :                                 |       | has been successfully received. This bit is     
+ * :                                 |       | never reset by CAN internal events.             
+ *  ALT_CAN_PROTO_CSTS_RXOK_E_RXOK   | 0x1   | Since this bit was last reset by a read access  
+ * :                                 |       | of the CPU, a message has been successfully     
+ * :                                 |       | received (independently of the result of        
+ * :                                 |       | acceptance filtering). This bit will be reset by
+ * :                                 |       | reading the Status Register.                    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_RXOK
+ * 
+ * Since this bit was read by the CPU, no message has been successfully received.
+ * This bit is never reset by CAN internal events.
+ */
+#define ALT_CAN_PROTO_CSTS_RXOK_E_NORXOK    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_RXOK
+ * 
+ * Since this bit was last reset by a read access of the CPU, a message has been
+ * successfully received (independently of the result of acceptance filtering).
+ * This bit will be reset by reading the Status Register.
+ */
+#define ALT_CAN_PROTO_CSTS_RXOK_E_RXOK      0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_RXOK register field. */
+#define ALT_CAN_PROTO_CSTS_RXOK_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_RXOK register field. */
+#define ALT_CAN_PROTO_CSTS_RXOK_MSB        4
+/* The width in bits of the ALT_CAN_PROTO_CSTS_RXOK register field. */
+#define ALT_CAN_PROTO_CSTS_RXOK_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_RXOK register field value. */
+#define ALT_CAN_PROTO_CSTS_RXOK_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_RXOK register field value. */
+#define ALT_CAN_PROTO_CSTS_RXOK_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_PROTO_CSTS_RXOK register field. */
+#define ALT_CAN_PROTO_CSTS_RXOK_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_RXOK field value from a register. */
+#define ALT_CAN_PROTO_CSTS_RXOK_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_PROTO_CSTS_RXOK register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_RXOK_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : Error Passive - EPASS
+ * 
+ * Error Passive
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                               | Value | Description                                  
+ * :-----------------------------------|:------|:----------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_EPASS_E_ACT     | 0x0   | The CAN Core is in the error active state. It
+ * :                                   |       | normally takes part in bus communication and 
+ * :                                   |       | sends an active error flag when an error has 
+ * :                                   |       | been detected.                               
+ *  ALT_CAN_PROTO_CSTS_EPASS_E_PASSIVE | 0x1   | The CAN Core is in the error passive state as
+ * :                                   |       | defined in the CAN Specification.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_EPASS
+ * 
+ * The CAN Core is in the error active state. It normally takes part in bus
+ * communication and sends an active error flag when an error has been detected.
+ */
+#define ALT_CAN_PROTO_CSTS_EPASS_E_ACT      0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_EPASS
+ * 
+ * The CAN Core is in the error passive state as defined in the CAN Specification.
+ */
+#define ALT_CAN_PROTO_CSTS_EPASS_E_PASSIVE  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_EPASS register field. */
+#define ALT_CAN_PROTO_CSTS_EPASS_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_EPASS register field. */
+#define ALT_CAN_PROTO_CSTS_EPASS_MSB        5
+/* The width in bits of the ALT_CAN_PROTO_CSTS_EPASS register field. */
+#define ALT_CAN_PROTO_CSTS_EPASS_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_EPASS register field value. */
+#define ALT_CAN_PROTO_CSTS_EPASS_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_EPASS register field value. */
+#define ALT_CAN_PROTO_CSTS_EPASS_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_PROTO_CSTS_EPASS register field. */
+#define ALT_CAN_PROTO_CSTS_EPASS_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_EPASS field value from a register. */
+#define ALT_CAN_PROTO_CSTS_EPASS_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_PROTO_CSTS_EPASS register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_EPASS_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : Warning Status - EWarn
+ * 
+ * Warning Status
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description                                    
+ * :--------------------------------------|:------|:------------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_EWARN_E_BELOWLIMIT | 0x0   | Both error counters are below the error warning
+ * :                                      |       | limit of 96.                                   
+ *  ALT_CAN_PROTO_CSTS_EWARN_E_ABOVELIMIT | 0x1   | At least one of the error counters in the EML  
+ * :                                      |       | has reached the error warning limit of 96.     
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_EWARN
+ * 
+ * Both error counters are below the error warning limit of 96.
+ */
+#define ALT_CAN_PROTO_CSTS_EWARN_E_BELOWLIMIT   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_EWARN
+ * 
+ * At least one of the error counters in the EML has reached the error warning
+ * limit of 96.
+ */
+#define ALT_CAN_PROTO_CSTS_EWARN_E_ABOVELIMIT   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_EWARN register field. */
+#define ALT_CAN_PROTO_CSTS_EWARN_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_EWARN register field. */
+#define ALT_CAN_PROTO_CSTS_EWARN_MSB        6
+/* The width in bits of the ALT_CAN_PROTO_CSTS_EWARN register field. */
+#define ALT_CAN_PROTO_CSTS_EWARN_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_EWARN register field value. */
+#define ALT_CAN_PROTO_CSTS_EWARN_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_EWARN register field value. */
+#define ALT_CAN_PROTO_CSTS_EWARN_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_PROTO_CSTS_EWARN register field. */
+#define ALT_CAN_PROTO_CSTS_EWARN_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_EWARN field value from a register. */
+#define ALT_CAN_PROTO_CSTS_EWARN_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_PROTO_CSTS_EWARN register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_EWARN_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : Bus_Off Status - BOff
+ * 
+ * Bus_Off Status
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description                        
+ * :------------------------------------|:------|:------------------------------------
+ *  ALT_CAN_PROTO_CSTS_BOFF_E_NOTBUSOFF | 0x0   | The CAN module is not Bus_Off.     
+ *  ALT_CAN_PROTO_CSTS_BOFF_E_BUSOFF    | 0x1   | The CAN module is in Bus_Off state.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_BOFF
+ * 
+ * The CAN module is not Bus_Off.
+ */
+#define ALT_CAN_PROTO_CSTS_BOFF_E_NOTBUSOFF 0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_BOFF
+ * 
+ * The CAN module is in Bus_Off state.
+ */
+#define ALT_CAN_PROTO_CSTS_BOFF_E_BUSOFF    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_BOFF register field. */
+#define ALT_CAN_PROTO_CSTS_BOFF_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_BOFF register field. */
+#define ALT_CAN_PROTO_CSTS_BOFF_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CSTS_BOFF register field. */
+#define ALT_CAN_PROTO_CSTS_BOFF_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_BOFF register field value. */
+#define ALT_CAN_PROTO_CSTS_BOFF_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_BOFF register field value. */
+#define ALT_CAN_PROTO_CSTS_BOFF_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_PROTO_CSTS_BOFF register field. */
+#define ALT_CAN_PROTO_CSTS_BOFF_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_BOFF field value from a register. */
+#define ALT_CAN_PROTO_CSTS_BOFF_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_PROTO_CSTS_BOFF register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_BOFF_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : Parity Error Detected - PER
+ * 
+ * Parity Error Detected
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                   | Value | Description                                     
+ * :---------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CSTS_PER_E_NONE          | 0x0   | No parity error detected since last read access.
+ *  ALT_CAN_PROTO_CSTS_PER_E_ERRORDETECTED | 0x1   | The Parity CheckMechanism has detected a parity 
+ * :                                       |       | error in the Message RAM, this bit will be reset
+ * :                                       |       | if Status Register is read                      
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_PER
+ * 
+ * No parity error detected since last read access.
+ */
+#define ALT_CAN_PROTO_CSTS_PER_E_NONE           0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CSTS_PER
+ * 
+ * The Parity CheckMechanism has detected a parity error in the Message RAM, this
+ * bit will be reset if Status Register is read
+ */
+#define ALT_CAN_PROTO_CSTS_PER_E_ERRORDETECTED  0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_PER register field. */
+#define ALT_CAN_PROTO_CSTS_PER_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_PER register field. */
+#define ALT_CAN_PROTO_CSTS_PER_MSB        8
+/* The width in bits of the ALT_CAN_PROTO_CSTS_PER register field. */
+#define ALT_CAN_PROTO_CSTS_PER_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CSTS_PER register field value. */
+#define ALT_CAN_PROTO_CSTS_PER_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CAN_PROTO_CSTS_PER register field value. */
+#define ALT_CAN_PROTO_CSTS_PER_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CAN_PROTO_CSTS_PER register field. */
+#define ALT_CAN_PROTO_CSTS_PER_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CSTS_PER field value from a register. */
+#define ALT_CAN_PROTO_CSTS_PER_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CAN_PROTO_CSTS_PER register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CSTS_PER_SET(value) (((value) << 8) & 0x00000100)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CSTS.
+ */
+struct ALT_CAN_PROTO_CSTS_s
+{
+    const uint32_t  LEC   :  3;  /* Last Error Code */
+    const uint32_t  TxOK  :  1;  /* Transmitted a Message Successfully */
+    const uint32_t  RxOK  :  1;  /* Received a Message Successfully */
+    const uint32_t  EPASS :  1;  /* Error Passive */
+    const uint32_t  EWarn :  1;  /* Warning Status */
+    const uint32_t  BOff  :  1;  /* Bus_Off Status */
+    const uint32_t  PER   :  1;  /* Parity Error Detected */
+    uint32_t              : 23;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CSTS. */
+typedef volatile struct ALT_CAN_PROTO_CSTS_s  ALT_CAN_PROTO_CSTS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CSTS register from the beginning of the component. */
+#define ALT_CAN_PROTO_CSTS_OFST        0x4
+/* The address of the ALT_CAN_PROTO_CSTS register. */
+#define ALT_CAN_PROTO_CSTS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CSTS_OFST))
+
+/*
+ * Register : Error Counter Register - CERC
+ * 
+ * Error Counter Register
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description           
+ * :--------|:-------|:------|:-----------------------
+ *  [7:0]   | R      | 0x0   | Transmit Error Counter
+ *  [14:8]  | R      | 0x0   | Receive Error Counter 
+ *  [15]    | R      | 0x0   | Receive Error Passive 
+ *  [31:16] | ???    | 0x0   | *UNDEFINED*           
+ * 
+ */
+/*
+ * Field : Transmit Error Counter - TEC
+ * 
+ * Actual state of the Transmit Error Counter. Values between 0 and 255.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_TEC register field. */
+#define ALT_CAN_PROTO_CERC_TEC_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_TEC register field. */
+#define ALT_CAN_PROTO_CERC_TEC_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CERC_TEC register field. */
+#define ALT_CAN_PROTO_CERC_TEC_WIDTH      8
+/* The mask used to set the ALT_CAN_PROTO_CERC_TEC register field value. */
+#define ALT_CAN_PROTO_CERC_TEC_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_CAN_PROTO_CERC_TEC register field value. */
+#define ALT_CAN_PROTO_CERC_TEC_CLR_MSK    0xffffff00
+/* The reset value of the ALT_CAN_PROTO_CERC_TEC register field. */
+#define ALT_CAN_PROTO_CERC_TEC_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CERC_TEC field value from a register. */
+#define ALT_CAN_PROTO_CERC_TEC_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_CAN_PROTO_CERC_TEC register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CERC_TEC_SET(value) (((value) << 0) & 0x000000ff)
+
+/*
+ * Field : Receive Error Counter - REC
+ * 
+ * Actual state of the Receive Error Counter. Values between 0 and 127.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_REC register field. */
+#define ALT_CAN_PROTO_CERC_REC_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_REC register field. */
+#define ALT_CAN_PROTO_CERC_REC_MSB        14
+/* The width in bits of the ALT_CAN_PROTO_CERC_REC register field. */
+#define ALT_CAN_PROTO_CERC_REC_WIDTH      7
+/* The mask used to set the ALT_CAN_PROTO_CERC_REC register field value. */
+#define ALT_CAN_PROTO_CERC_REC_SET_MSK    0x00007f00
+/* The mask used to clear the ALT_CAN_PROTO_CERC_REC register field value. */
+#define ALT_CAN_PROTO_CERC_REC_CLR_MSK    0xffff80ff
+/* The reset value of the ALT_CAN_PROTO_CERC_REC register field. */
+#define ALT_CAN_PROTO_CERC_REC_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CERC_REC field value from a register. */
+#define ALT_CAN_PROTO_CERC_REC_GET(value) (((value) & 0x00007f00) >> 8)
+/* Produces a ALT_CAN_PROTO_CERC_REC register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CERC_REC_SET(value) (((value) << 8) & 0x00007f00)
+
+/*
+ * Field : Receive Error Passive - RP
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                            | Value | Description                                    
+ * :--------------------------------|:------|:------------------------------------------------
+ *  ALT_CAN_PROTO_CERC_RP_E_BELOW   | 0x0   | The Receive Error Counter is below the error   
+ * :                                |       | passive level.                                 
+ *  ALT_CAN_PROTO_CERC_RP_E_REACHED | 0x1   | The Receive Error Counter has reached the error
+ * :                                |       | passive level as defined in the CAN            
+ * :                                |       | Specification.                                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CERC_RP
+ * 
+ * The Receive Error Counter is below the error passive level.
+ */
+#define ALT_CAN_PROTO_CERC_RP_E_BELOW   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CERC_RP
+ * 
+ * The Receive Error Counter has reached the error passive level as defined in the
+ * CAN Specification.
+ */
+#define ALT_CAN_PROTO_CERC_RP_E_REACHED 0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_RP register field. */
+#define ALT_CAN_PROTO_CERC_RP_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_RP register field. */
+#define ALT_CAN_PROTO_CERC_RP_MSB        15
+/* The width in bits of the ALT_CAN_PROTO_CERC_RP register field. */
+#define ALT_CAN_PROTO_CERC_RP_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CERC_RP register field value. */
+#define ALT_CAN_PROTO_CERC_RP_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_PROTO_CERC_RP register field value. */
+#define ALT_CAN_PROTO_CERC_RP_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_PROTO_CERC_RP register field. */
+#define ALT_CAN_PROTO_CERC_RP_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CERC_RP field value from a register. */
+#define ALT_CAN_PROTO_CERC_RP_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_PROTO_CERC_RP register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CERC_RP_SET(value) (((value) << 15) & 0x00008000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CERC.
+ */
+struct ALT_CAN_PROTO_CERC_s
+{
+    const uint32_t  TEC :  8;  /* Transmit Error Counter */
+    const uint32_t  REC :  7;  /* Receive Error Counter */
+    const uint32_t  RP  :  1;  /* Receive Error Passive */
+    uint32_t            : 16;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CERC. */
+typedef volatile struct ALT_CAN_PROTO_CERC_s  ALT_CAN_PROTO_CERC_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CERC register from the beginning of the component. */
+#define ALT_CAN_PROTO_CERC_OFST        0x8
+/* The address of the ALT_CAN_PROTO_CERC register. */
+#define ALT_CAN_PROTO_CERC_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CERC_OFST))
+
+/*
+ * Register : Bit Timing / BRP Extension Register - CBT
+ * 
+ * This register is only writable if bits CCTRL.CCE and CCTRL.Init are set. The CAN
+ * bit time may be programed in the range of [4 .. 25] time quanta. The CAN time
+ * quantum may be programmed in the range of [1 .. 1024] CAN_CLK periods. For
+ * details see Application Note 001 "Configuration of Bit Timing". The actual
+ * interpretation by the hardware of this value is such that one more than the
+ * value programmed here is used. TSeg1 is the sum of Prop_Seg and Phase_Seg1.
+ * TSeg2 is Phase_Seg2. Therefore the length of the bit time is (programmed values)
+ * [TSeg1 + TSeg2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1
+ * + Phase_Seg2] tq.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                             
+ * :--------|:-------|:------|:-----------------------------------------
+ *  [5:0]   | RW     | 0x1   | Baud Rate Prescaler                     
+ *  [7:6]   | RW     | 0x0   | (Re) Synchronization Jump Width         
+ *  [11:8]  | RW     | 0x3   | The time segment before the sample point
+ *  [14:12] | RW     | 0x2   | The time segment after the sample point 
+ *  [15]    | ???    | 0x0   | *UNDEFINED*                             
+ *  [19:16] | RW     | 0x0   | Baud Rate Prescaler Extension           
+ *  [31:20] | ???    | 0x0   | *UNDEFINED*                             
+ * 
+ */
+/*
+ * Field : Baud Rate Prescaler - BRP
+ * 
+ * The value by which the oscillator frequency is divided for generating the bit
+ * time quanta. The bit time is built up from a multiple of this quanta. Valid
+ * values for the Baud Rate Prescaler are [0 .. 63]. The actual interpretation by
+ * the hardware of this value is such that one more than the value programmed here
+ * is used.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_BRP register field. */
+#define ALT_CAN_PROTO_CBT_BRP_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_BRP register field. */
+#define ALT_CAN_PROTO_CBT_BRP_MSB        5
+/* The width in bits of the ALT_CAN_PROTO_CBT_BRP register field. */
+#define ALT_CAN_PROTO_CBT_BRP_WIDTH      6
+/* The mask used to set the ALT_CAN_PROTO_CBT_BRP register field value. */
+#define ALT_CAN_PROTO_CBT_BRP_SET_MSK    0x0000003f
+/* The mask used to clear the ALT_CAN_PROTO_CBT_BRP register field value. */
+#define ALT_CAN_PROTO_CBT_BRP_CLR_MSK    0xffffffc0
+/* The reset value of the ALT_CAN_PROTO_CBT_BRP register field. */
+#define ALT_CAN_PROTO_CBT_BRP_RESET      0x1
+/* Extracts the ALT_CAN_PROTO_CBT_BRP field value from a register. */
+#define ALT_CAN_PROTO_CBT_BRP_GET(value) (((value) & 0x0000003f) >> 0)
+/* Produces a ALT_CAN_PROTO_CBT_BRP register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CBT_BRP_SET(value) (((value) << 0) & 0x0000003f)
+
+/*
+ * Field : (Re) Synchronization Jump Width - SJW
+ * 
+ * Valid programmed values are [0 .. 3]. The actual interpretation by the hardware
+ * of this value is such that one more than the value programmed here is used.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_SJW register field. */
+#define ALT_CAN_PROTO_CBT_SJW_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_SJW register field. */
+#define ALT_CAN_PROTO_CBT_SJW_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CBT_SJW register field. */
+#define ALT_CAN_PROTO_CBT_SJW_WIDTH      2
+/* The mask used to set the ALT_CAN_PROTO_CBT_SJW register field value. */
+#define ALT_CAN_PROTO_CBT_SJW_SET_MSK    0x000000c0
+/* The mask used to clear the ALT_CAN_PROTO_CBT_SJW register field value. */
+#define ALT_CAN_PROTO_CBT_SJW_CLR_MSK    0xffffff3f
+/* The reset value of the ALT_CAN_PROTO_CBT_SJW register field. */
+#define ALT_CAN_PROTO_CBT_SJW_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CBT_SJW field value from a register. */
+#define ALT_CAN_PROTO_CBT_SJW_GET(value) (((value) & 0x000000c0) >> 6)
+/* Produces a ALT_CAN_PROTO_CBT_SJW register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CBT_SJW_SET(value) (((value) << 6) & 0x000000c0)
+
+/*
+ * Field : The time segment before the sample point - TSeg1
+ * 
+ * Valid values for TSeg1 are [1 .. 15].
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_TSEG1 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG1_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_TSEG1 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG1_MSB        11
+/* The width in bits of the ALT_CAN_PROTO_CBT_TSEG1 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG1_WIDTH      4
+/* The mask used to set the ALT_CAN_PROTO_CBT_TSEG1 register field value. */
+#define ALT_CAN_PROTO_CBT_TSEG1_SET_MSK    0x00000f00
+/* The mask used to clear the ALT_CAN_PROTO_CBT_TSEG1 register field value. */
+#define ALT_CAN_PROTO_CBT_TSEG1_CLR_MSK    0xfffff0ff
+/* The reset value of the ALT_CAN_PROTO_CBT_TSEG1 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG1_RESET      0x3
+/* Extracts the ALT_CAN_PROTO_CBT_TSEG1 field value from a register. */
+#define ALT_CAN_PROTO_CBT_TSEG1_GET(value) (((value) & 0x00000f00) >> 8)
+/* Produces a ALT_CAN_PROTO_CBT_TSEG1 register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CBT_TSEG1_SET(value) (((value) << 8) & 0x00000f00)
+
+/*
+ * Field : The time segment after the sample point - TSeg2
+ * 
+ * Valid values for TSeg2 are [0 .. 7].
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_TSEG2 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG2_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_TSEG2 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG2_MSB        14
+/* The width in bits of the ALT_CAN_PROTO_CBT_TSEG2 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG2_WIDTH      3
+/* The mask used to set the ALT_CAN_PROTO_CBT_TSEG2 register field value. */
+#define ALT_CAN_PROTO_CBT_TSEG2_SET_MSK    0x00007000
+/* The mask used to clear the ALT_CAN_PROTO_CBT_TSEG2 register field value. */
+#define ALT_CAN_PROTO_CBT_TSEG2_CLR_MSK    0xffff8fff
+/* The reset value of the ALT_CAN_PROTO_CBT_TSEG2 register field. */
+#define ALT_CAN_PROTO_CBT_TSEG2_RESET      0x2
+/* Extracts the ALT_CAN_PROTO_CBT_TSEG2 field value from a register. */
+#define ALT_CAN_PROTO_CBT_TSEG2_GET(value) (((value) & 0x00007000) >> 12)
+/* Produces a ALT_CAN_PROTO_CBT_TSEG2 register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CBT_TSEG2_SET(value) (((value) << 12) & 0x00007000)
+
+/*
+ * Field : Baud Rate Prescaler Extension - BRPE
+ * 
+ * By programming BRPE the Baud Rate Prescaler can be extended to values up to
+ * 1023. The actual interpretation by the hardware is that one more than the value
+ * programmed by BRPE (MSBs) and BRP (LSBs) is used.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_BRPE register field. */
+#define ALT_CAN_PROTO_CBT_BRPE_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_BRPE register field. */
+#define ALT_CAN_PROTO_CBT_BRPE_MSB        19
+/* The width in bits of the ALT_CAN_PROTO_CBT_BRPE register field. */
+#define ALT_CAN_PROTO_CBT_BRPE_WIDTH      4
+/* The mask used to set the ALT_CAN_PROTO_CBT_BRPE register field value. */
+#define ALT_CAN_PROTO_CBT_BRPE_SET_MSK    0x000f0000
+/* The mask used to clear the ALT_CAN_PROTO_CBT_BRPE register field value. */
+#define ALT_CAN_PROTO_CBT_BRPE_CLR_MSK    0xfff0ffff
+/* The reset value of the ALT_CAN_PROTO_CBT_BRPE register field. */
+#define ALT_CAN_PROTO_CBT_BRPE_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CBT_BRPE field value from a register. */
+#define ALT_CAN_PROTO_CBT_BRPE_GET(value) (((value) & 0x000f0000) >> 16)
+/* Produces a ALT_CAN_PROTO_CBT_BRPE register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CBT_BRPE_SET(value) (((value) << 16) & 0x000f0000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CBT.
+ */
+struct ALT_CAN_PROTO_CBT_s
+{
+    uint32_t  BRP   :  6;  /* Baud Rate Prescaler */
+    uint32_t  SJW   :  2;  /* (Re) Synchronization Jump Width */
+    uint32_t  TSeg1 :  4;  /* The time segment before the sample point */
+    uint32_t  TSeg2 :  3;  /* The time segment after the sample point */
+    uint32_t        :  1;  /* *UNDEFINED* */
+    uint32_t  BRPE  :  4;  /* Baud Rate Prescaler Extension */
+    uint32_t        : 12;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CBT. */
+typedef volatile struct ALT_CAN_PROTO_CBT_s  ALT_CAN_PROTO_CBT_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CBT register from the beginning of the component. */
+#define ALT_CAN_PROTO_CBT_OFST        0xc
+/* The address of the ALT_CAN_PROTO_CBT register. */
+#define ALT_CAN_PROTO_CBT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CBT_OFST))
+
+/*
+ * Register : Interrupt Register - CIR
+ * 
+ * If several interrupts are pending, the CAN Interrupt Register will point to the
+ * pending interrupt with the highest priority, disregarding their chronological
+ * order. An interrupt remains pending until the CPU has cleared it. If IntID is
+ * different from 0x00 and CCTRL.MIL is set, the interrupt port CAN_INT_MO is
+ * active. The interrupt port remains active until IntID is back to value 0x00 (the
+ * cause of the interrupt is reset) or until CCTRL.MIL is reset. If CCTRL.ILE is
+ * set and CCTRL.MIL is reseted the Message Object interrupts will be routed to
+ * interrupt port CAN_INT_STATUS. The interrupt port remains active until IntID is
+ * back to value 0x00 (the cause of the interrupt is reset) or until CCTRL.MIL is
+ * set or CCTRL.ILE is reset.
+ * 
+ * The Message Object's interrupt priority decreases with increasing message
+ * number.
+ * 
+ * A message interrupt is cleared by clearing the Message Object's IntPnd bit.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description                    
+ * :--------|:-------|:------|:--------------------------------
+ *  [7:0]   | R      | 0x0   | Interrupt Identifier           
+ *  [14:8]  | ???    | 0x0   | *UNDEFINED*                    
+ *  [15]    | R      | 0x0   | A Status Interrupt has occurred
+ *  [31:16] | ???    | 0x0   | *UNDEFINED*                    
+ * 
+ */
+/*
+ * Field : Interrupt Identifier - IntId
+ * 
+ * 0x00 No Message Object interrupt is pending.
+ * 
+ * 0x01-0x80 Number of Message Object which caused the interrupt.
+ * 
+ * 0x81-0xFF unused.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CIR_INTID register field. */
+#define ALT_CAN_PROTO_CIR_INTID_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CIR_INTID register field. */
+#define ALT_CAN_PROTO_CIR_INTID_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CIR_INTID register field. */
+#define ALT_CAN_PROTO_CIR_INTID_WIDTH      8
+/* The mask used to set the ALT_CAN_PROTO_CIR_INTID register field value. */
+#define ALT_CAN_PROTO_CIR_INTID_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_CAN_PROTO_CIR_INTID register field value. */
+#define ALT_CAN_PROTO_CIR_INTID_CLR_MSK    0xffffff00
+/* The reset value of the ALT_CAN_PROTO_CIR_INTID register field. */
+#define ALT_CAN_PROTO_CIR_INTID_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CIR_INTID field value from a register. */
+#define ALT_CAN_PROTO_CIR_INTID_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_CAN_PROTO_CIR_INTID register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CIR_INTID_SET(value) (((value) << 0) & 0x000000ff)
+
+/*
+ * Field : A Status Interrupt has occurred - StatusInt
+ * 
+ * The Status Interrupt is cleared by reading the Status Register.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CIR_STATINT register field. */
+#define ALT_CAN_PROTO_CIR_STATINT_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CIR_STATINT register field. */
+#define ALT_CAN_PROTO_CIR_STATINT_MSB        15
+/* The width in bits of the ALT_CAN_PROTO_CIR_STATINT register field. */
+#define ALT_CAN_PROTO_CIR_STATINT_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CIR_STATINT register field value. */
+#define ALT_CAN_PROTO_CIR_STATINT_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_PROTO_CIR_STATINT register field value. */
+#define ALT_CAN_PROTO_CIR_STATINT_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_PROTO_CIR_STATINT register field. */
+#define ALT_CAN_PROTO_CIR_STATINT_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CIR_STATINT field value from a register. */
+#define ALT_CAN_PROTO_CIR_STATINT_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_PROTO_CIR_STATINT register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CIR_STATINT_SET(value) (((value) << 15) & 0x00008000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CIR.
+ */
+struct ALT_CAN_PROTO_CIR_s
+{
+    const uint32_t  IntId     :  8;  /* Interrupt Identifier */
+    uint32_t                  :  7;  /* *UNDEFINED* */
+    const uint32_t  StatusInt :  1;  /* A Status Interrupt has occurred */
+    uint32_t                  : 16;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CIR. */
+typedef volatile struct ALT_CAN_PROTO_CIR_s  ALT_CAN_PROTO_CIR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CIR register from the beginning of the component. */
+#define ALT_CAN_PROTO_CIR_OFST        0x10
+/* The address of the ALT_CAN_PROTO_CIR register. */
+#define ALT_CAN_PROTO_CIR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CIR_OFST))
+
+/*
+ * Register : Test Register - CTR
+ * 
+ * The Test Mode is entered by setting bit CCTRL.Test to one. In Test Mode the bits
+ * EXL, Tx1, Tx0, LBack and Silent in the Test Register are writable. Bit Rx
+ * monitors the state of pin CAN_RXD and therefore is only readable. All Test
+ * Register functions are disabled when bit Test is reset to zero.
+ * 
+ * Loop Back Mode and CAN_TXD Control Mode are hardware test modes, not to be used
+ * by application programs.
+ * 
+ * Note: This register is only writable if bit CCTRL.Test is set.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset   | Description   
+ * :-------|:-------|:--------|:---------------
+ *  [2:0]  | ???    | 0x0     | *UNDEFINED*   
+ *  [3]    | RW     | 0x0     | Silent Mode   
+ *  [4]    | RW     | 0x0     | Loop Back Mode
+ *  [6:5]  | RW     | 0x0     | Transmit Pin  
+ *  [7]    | R      | Unknown | Receive Pin   
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*   
+ * 
+ */
+/*
+ * Field : Silent Mode - Silent
+ * 
+ * Silent Mode
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                              | Value | Description               
+ * :----------------------------------|:------|:---------------------------
+ *  ALT_CAN_PROTO_CTR_SILENT_E_NORMAL | 0x0   | Normal operation.         
+ *  ALT_CAN_PROTO_CTR_SILENT_E_SILENT | 0x1   | The CAN is in Silent Mode.
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_SILENT
+ * 
+ * Normal operation.
+ */
+#define ALT_CAN_PROTO_CTR_SILENT_E_NORMAL   0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_SILENT
+ * 
+ * The CAN is in Silent Mode.
+ */
+#define ALT_CAN_PROTO_CTR_SILENT_E_SILENT   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_SILENT register field. */
+#define ALT_CAN_PROTO_CTR_SILENT_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_SILENT register field. */
+#define ALT_CAN_PROTO_CTR_SILENT_MSB        3
+/* The width in bits of the ALT_CAN_PROTO_CTR_SILENT register field. */
+#define ALT_CAN_PROTO_CTR_SILENT_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CTR_SILENT register field value. */
+#define ALT_CAN_PROTO_CTR_SILENT_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_PROTO_CTR_SILENT register field value. */
+#define ALT_CAN_PROTO_CTR_SILENT_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_PROTO_CTR_SILENT register field. */
+#define ALT_CAN_PROTO_CTR_SILENT_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CTR_SILENT field value from a register. */
+#define ALT_CAN_PROTO_CTR_SILENT_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_PROTO_CTR_SILENT register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CTR_SILENT_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : Loop Back Mode - LBack
+ * 
+ * Loop Back Mode
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                           | Value | Description                
+ * :-------------------------------|:------|:----------------------------
+ *  ALT_CAN_PROTO_CTR_LBACK_E_DISD | 0x0   | Loop Back Mode is disabled.
+ *  ALT_CAN_PROTO_CTR_LBACK_E_END  | 0x1   | Loop Back Mode is enabled. 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_LBACK
+ * 
+ * Loop Back Mode is disabled.
+ */
+#define ALT_CAN_PROTO_CTR_LBACK_E_DISD  0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_LBACK
+ * 
+ * Loop Back Mode is enabled.
+ */
+#define ALT_CAN_PROTO_CTR_LBACK_E_END   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_LBACK register field. */
+#define ALT_CAN_PROTO_CTR_LBACK_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_LBACK register field. */
+#define ALT_CAN_PROTO_CTR_LBACK_MSB        4
+/* The width in bits of the ALT_CAN_PROTO_CTR_LBACK register field. */
+#define ALT_CAN_PROTO_CTR_LBACK_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CTR_LBACK register field value. */
+#define ALT_CAN_PROTO_CTR_LBACK_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_PROTO_CTR_LBACK register field value. */
+#define ALT_CAN_PROTO_CTR_LBACK_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_PROTO_CTR_LBACK register field. */
+#define ALT_CAN_PROTO_CTR_LBACK_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CTR_LBACK field value from a register. */
+#define ALT_CAN_PROTO_CTR_LBACK_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_PROTO_CTR_LBACK register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CTR_LBACK_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : Transmit Pin - Tx
+ * 
+ * Controls CAN_TXD pin.  Setting to non-zero disturbs message transfer.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                                  
+ * :---------------------------------|:------|:----------------------------------------------
+ *  ALT_CAN_PROTO_CTR_TX_E_RST       | 0x0   | Reset value, CAN_TXD is controlled by the    
+ * :                                 |       | CAN_Core.                                    
+ *  ALT_CAN_PROTO_CTR_TX_E_SMPL      | 0x1   | Sample Point can be monitored at CAN_TXD pin.
+ *  ALT_CAN_PROTO_CTR_TX_E_DOMINANT  | 0x2   | CAN_TXD pin drives a dominant (0) value.     
+ *  ALT_CAN_PROTO_CTR_TX_E_RECESSIVE | 0x3   | CAN_TXD pin drives a recessive (1) value.    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_TX
+ * 
+ * Reset value, CAN_TXD is controlled by the CAN_Core.
+ */
+#define ALT_CAN_PROTO_CTR_TX_E_RST          0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_TX
+ * 
+ * Sample Point can be monitored at CAN_TXD pin.
+ */
+#define ALT_CAN_PROTO_CTR_TX_E_SMPL         0x1
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_TX
+ * 
+ * CAN_TXD pin drives a dominant (0) value.
+ */
+#define ALT_CAN_PROTO_CTR_TX_E_DOMINANT     0x2
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_TX
+ * 
+ * CAN_TXD pin drives a recessive (1) value.
+ */
+#define ALT_CAN_PROTO_CTR_TX_E_RECESSIVE    0x3
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_TX register field. */
+#define ALT_CAN_PROTO_CTR_TX_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_TX register field. */
+#define ALT_CAN_PROTO_CTR_TX_MSB        6
+/* The width in bits of the ALT_CAN_PROTO_CTR_TX register field. */
+#define ALT_CAN_PROTO_CTR_TX_WIDTH      2
+/* The mask used to set the ALT_CAN_PROTO_CTR_TX register field value. */
+#define ALT_CAN_PROTO_CTR_TX_SET_MSK    0x00000060
+/* The mask used to clear the ALT_CAN_PROTO_CTR_TX register field value. */
+#define ALT_CAN_PROTO_CTR_TX_CLR_MSK    0xffffff9f
+/* The reset value of the ALT_CAN_PROTO_CTR_TX register field. */
+#define ALT_CAN_PROTO_CTR_TX_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CTR_TX field value from a register. */
+#define ALT_CAN_PROTO_CTR_TX_GET(value) (((value) & 0x00000060) >> 5)
+/* Produces a ALT_CAN_PROTO_CTR_TX register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CTR_TX_SET(value) (((value) << 5) & 0x00000060)
+
+/*
+ * Field : Receive Pin - Rx
+ * 
+ * Monitors the actual value of the CAN_RXD pin.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                             | Value | Description                            
+ * :---------------------------------|:------|:----------------------------------------
+ *  ALT_CAN_PROTO_CTR_RX_E_DOMINANT  | 0x0   | The CAN bus is dominant (CAN_RXD = 0). 
+ *  ALT_CAN_PROTO_CTR_RX_E_RECESSIVE | 0x1   | The CAN bus is recessive (CAN_RXD = 1).
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_RX
+ * 
+ * The CAN bus is dominant (CAN_RXD = 0).
+ */
+#define ALT_CAN_PROTO_CTR_RX_E_DOMINANT     0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CTR_RX
+ * 
+ * The CAN bus is recessive (CAN_RXD = 1).
+ */
+#define ALT_CAN_PROTO_CTR_RX_E_RECESSIVE    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_RX register field. */
+#define ALT_CAN_PROTO_CTR_RX_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_RX register field. */
+#define ALT_CAN_PROTO_CTR_RX_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CTR_RX register field. */
+#define ALT_CAN_PROTO_CTR_RX_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CTR_RX register field value. */
+#define ALT_CAN_PROTO_CTR_RX_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_PROTO_CTR_RX register field value. */
+#define ALT_CAN_PROTO_CTR_RX_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_PROTO_CTR_RX register field is UNKNOWN. */
+#define ALT_CAN_PROTO_CTR_RX_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CTR_RX field value from a register. */
+#define ALT_CAN_PROTO_CTR_RX_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_PROTO_CTR_RX register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CTR_RX_SET(value) (((value) << 7) & 0x00000080)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CTR.
+ */
+struct ALT_CAN_PROTO_CTR_s
+{
+    uint32_t               :  3;  /* *UNDEFINED* */
+    uint32_t        Silent :  1;  /* Silent Mode */
+    uint32_t        LBack  :  1;  /* Loop Back Mode */
+    uint32_t        Tx     :  2;  /* Transmit Pin */
+    const uint32_t  Rx     :  1;  /* Receive Pin */
+    uint32_t               : 24;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CTR. */
+typedef volatile struct ALT_CAN_PROTO_CTR_s  ALT_CAN_PROTO_CTR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CTR register from the beginning of the component. */
+#define ALT_CAN_PROTO_CTR_OFST        0x14
+/* The address of the ALT_CAN_PROTO_CTR register. */
+#define ALT_CAN_PROTO_CTR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CTR_OFST))
+
+/*
+ * Register : Function Register - CFR
+ * 
+ * The Function Register controls the features RAM_Initialisation and Power_Down
+ * also by application register.
+ * 
+ * The CAN module can be prepared for Power_Down by setting the port
+ * CAN_CLKSTOP_REQ to one or writing to CFR.ClkStReq a one. The power down state is
+ * left by setting port CAN_CLKSTOP_REQ to zero or writing to CFR.ClkStReq a zero,
+ * acknowledged by CAN_CLKSTOP_ACK is going to zero as well as CFR.ClkStAck. The
+ * CCTRL.Init bit is left one and has to be written by the application to re-enable
+ * CAN transfers.
+ * 
+ * Note: It's recommended to use either the ports CAN_CLKSTOP_REQ and
+ * CAN_CLKSTOP_ACK or the CCTRL.ClkStReq and CFR.ClkStAck. The application
+ * CFR.ClkStReq showsalso the actual status of the portCAN_CLKSTOP_REQ.
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description                             
+ * :-------|:-------|:------|:-----------------------------------------
+ *  [0]    | R      | 0x0   | Clock Stop Acknowledgement              
+ *  [1]    | RW     | 0x0   | Clock Stop Request                      
+ *  [2]    | ???    | 0x0   | *UNDEFINED*                             
+ *  [3]    | RW     | 0x0   | Request for automatic RAM Initialization
+ *  [31:4] | ???    | 0x0   | *UNDEFINED*                             
+ * 
+ */
+/*
+ * Field : Clock Stop Acknowledgement - ClkStAck
+ * 
+ * Clock Stop Acknowledgement
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_MSB        0
+/* The width in bits of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CFR_CLKSTACK register field value. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_PROTO_CFR_CLKSTACK register field value. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CFR_CLKSTACK field value from a register. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_PROTO_CFR_CLKSTACK register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CFR_CLKSTACK_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : Clock Stop Request - ClkStReq
+ * 
+ * Clock Stop Request
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_MSB        1
+/* The width in bits of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CFR_CLKSTREQ register field value. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_PROTO_CFR_CLKSTREQ register field value. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CFR_CLKSTREQ field value from a register. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_PROTO_CFR_CLKSTREQ register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CFR_CLKSTREQ_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : Request for automatic RAM Initialization - RAMinit
+ * 
+ * Request for automatic RAM Initialization
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                  | Value | Description                                     
+ * :--------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_PROTO_CFR_RAMINIT_E_NOAUTO    | 0x0   | No automatic RAM Initialization is requested, if
+ * :                                      |       | once a ram initialization is started a write of 
+ * :                                      |       | a zero will be ignored. The Bit is cleared by   
+ * :                                      |       | hardware, after RAM Initialization is completed.
+ *  ALT_CAN_PROTO_CFR_RAMINIT_E_STARTAUTO | 0x1   | Start automatic RAM Initialization. All message 
+ * :                                      |       | objects will be written with zeros and the      
+ * :                                      |       | parity bits will be set. The RAMInit Bit will   
+ * :                                      |       | return to zero after the RAM-Initialization     
+ * :                                      |       | process is completed. A RAM Initialization      
+ * :                                      |       | Request is only possible if CCTRL.Init is set.  
+ * :                                      |       | The duration of the automatic RAM Initialization
+ * :                                      |       | is messagebuffer-size + 4 host_clock cycles.    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CFR_RAMINIT
+ * 
+ * No automatic RAM Initialization is requested, if once a ram initialization is
+ * started a write of a zero will be ignored. The Bit is cleared by hardware, after
+ * RAM Initialization is completed.
+ */
+#define ALT_CAN_PROTO_CFR_RAMINIT_E_NOAUTO      0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_CFR_RAMINIT
+ * 
+ * Start automatic RAM Initialization. All message objects will be written with
+ * zeros and the parity bits will be set. The RAMInit Bit will return to zero after
+ * the RAM-Initialization process is completed. A RAM Initialization Request is
+ * only possible if CCTRL.Init is set. The duration of the automatic RAM
+ * Initialization is messagebuffer-size + 4 host_clock cycles.
+ */
+#define ALT_CAN_PROTO_CFR_RAMINIT_E_STARTAUTO   0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_RAMINIT register field. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_RAMINIT register field. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_MSB        3
+/* The width in bits of the ALT_CAN_PROTO_CFR_RAMINIT register field. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_CFR_RAMINIT register field value. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_PROTO_CFR_RAMINIT register field value. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_PROTO_CFR_RAMINIT register field. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_CFR_RAMINIT field value from a register. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_PROTO_CFR_RAMINIT register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CFR_RAMINIT_SET(value) (((value) << 3) & 0x00000008)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CFR.
+ */
+struct ALT_CAN_PROTO_CFR_s
+{
+    const uint32_t  ClkStAck :  1;  /* Clock Stop Acknowledgement */
+    uint32_t        ClkStReq :  1;  /* Clock Stop Request */
+    uint32_t                 :  1;  /* *UNDEFINED* */
+    uint32_t        RAMinit  :  1;  /* Request for automatic RAM Initialization */
+    uint32_t                 : 28;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CFR. */
+typedef volatile struct ALT_CAN_PROTO_CFR_s  ALT_CAN_PROTO_CFR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CFR register from the beginning of the component. */
+#define ALT_CAN_PROTO_CFR_OFST        0x18
+/* The address of the ALT_CAN_PROTO_CFR register. */
+#define ALT_CAN_PROTO_CFR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CFR_OFST))
+
+/*
+ * Register : Core Release Register - CRR
+ * 
+ * Core Release Register
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description             
+ * :--------|:-------|:------|:-------------------------
+ *  [7:0]   | R      | 0x28  | Design Time Stamp, Day  
+ *  [15:8]  | R      | 0x11  | Design Time Stamp, Month
+ *  [19:16] | R      | 0x6   | Design Time Stamp, Year 
+ *  [27:20] | R      | 0x11  | Step of Core Release    
+ *  [31:28] | R      | 0x1   | Core Release            
+ * 
+ */
+/*
+ * Field : Design Time Stamp, Day - DAY
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_DAY register field. */
+#define ALT_CAN_PROTO_CRR_DAY_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_DAY register field. */
+#define ALT_CAN_PROTO_CRR_DAY_MSB        7
+/* The width in bits of the ALT_CAN_PROTO_CRR_DAY register field. */
+#define ALT_CAN_PROTO_CRR_DAY_WIDTH      8
+/* The mask used to set the ALT_CAN_PROTO_CRR_DAY register field value. */
+#define ALT_CAN_PROTO_CRR_DAY_SET_MSK    0x000000ff
+/* The mask used to clear the ALT_CAN_PROTO_CRR_DAY register field value. */
+#define ALT_CAN_PROTO_CRR_DAY_CLR_MSK    0xffffff00
+/* The reset value of the ALT_CAN_PROTO_CRR_DAY register field. */
+#define ALT_CAN_PROTO_CRR_DAY_RESET      0x28
+/* Extracts the ALT_CAN_PROTO_CRR_DAY field value from a register. */
+#define ALT_CAN_PROTO_CRR_DAY_GET(value) (((value) & 0x000000ff) >> 0)
+/* Produces a ALT_CAN_PROTO_CRR_DAY register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CRR_DAY_SET(value) (((value) << 0) & 0x000000ff)
+
+/*
+ * Field : Design Time Stamp, Month - MON
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_MON register field. */
+#define ALT_CAN_PROTO_CRR_MON_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_MON register field. */
+#define ALT_CAN_PROTO_CRR_MON_MSB        15
+/* The width in bits of the ALT_CAN_PROTO_CRR_MON register field. */
+#define ALT_CAN_PROTO_CRR_MON_WIDTH      8
+/* The mask used to set the ALT_CAN_PROTO_CRR_MON register field value. */
+#define ALT_CAN_PROTO_CRR_MON_SET_MSK    0x0000ff00
+/* The mask used to clear the ALT_CAN_PROTO_CRR_MON register field value. */
+#define ALT_CAN_PROTO_CRR_MON_CLR_MSK    0xffff00ff
+/* The reset value of the ALT_CAN_PROTO_CRR_MON register field. */
+#define ALT_CAN_PROTO_CRR_MON_RESET      0x11
+/* Extracts the ALT_CAN_PROTO_CRR_MON field value from a register. */
+#define ALT_CAN_PROTO_CRR_MON_GET(value) (((value) & 0x0000ff00) >> 8)
+/* Produces a ALT_CAN_PROTO_CRR_MON register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CRR_MON_SET(value) (((value) << 8) & 0x0000ff00)
+
+/*
+ * Field : Design Time Stamp, Year - YEAR
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_YEAR register field. */
+#define ALT_CAN_PROTO_CRR_YEAR_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_YEAR register field. */
+#define ALT_CAN_PROTO_CRR_YEAR_MSB        19
+/* The width in bits of the ALT_CAN_PROTO_CRR_YEAR register field. */
+#define ALT_CAN_PROTO_CRR_YEAR_WIDTH      4
+/* The mask used to set the ALT_CAN_PROTO_CRR_YEAR register field value. */
+#define ALT_CAN_PROTO_CRR_YEAR_SET_MSK    0x000f0000
+/* The mask used to clear the ALT_CAN_PROTO_CRR_YEAR register field value. */
+#define ALT_CAN_PROTO_CRR_YEAR_CLR_MSK    0xfff0ffff
+/* The reset value of the ALT_CAN_PROTO_CRR_YEAR register field. */
+#define ALT_CAN_PROTO_CRR_YEAR_RESET      0x6
+/* Extracts the ALT_CAN_PROTO_CRR_YEAR field value from a register. */
+#define ALT_CAN_PROTO_CRR_YEAR_GET(value) (((value) & 0x000f0000) >> 16)
+/* Produces a ALT_CAN_PROTO_CRR_YEAR register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CRR_YEAR_SET(value) (((value) << 16) & 0x000f0000)
+
+/*
+ * Field : Step of Core Release - STEP
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_STEP register field. */
+#define ALT_CAN_PROTO_CRR_STEP_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_STEP register field. */
+#define ALT_CAN_PROTO_CRR_STEP_MSB        27
+/* The width in bits of the ALT_CAN_PROTO_CRR_STEP register field. */
+#define ALT_CAN_PROTO_CRR_STEP_WIDTH      8
+/* The mask used to set the ALT_CAN_PROTO_CRR_STEP register field value. */
+#define ALT_CAN_PROTO_CRR_STEP_SET_MSK    0x0ff00000
+/* The mask used to clear the ALT_CAN_PROTO_CRR_STEP register field value. */
+#define ALT_CAN_PROTO_CRR_STEP_CLR_MSK    0xf00fffff
+/* The reset value of the ALT_CAN_PROTO_CRR_STEP register field. */
+#define ALT_CAN_PROTO_CRR_STEP_RESET      0x11
+/* Extracts the ALT_CAN_PROTO_CRR_STEP field value from a register. */
+#define ALT_CAN_PROTO_CRR_STEP_GET(value) (((value) & 0x0ff00000) >> 20)
+/* Produces a ALT_CAN_PROTO_CRR_STEP register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CRR_STEP_SET(value) (((value) << 20) & 0x0ff00000)
+
+/*
+ * Field : Core Release - REL
+ * 
+ * Field Access Macros:
+ * 
+ */
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_REL register field. */
+#define ALT_CAN_PROTO_CRR_REL_LSB        28
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_REL register field. */
+#define ALT_CAN_PROTO_CRR_REL_MSB        31
+/* The width in bits of the ALT_CAN_PROTO_CRR_REL register field. */
+#define ALT_CAN_PROTO_CRR_REL_WIDTH      4
+/* The mask used to set the ALT_CAN_PROTO_CRR_REL register field value. */
+#define ALT_CAN_PROTO_CRR_REL_SET_MSK    0xf0000000
+/* The mask used to clear the ALT_CAN_PROTO_CRR_REL register field value. */
+#define ALT_CAN_PROTO_CRR_REL_CLR_MSK    0x0fffffff
+/* The reset value of the ALT_CAN_PROTO_CRR_REL register field. */
+#define ALT_CAN_PROTO_CRR_REL_RESET      0x1
+/* Extracts the ALT_CAN_PROTO_CRR_REL field value from a register. */
+#define ALT_CAN_PROTO_CRR_REL_GET(value) (((value) & 0xf0000000) >> 28)
+/* Produces a ALT_CAN_PROTO_CRR_REL register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_CRR_REL_SET(value) (((value) << 28) & 0xf0000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_CRR.
+ */
+struct ALT_CAN_PROTO_CRR_s
+{
+    const uint32_t  DAY  :  8;  /* Design Time Stamp, Day */
+    const uint32_t  MON  :  8;  /* Design Time Stamp, Month */
+    const uint32_t  YEAR :  4;  /* Design Time Stamp, Year */
+    const uint32_t  STEP :  8;  /* Step of Core Release */
+    const uint32_t  REL  :  4;  /* Core Release */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_CRR. */
+typedef volatile struct ALT_CAN_PROTO_CRR_s  ALT_CAN_PROTO_CRR_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_CRR register from the beginning of the component. */
+#define ALT_CAN_PROTO_CRR_OFST        0x20
+/* The address of the ALT_CAN_PROTO_CRR register. */
+#define ALT_CAN_PROTO_CRR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CRR_OFST))
+
+/*
+ * Register : Hardware Configuration Status Register - HWS
+ * 
+ * Hardware Configuration Status Register
+ * 
+ * Register Layout
+ * 
+ *  Bits   | Access | Reset | Description         
+ * :-------|:-------|:------|:---------------------
+ *  [1:0]  | R      | 0x3   | Message Buffer Count
+ *  [2]    | R      | 0x0   | Parity Generation   
+ *  [31:3] | ???    | 0x0   | *UNDEFINED*         
+ * 
+ */
+/*
+ * Field : Message Buffer Count - mb_w
+ * 
+ * Message Buffer Count
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                | Value | Description        
+ * :------------------------------------|:------|:--------------------
+ *  ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS16  | 0x0   | 16 Message Objects 
+ *  ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS32  | 0x1   | 32 Message Objects 
+ *  ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS64  | 0x2   | 64 Message Objects 
+ *  ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS128 | 0x3   | 128 Message Objects
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W
+ * 
+ * 16 Message Objects
+ */
+#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS16  0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W
+ * 
+ * 32 Message Objects
+ */
+#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS32  0x1
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W
+ * 
+ * 64 Message Objects
+ */
+#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS64  0x2
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W
+ * 
+ * 128 Message Objects
+ */
+#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS128 0x3
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_HWS_MB_W register field. */
+#define ALT_CAN_PROTO_HWS_MB_W_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_HWS_MB_W register field. */
+#define ALT_CAN_PROTO_HWS_MB_W_MSB        1
+/* The width in bits of the ALT_CAN_PROTO_HWS_MB_W register field. */
+#define ALT_CAN_PROTO_HWS_MB_W_WIDTH      2
+/* The mask used to set the ALT_CAN_PROTO_HWS_MB_W register field value. */
+#define ALT_CAN_PROTO_HWS_MB_W_SET_MSK    0x00000003
+/* The mask used to clear the ALT_CAN_PROTO_HWS_MB_W register field value. */
+#define ALT_CAN_PROTO_HWS_MB_W_CLR_MSK    0xfffffffc
+/* The reset value of the ALT_CAN_PROTO_HWS_MB_W register field. */
+#define ALT_CAN_PROTO_HWS_MB_W_RESET      0x3
+/* Extracts the ALT_CAN_PROTO_HWS_MB_W field value from a register. */
+#define ALT_CAN_PROTO_HWS_MB_W_GET(value) (((value) & 0x00000003) >> 0)
+/* Produces a ALT_CAN_PROTO_HWS_MB_W register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_HWS_MB_W_SET(value) (((value) << 0) & 0x00000003)
+
+/*
+ * Field : Parity Generation - paren
+ * 
+ * Parity Generation
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                 | Value | Description                              
+ * :-------------------------------------|:------|:------------------------------------------
+ *  ALT_CAN_PROTO_HWS_PAREN_E_NOTPRESENT | 0x0   | Parity generation harware is not present.
+ *  ALT_CAN_PROTO_HWS_PAREN_E_PRESENT    | 0x1   | Parity generation harware is present.    
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_PAREN
+ * 
+ * Parity generation harware is not present.
+ */
+#define ALT_CAN_PROTO_HWS_PAREN_E_NOTPRESENT    0x0
+/*
+ * Enumerated value for register field ALT_CAN_PROTO_HWS_PAREN
+ * 
+ * Parity generation harware is present.
+ */
+#define ALT_CAN_PROTO_HWS_PAREN_E_PRESENT       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_HWS_PAREN register field. */
+#define ALT_CAN_PROTO_HWS_PAREN_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_HWS_PAREN register field. */
+#define ALT_CAN_PROTO_HWS_PAREN_MSB        2
+/* The width in bits of the ALT_CAN_PROTO_HWS_PAREN register field. */
+#define ALT_CAN_PROTO_HWS_PAREN_WIDTH      1
+/* The mask used to set the ALT_CAN_PROTO_HWS_PAREN register field value. */
+#define ALT_CAN_PROTO_HWS_PAREN_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_PROTO_HWS_PAREN register field value. */
+#define ALT_CAN_PROTO_HWS_PAREN_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_PROTO_HWS_PAREN register field. */
+#define ALT_CAN_PROTO_HWS_PAREN_RESET      0x0
+/* Extracts the ALT_CAN_PROTO_HWS_PAREN field value from a register. */
+#define ALT_CAN_PROTO_HWS_PAREN_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_PROTO_HWS_PAREN register field value suitable for setting the register. */
+#define ALT_CAN_PROTO_HWS_PAREN_SET(value) (((value) << 2) & 0x00000004)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_PROTO_HWS.
+ */
+struct ALT_CAN_PROTO_HWS_s
+{
+    const uint32_t  mb_w  :  2;  /* Message Buffer Count */
+    const uint32_t  paren :  1;  /* Parity Generation */
+    uint32_t              : 29;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_PROTO_HWS. */
+typedef volatile struct ALT_CAN_PROTO_HWS_s  ALT_CAN_PROTO_HWS_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_PROTO_HWS register from the beginning of the component. */
+#define ALT_CAN_PROTO_HWS_OFST        0x24
+/* The address of the ALT_CAN_PROTO_HWS register. */
+#define ALT_CAN_PROTO_HWS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_HWS_OFST))
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register group ALT_CAN_PROTO.
+ */
+struct ALT_CAN_PROTO_s
+{
+    volatile ALT_CAN_PROTO_CCTL_t  CCTRL;           /* ALT_CAN_PROTO_CCTL */
+    volatile ALT_CAN_PROTO_CSTS_t  CSTS;            /* ALT_CAN_PROTO_CSTS */
+    volatile ALT_CAN_PROTO_CERC_t  CERC;            /* ALT_CAN_PROTO_CERC */
+    volatile ALT_CAN_PROTO_CBT_t   CBT;             /* ALT_CAN_PROTO_CBT */
+    volatile ALT_CAN_PROTO_CIR_t   CIR;             /* ALT_CAN_PROTO_CIR */
+    volatile ALT_CAN_PROTO_CTR_t   CTR;             /* ALT_CAN_PROTO_CTR */
+    volatile ALT_CAN_PROTO_CFR_t   CFR;             /* ALT_CAN_PROTO_CFR */
+    volatile uint32_t              _pad_0x1c_0x1f;  /* *UNDEFINED* */
+    volatile ALT_CAN_PROTO_CRR_t   CRR;             /* ALT_CAN_PROTO_CRR */
+    volatile ALT_CAN_PROTO_HWS_t   HWS;             /* ALT_CAN_PROTO_HWS */
+};
+
+/* The typedef declaration for register group ALT_CAN_PROTO. */
+typedef volatile struct ALT_CAN_PROTO_s  ALT_CAN_PROTO_t;
+/* The struct declaration for the raw register contents of register group ALT_CAN_PROTO. */
+struct ALT_CAN_PROTO_raw_s
+{
+    volatile uint32_t  CCTRL;           /* ALT_CAN_PROTO_CCTL */
+    volatile uint32_t  CSTS;            /* ALT_CAN_PROTO_CSTS */
+    volatile uint32_t  CERC;            /* ALT_CAN_PROTO_CERC */
+    volatile uint32_t  CBT;             /* ALT_CAN_PROTO_CBT */
+    volatile uint32_t  CIR;             /* ALT_CAN_PROTO_CIR */
+    volatile uint32_t  CTR;             /* ALT_CAN_PROTO_CTR */
+    volatile uint32_t  CFR;             /* ALT_CAN_PROTO_CFR */
+    volatile uint32_t  _pad_0x1c_0x1f;  /* *UNDEFINED* */
+    volatile uint32_t  CRR;             /* ALT_CAN_PROTO_CRR */
+    volatile uint32_t  HWS;             /* ALT_CAN_PROTO_HWS */
+};
+
+/* The typedef declaration for the raw register contents of register group ALT_CAN_PROTO. */
+typedef volatile struct ALT_CAN_PROTO_raw_s  ALT_CAN_PROTO_raw_t;
+#endif  /* __ASSEMBLY__ */
+
+
+/*
+ * Register Group : Message Handler Group - ALT_CAN_MSGHAND
+ * Message Handler Group
+ * 
+ * These registers are related to the operation of the Message Handler. The Message
+ * Handler is a state machine that controls the data transfer between the single
+ * ported Message RAM and the CAN Core's Rx/Tx Shift Register. It also handles
+ * acceptance filtering and the interrupt setting as programmed in the Control and
+ * Configuration Registers.
+ * 
+ */
+/*
+ * Register : Transmission Request X Register - MOTRX
+ * 
+ * Reading this register allows the CPU to quickly detect if any of the
+ * transmission request bits in each of the MOTRA, MOTRB, MOTRC, and MOTRD
+ * Transmission Request Registers are set.
+ * 
+ * Register Layout
+ * 
+ *  Bits    | Access | Reset | Description
+ * :--------|:-------|:------|:------------
+ *  [0]     | R      | 0x0   | TxRqstA    
+ *  [1]     | R      | 0x0   | TxRqstA    
+ *  [2]     | R      | 0x0   | TxRqstA    
+ *  [3]     | R      | 0x0   | TxRqstA    
+ *  [4]     | R      | 0x0   | TxRqstB    
+ *  [5]     | R      | 0x0   | TxRqstB    
+ *  [6]     | R      | 0x0   | TxRqstB    
+ *  [7]     | R      | 0x0   | TxRqstB    
+ *  [8]     | R      | 0x0   | TxRqstC    
+ *  [9]     | R      | 0x0   | TxRqstC    
+ *  [10]    | R      | 0x0   | TxRqstC    
+ *  [11]    | R      | 0x0   | TxRqstC    
+ *  [12]    | R      | 0x0   | TxRqstD    
+ *  [13]    | R      | 0x0   | TxRqstD    
+ *  [14]    | R      | 0x0   | TxRqstD    
+ *  [15]    | R      | 0x0   | TxRqstD    
+ *  [31:16] | ???    | 0x0   | *UNDEFINED*
+ * 
+ */
+/*
+ * Field : TxRqstA - TxRqstA_0
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRA register. Array
+ * index i corresponds to byte i of the MOTRA register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRA are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRA are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0
+ * 
+ * The Message Objects in the corresponding byte of MOTRA are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRA are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_MSB        0
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : TxRqstA - TxRqstA_1
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRA register. Array
+ * index i corresponds to byte i of the MOTRA register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRA are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRA are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1
+ * 
+ * The Message Objects in the corresponding byte of MOTRA are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRA are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_MSB        1
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : TxRqstA - TxRqstA_2
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRA register. Array
+ * index i corresponds to byte i of the MOTRA register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRA are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRA are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2
+ * 
+ * The Message Objects in the corresponding byte of MOTRA are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRA are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_MSB        2
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : TxRqstA - TxRqstA_3
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRA register. Array
+ * index i corresponds to byte i of the MOTRA register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRA are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRA are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3
+ * 
+ * The Message Objects in the corresponding byte of MOTRA are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRA are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_MSB        3
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : TxRqstB - TxRqstB_0
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRB register. Array
+ * index i corresponds to byte i of the MOTRB register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRB are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRB are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0
+ * 
+ * The Message Objects in the corresponding byte of MOTRB are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRB are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_MSB        4
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : TxRqstB - TxRqstB_1
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRB register. Array
+ * index i corresponds to byte i of the MOTRB register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRB are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRB are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1
+ * 
+ * The Message Objects in the corresponding byte of MOTRB are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRB are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_MSB        5
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : TxRqstB - TxRqstB_2
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRB register. Array
+ * index i corresponds to byte i of the MOTRB register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRB are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRB are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2
+ * 
+ * The Message Objects in the corresponding byte of MOTRB are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRB are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_MSB        6
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : TxRqstB - TxRqstB_3
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRB register. Array
+ * index i corresponds to byte i of the MOTRB register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRB are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRB are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3
+ * 
+ * The Message Objects in the corresponding byte of MOTRB are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRB are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_MSB        7
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : TxRqstC - TxRqstC_0
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRC register. Array
+ * index i corresponds to byte i of the MOTRC register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRC are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRC are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0
+ * 
+ * The Message Objects in the corresponding byte of MOTRC are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRC are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_MSB        8
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : TxRqstC - TxRqstC_1
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRC register. Array
+ * index i corresponds to byte i of the MOTRC register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRC are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRC are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1
+ * 
+ * The Message Objects in the corresponding byte of MOTRC are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRC are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_MSB        9
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : TxRqstC - TxRqstC_2
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRC register. Array
+ * index i corresponds to byte i of the MOTRC register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRC are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRC are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2
+ * 
+ * The Message Objects in the corresponding byte of MOTRC are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRC are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_MSB        10
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_SET_MSK    0x00000400
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : TxRqstC - TxRqstC_3
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRC register. Array
+ * index i corresponds to byte i of the MOTRC register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRC are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRC are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3
+ * 
+ * The Message Objects in the corresponding byte of MOTRC are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRC are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_MSB        11
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_SET_MSK    0x00000800
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : TxRqstD - TxRqstD_0
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRD register. Array
+ * index i corresponds to byte i of the MOTRD register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRD are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRD are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0
+ * 
+ * The Message Objects in the corresponding byte of MOTRD are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRD are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_MSB        12
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_SET_MSK    0x00001000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_CLR_MSK    0xffffefff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : TxRqstD - TxRqstD_1
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRD register. Array
+ * index i corresponds to byte i of the MOTRD register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRD are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRD are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1
+ * 
+ * The Message Objects in the corresponding byte of MOTRD are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRD are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_MSB        13
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : TxRqstD - TxRqstD_2
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRD register. Array
+ * index i corresponds to byte i of the MOTRD register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRD are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRD are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2
+ * 
+ * The Message Objects in the corresponding byte of MOTRD are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRD are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_MSB        14
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : TxRqstD - TxRqstD_3
+ * 
+ * Each bit in this field is a logical OR of a byte of the MOTRD register. Array
+ * index i corresponds to byte i of the MOTRD register.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                                     
+ * :---------------------------------------------|:------|:-------------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_NOTWAITING | 0x0   | The Message Objects in the corresponding byte of
+ * :                                             |       | MOTRD are not waiting for transmission.         
+ *  ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_PENDING    | 0x1   | One or more of the transmission of the Message  
+ * :                                             |       | Objects in the corresponding byte of MOTRD are  
+ * :                                             |       | requested and are not yet done.                 
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3
+ * 
+ * The Message Objects in the corresponding byte of MOTRD are not waiting for
+ * transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3
+ * 
+ * One or more of the transmission of the Message Objects in the corresponding byte
+ * of MOTRD are requested and are not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_MSB        15
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_SET(value) (((value) << 15) & 0x00008000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_MSGHAND_MOTRX.
+ */
+struct ALT_CAN_MSGHAND_MOTRX_s
+{
+    const uint32_t  TxRqstA_0 :  1;  /* TxRqstA */
+    const uint32_t  TxRqstA_1 :  1;  /* TxRqstA */
+    const uint32_t  TxRqstA_2 :  1;  /* TxRqstA */
+    const uint32_t  TxRqstA_3 :  1;  /* TxRqstA */
+    const uint32_t  TxRqstB_0 :  1;  /* TxRqstB */
+    const uint32_t  TxRqstB_1 :  1;  /* TxRqstB */
+    const uint32_t  TxRqstB_2 :  1;  /* TxRqstB */
+    const uint32_t  TxRqstB_3 :  1;  /* TxRqstB */
+    const uint32_t  TxRqstC_0 :  1;  /* TxRqstC */
+    const uint32_t  TxRqstC_1 :  1;  /* TxRqstC */
+    const uint32_t  TxRqstC_2 :  1;  /* TxRqstC */
+    const uint32_t  TxRqstC_3 :  1;  /* TxRqstC */
+    const uint32_t  TxRqstD_0 :  1;  /* TxRqstD */
+    const uint32_t  TxRqstD_1 :  1;  /* TxRqstD */
+    const uint32_t  TxRqstD_2 :  1;  /* TxRqstD */
+    const uint32_t  TxRqstD_3 :  1;  /* TxRqstD */
+    uint32_t                  : 16;  /* *UNDEFINED* */
+};
+
+/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRX. */
+typedef volatile struct ALT_CAN_MSGHAND_MOTRX_s  ALT_CAN_MSGHAND_MOTRX_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_MSGHAND_MOTRX register from the beginning of the component. */
+#define ALT_CAN_MSGHAND_MOTRX_OFST        0x0
+/* The address of the ALT_CAN_MSGHAND_MOTRX register. */
+#define ALT_CAN_MSGHAND_MOTRX_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRX_OFST))
+
+/*
+ * Register : Transmission Request A Register - MOTRA
+ * 
+ * Transmission request bits for Message Objects 1 to 32.  By reading the TxRqst
+ * bits, the CPU can check for which Message Object a Transmission Request is
+ * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU
+ * via the IFx Message Interface Registers or set by the Message Handler after
+ * reception of a Remote Frame or reset by the Message Handler after a successful
+ * transmission.
+ * 
+ * Register Layout
+ * 
+ *  Bits | Access | Reset | Description
+ * :-----|:-------|:------|:------------
+ *  [0]  | R      | 0x0   | TxRqst32-1 
+ *  [1]  | R      | 0x0   | TxRqst32-1 
+ *  [2]  | R      | 0x0   | TxRqst32-1 
+ *  [3]  | R      | 0x0   | TxRqst32-1 
+ *  [4]  | R      | 0x0   | TxRqst32-1 
+ *  [5]  | R      | 0x0   | TxRqst32-1 
+ *  [6]  | R      | 0x0   | TxRqst32-1 
+ *  [7]  | R      | 0x0   | TxRqst32-1 
+ *  [8]  | R      | 0x0   | TxRqst32-1 
+ *  [9]  | R      | 0x0   | TxRqst32-1 
+ *  [10] | R      | 0x0   | TxRqst32-1 
+ *  [11] | R      | 0x0   | TxRqst32-1 
+ *  [12] | R      | 0x0   | TxRqst32-1 
+ *  [13] | R      | 0x0   | TxRqst32-1 
+ *  [14] | R      | 0x0   | TxRqst32-1 
+ *  [15] | R      | 0x0   | TxRqst32-1 
+ *  [16] | R      | 0x0   | TxRqst32-1 
+ *  [17] | R      | 0x0   | TxRqst32-1 
+ *  [18] | R      | 0x0   | TxRqst32-1 
+ *  [19] | R      | 0x0   | TxRqst32-1 
+ *  [20] | R      | 0x0   | TxRqst32-1 
+ *  [21] | R      | 0x0   | TxRqst32-1 
+ *  [22] | R      | 0x0   | TxRqst32-1 
+ *  [23] | R      | 0x0   | TxRqst32-1 
+ *  [24] | R      | 0x0   | TxRqst32-1 
+ *  [25] | R      | 0x0   | TxRqst32-1 
+ *  [26] | R      | 0x0   | TxRqst32-1 
+ *  [27] | R      | 0x0   | TxRqst32-1 
+ *  [28] | R      | 0x0   | TxRqst32-1 
+ *  [29] | R      | 0x0   | TxRqst32-1 
+ *  [30] | R      | 0x0   | TxRqst32-1 
+ *  [31] | R      | 0x0   | TxRqst32-1 
+ * 
+ */
+/*
+ * Field : TxRqst32-1 - TxRqst_0
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_0
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_0
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_MSB        0
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_1
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_1
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_1
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_MSB        1
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_2
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_2
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_2
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_MSB        2
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_3
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_3
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_3
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_MSB        3
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_4
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_4
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_4
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_MSB        4
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_5
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_5
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_5
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_MSB        5
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_6
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_6
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_6
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_MSB        6
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_7
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_7
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_7
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_MSB        7
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_8
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_8
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_8
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_MSB        8
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_9
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_9
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_9
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_MSB        9
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_10
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_10
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_10
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_MSB        10
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_SET_MSK    0x00000400
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_11
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_11
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_11
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_MSB        11
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_SET_MSK    0x00000800
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_12
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_12
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_12
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_MSB        12
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_SET_MSK    0x00001000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_CLR_MSK    0xffffefff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_13
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_13
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_13
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_MSB        13
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_14
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_14
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_14
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_MSB        14
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_15
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_15
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_15
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_MSB        15
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_16
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_16
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_16
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_MSB        16
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_SET_MSK    0x00010000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_CLR_MSK    0xfffeffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_SET(value) (((value) << 16) & 0x00010000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_17
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_17
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_17
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_MSB        17
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_SET_MSK    0x00020000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_18
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_18
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_18
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_MSB        18
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_SET_MSK    0x00040000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_19
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_19
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_19
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_MSB        19
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_SET_MSK    0x00080000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_SET(value) (((value) << 19) & 0x00080000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_20
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_20
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_20
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_MSB        20
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_SET_MSK    0x00100000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_CLR_MSK    0xffefffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_SET(value) (((value) << 20) & 0x00100000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_21
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_21
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_21
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_LSB        21
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_MSB        21
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_SET_MSK    0x00200000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_CLR_MSK    0xffdfffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_SET(value) (((value) << 21) & 0x00200000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_22
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_22
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_22
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_MSB        22
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_SET_MSK    0x00400000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_CLR_MSK    0xffbfffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_SET(value) (((value) << 22) & 0x00400000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_23
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_23
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_23
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_LSB        23
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_MSB        23
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_SET_MSK    0x00800000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_CLR_MSK    0xff7fffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_SET(value) (((value) << 23) & 0x00800000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_24
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_24
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_24
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_MSB        24
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_SET_MSK    0x01000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_25
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_25
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_25
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_MSB        25
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_SET_MSK    0x02000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_CLR_MSK    0xfdffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_SET(value) (((value) << 25) & 0x02000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_26
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_26
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_26
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_LSB        26
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_MSB        26
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_SET_MSK    0x04000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_CLR_MSK    0xfbffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_SET(value) (((value) << 26) & 0x04000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_27
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_27
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_27
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_LSB        27
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_MSB        27
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_SET_MSK    0x08000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_CLR_MSK    0xf7ffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_SET(value) (((value) << 27) & 0x08000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_28
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_28
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_28
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_LSB        28
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_MSB        28
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_SET_MSK    0x10000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_CLR_MSK    0xefffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_SET(value) (((value) << 28) & 0x10000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_29
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_29
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_29
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_LSB        29
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_MSB        29
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_SET_MSK    0x20000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_CLR_MSK    0xdfffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_SET(value) (((value) << 29) & 0x20000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_30
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_30
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_30
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_LSB        30
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_MSB        30
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_SET_MSK    0x40000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_CLR_MSK    0xbfffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_SET(value) (((value) << 30) & 0x40000000)
+
+/*
+ * Field : TxRqst32-1 - TxRqst_31
+ * 
+ * Transmission request bits for Message Objects 1 to 32. Array index i corresponds
+ * to Message Object i+1.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_31
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_31
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_MSB        31
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_SET_MSK    0x80000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_MSGHAND_MOTRA.
+ */
+struct ALT_CAN_MSGHAND_MOTRA_s
+{
+    const uint32_t  TxRqst_0  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_1  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_2  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_3  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_4  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_5  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_6  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_7  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_8  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_9  :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_10 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_11 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_12 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_13 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_14 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_15 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_16 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_17 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_18 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_19 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_20 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_21 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_22 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_23 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_24 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_25 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_26 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_27 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_28 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_29 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_30 :  1;  /* TxRqst32-1 */
+    const uint32_t  TxRqst_31 :  1;  /* TxRqst32-1 */
+};
+
+/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRA. */
+typedef volatile struct ALT_CAN_MSGHAND_MOTRA_s  ALT_CAN_MSGHAND_MOTRA_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_MSGHAND_MOTRA register from the beginning of the component. */
+#define ALT_CAN_MSGHAND_MOTRA_OFST        0x4
+/* The address of the ALT_CAN_MSGHAND_MOTRA register. */
+#define ALT_CAN_MSGHAND_MOTRA_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRA_OFST))
+
+/*
+ * Register : Transmission Request B Register - MOTRB
+ * 
+ * Transmission request bits for Message Objects 33 to 64.  By reading the TxRqst
+ * bits, the CPU can check for which Message Object a Transmission Request is
+ * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU
+ * via the IFx Message Interface Registers or set by the Message Handler after
+ * reception of a Remote Frame or reset by the Message Handler after a successful
+ * transmission.
+ * 
+ * Register Layout
+ * 
+ *  Bits | Access | Reset | Description
+ * :-----|:-------|:------|:------------
+ *  [0]  | R      | 0x0   | TxRqst64-33
+ *  [1]  | R      | 0x0   | TxRqst64-33
+ *  [2]  | R      | 0x0   | TxRqst64-33
+ *  [3]  | R      | 0x0   | TxRqst64-33
+ *  [4]  | R      | 0x0   | TxRqst64-33
+ *  [5]  | R      | 0x0   | TxRqst64-33
+ *  [6]  | R      | 0x0   | TxRqst64-33
+ *  [7]  | R      | 0x0   | TxRqst64-33
+ *  [8]  | R      | 0x0   | TxRqst64-33
+ *  [9]  | R      | 0x0   | TxRqst64-33
+ *  [10] | R      | 0x0   | TxRqst64-33
+ *  [11] | R      | 0x0   | TxRqst64-33
+ *  [12] | R      | 0x0   | TxRqst64-33
+ *  [13] | R      | 0x0   | TxRqst64-33
+ *  [14] | R      | 0x0   | TxRqst64-33
+ *  [15] | R      | 0x0   | TxRqst64-33
+ *  [16] | R      | 0x0   | TxRqst64-33
+ *  [17] | R      | 0x0   | TxRqst64-33
+ *  [18] | R      | 0x0   | TxRqst64-33
+ *  [19] | R      | 0x0   | TxRqst64-33
+ *  [20] | R      | 0x0   | TxRqst64-33
+ *  [21] | R      | 0x0   | TxRqst64-33
+ *  [22] | R      | 0x0   | TxRqst64-33
+ *  [23] | R      | 0x0   | TxRqst64-33
+ *  [24] | R      | 0x0   | TxRqst64-33
+ *  [25] | R      | 0x0   | TxRqst64-33
+ *  [26] | R      | 0x0   | TxRqst64-33
+ *  [27] | R      | 0x0   | TxRqst64-33
+ *  [28] | R      | 0x0   | TxRqst64-33
+ *  [29] | R      | 0x0   | TxRqst64-33
+ *  [30] | R      | 0x0   | TxRqst64-33
+ *  [31] | R      | 0x0   | TxRqst64-33
+ * 
+ */
+/*
+ * Field : TxRqst64-33 - TxRqst_0
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_0
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_0
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_MSB        0
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_1
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_1
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_1
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_MSB        1
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_2
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_2
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_2
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_MSB        2
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_3
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_3
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_3
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_MSB        3
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_4
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_4
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_4
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_MSB        4
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_5
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_5
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_5
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_MSB        5
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_6
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_6
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_6
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_MSB        6
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_7
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_7
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_7
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_MSB        7
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_8
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_8
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_8
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_MSB        8
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_9
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_9
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_9
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_MSB        9
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_10
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_10
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_10
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_MSB        10
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_SET_MSK    0x00000400
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_11
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_11
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_11
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_MSB        11
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_SET_MSK    0x00000800
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_12
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_12
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_12
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_MSB        12
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_SET_MSK    0x00001000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_CLR_MSK    0xffffefff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_13
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_13
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_13
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_MSB        13
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_14
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_14
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_14
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_MSB        14
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_15
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_15
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_15
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_MSB        15
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_16
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_16
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_16
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_MSB        16
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_SET_MSK    0x00010000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_CLR_MSK    0xfffeffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_SET(value) (((value) << 16) & 0x00010000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_17
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_17
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_17
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_MSB        17
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_SET_MSK    0x00020000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_18
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_18
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_18
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_MSB        18
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_SET_MSK    0x00040000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_19
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_19
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_19
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_MSB        19
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_SET_MSK    0x00080000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_SET(value) (((value) << 19) & 0x00080000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_20
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_20
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_20
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_MSB        20
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_SET_MSK    0x00100000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_CLR_MSK    0xffefffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_SET(value) (((value) << 20) & 0x00100000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_21
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_21
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_21
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_LSB        21
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_MSB        21
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_SET_MSK    0x00200000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_CLR_MSK    0xffdfffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_SET(value) (((value) << 21) & 0x00200000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_22
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_22
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_22
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_MSB        22
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_SET_MSK    0x00400000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_CLR_MSK    0xffbfffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_SET(value) (((value) << 22) & 0x00400000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_23
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_23
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_23
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_LSB        23
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_MSB        23
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_SET_MSK    0x00800000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_CLR_MSK    0xff7fffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_SET(value) (((value) << 23) & 0x00800000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_24
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_24
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_24
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_LSB        24
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_MSB        24
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_SET_MSK    0x01000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_CLR_MSK    0xfeffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_SET(value) (((value) << 24) & 0x01000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_25
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_25
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_25
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_LSB        25
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_MSB        25
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_SET_MSK    0x02000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_CLR_MSK    0xfdffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_SET(value) (((value) << 25) & 0x02000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_26
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_26
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_26
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_LSB        26
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_MSB        26
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_SET_MSK    0x04000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_CLR_MSK    0xfbffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_SET(value) (((value) << 26) & 0x04000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_27
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_27
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_27
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_LSB        27
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_MSB        27
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_SET_MSK    0x08000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_CLR_MSK    0xf7ffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_SET(value) (((value) << 27) & 0x08000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_28
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_28
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_28
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_LSB        28
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_MSB        28
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_SET_MSK    0x10000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_CLR_MSK    0xefffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_SET(value) (((value) << 28) & 0x10000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_29
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_29
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_29
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_LSB        29
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_MSB        29
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_SET_MSK    0x20000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_CLR_MSK    0xdfffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_SET(value) (((value) << 29) & 0x20000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_30
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_30
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_30
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_LSB        30
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_MSB        30
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_SET_MSK    0x40000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_CLR_MSK    0xbfffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_SET(value) (((value) << 30) & 0x40000000)
+
+/*
+ * Field : TxRqst64-33 - TxRqst_31
+ * 
+ * Transmission request bits for Message Objects 33 to 64. Array index i
+ * corresponds to Message Object i+33.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_31
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_31
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_LSB        31
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_MSB        31
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_SET_MSK    0x80000000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_CLR_MSK    0x7fffffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ * 
+ * The struct declaration for register ALT_CAN_MSGHAND_MOTRB.
+ */
+struct ALT_CAN_MSGHAND_MOTRB_s
+{
+    const uint32_t  TxRqst_0  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_1  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_2  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_3  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_4  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_5  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_6  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_7  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_8  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_9  :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_10 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_11 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_12 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_13 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_14 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_15 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_16 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_17 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_18 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_19 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_20 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_21 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_22 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_23 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_24 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_25 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_26 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_27 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_28 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_29 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_30 :  1;  /* TxRqst64-33 */
+    const uint32_t  TxRqst_31 :  1;  /* TxRqst64-33 */
+};
+
+/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRB. */
+typedef volatile struct ALT_CAN_MSGHAND_MOTRB_s  ALT_CAN_MSGHAND_MOTRB_t;
+#endif  /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_CAN_MSGHAND_MOTRB register from the beginning of the component. */
+#define ALT_CAN_MSGHAND_MOTRB_OFST        0x8
+/* The address of the ALT_CAN_MSGHAND_MOTRB register. */
+#define ALT_CAN_MSGHAND_MOTRB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRB_OFST))
+
+/*
+ * Register : Transmission Request C Register - MOTRC
+ * 
+ * Transmission request bits for Message Objects 65 to 96.  By reading the TxRqst
+ * bits, the CPU can check for which Message Object a Transmission Request is
+ * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU
+ * via the IFx Message Interface Registers or set by the Message Handler after
+ * reception of a Remote Frame or reset by the Message Handler after a successful
+ * transmission.
+ * 
+ * Register Layout
+ * 
+ *  Bits | Access | Reset | Description
+ * :-----|:-------|:------|:------------
+ *  [0]  | R      | 0x0   | TxRqst96-65
+ *  [1]  | R      | 0x0   | TxRqst96-65
+ *  [2]  | R      | 0x0   | TxRqst96-65
+ *  [3]  | R      | 0x0   | TxRqst96-65
+ *  [4]  | R      | 0x0   | TxRqst96-65
+ *  [5]  | R      | 0x0   | TxRqst96-65
+ *  [6]  | R      | 0x0   | TxRqst96-65
+ *  [7]  | R      | 0x0   | TxRqst96-65
+ *  [8]  | R      | 0x0   | TxRqst96-65
+ *  [9]  | R      | 0x0   | TxRqst96-65
+ *  [10] | R      | 0x0   | TxRqst96-65
+ *  [11] | R      | 0x0   | TxRqst96-65
+ *  [12] | R      | 0x0   | TxRqst96-65
+ *  [13] | R      | 0x0   | TxRqst96-65
+ *  [14] | R      | 0x0   | TxRqst96-65
+ *  [15] | R      | 0x0   | TxRqst96-65
+ *  [16] | R      | 0x0   | TxRqst96-65
+ *  [17] | R      | 0x0   | TxRqst96-65
+ *  [18] | R      | 0x0   | TxRqst96-65
+ *  [19] | R      | 0x0   | TxRqst96-65
+ *  [20] | R      | 0x0   | TxRqst96-65
+ *  [21] | R      | 0x0   | TxRqst96-65
+ *  [22] | R      | 0x0   | TxRqst96-65
+ *  [23] | R      | 0x0   | TxRqst96-65
+ *  [24] | R      | 0x0   | TxRqst96-65
+ *  [25] | R      | 0x0   | TxRqst96-65
+ *  [26] | R      | 0x0   | TxRqst96-65
+ *  [27] | R      | 0x0   | TxRqst96-65
+ *  [28] | R      | 0x0   | TxRqst96-65
+ *  [29] | R      | 0x0   | TxRqst96-65
+ *  [30] | R      | 0x0   | TxRqst96-65
+ *  [31] | R      | 0x0   | TxRqst96-65
+ * 
+ */
+/*
+ * Field : TxRqst96-65 - TxRqst_0
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_0
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_0
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_LSB        0
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_MSB        0
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_SET_MSK    0x00000001
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_CLR_MSK    0xfffffffe
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_SET(value) (((value) << 0) & 0x00000001)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_1
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_1
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_1
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_LSB        1
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_MSB        1
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_SET_MSK    0x00000002
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_CLR_MSK    0xfffffffd
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_SET(value) (((value) << 1) & 0x00000002)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_2
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_2
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_2
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_LSB        2
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_MSB        2
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_SET_MSK    0x00000004
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_CLR_MSK    0xfffffffb
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_SET(value) (((value) << 2) & 0x00000004)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_3
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_3
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_3
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_LSB        3
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_MSB        3
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_SET_MSK    0x00000008
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_CLR_MSK    0xfffffff7
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_SET(value) (((value) << 3) & 0x00000008)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_4
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_4
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_4
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_LSB        4
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_MSB        4
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_SET_MSK    0x00000010
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_CLR_MSK    0xffffffef
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_SET(value) (((value) << 4) & 0x00000010)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_5
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_5
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_5
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_LSB        5
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_MSB        5
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_SET_MSK    0x00000020
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_CLR_MSK    0xffffffdf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_SET(value) (((value) << 5) & 0x00000020)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_6
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_6
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_6
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_LSB        6
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_MSB        6
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_SET_MSK    0x00000040
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_CLR_MSK    0xffffffbf
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_SET(value) (((value) << 6) & 0x00000040)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_7
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_7
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_7
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_LSB        7
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_MSB        7
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_SET_MSK    0x00000080
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_CLR_MSK    0xffffff7f
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_SET(value) (((value) << 7) & 0x00000080)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_8
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_8
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_8
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_LSB        8
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_MSB        8
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_SET_MSK    0x00000100
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_CLR_MSK    0xfffffeff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_SET(value) (((value) << 8) & 0x00000100)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_9
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                        | Value | Description                               
+ * :--------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                            |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                            |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_9
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_NOTWAITING 0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_9
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_PENDING    0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_LSB        9
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_MSB        9
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_SET_MSK    0x00000200
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_CLR_MSK    0xfffffdff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_SET(value) (((value) << 9) & 0x00000200)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_10
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_10
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_10
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_LSB        10
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_MSB        10
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_SET_MSK    0x00000400
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_CLR_MSK    0xfffffbff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_SET(value) (((value) << 10) & 0x00000400)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_11
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_11
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_11
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_LSB        11
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_MSB        11
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_SET_MSK    0x00000800
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_CLR_MSK    0xfffff7ff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_SET(value) (((value) << 11) & 0x00000800)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_12
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_12
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_12
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_LSB        12
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_MSB        12
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_SET_MSK    0x00001000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_CLR_MSK    0xffffefff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_SET(value) (((value) << 12) & 0x00001000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_13
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_13
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_13
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_LSB        13
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_MSB        13
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_SET_MSK    0x00002000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_CLR_MSK    0xffffdfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_SET(value) (((value) << 13) & 0x00002000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_14
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_14
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_14
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_LSB        14
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_MSB        14
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_SET_MSK    0x00004000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_CLR_MSK    0xffffbfff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_SET(value) (((value) << 14) & 0x00004000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_15
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_15
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_15
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_LSB        15
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_MSB        15
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_SET_MSK    0x00008000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_CLR_MSK    0xffff7fff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_SET(value) (((value) << 15) & 0x00008000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_16
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_16
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_16
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_LSB        16
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_MSB        16
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_SET_MSK    0x00010000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_CLR_MSK    0xfffeffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_SET(value) (((value) << 16) & 0x00010000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_17
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_17
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_17
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_LSB        17
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_MSB        17
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_SET_MSK    0x00020000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_CLR_MSK    0xfffdffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_SET(value) (((value) << 17) & 0x00020000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_18
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_18
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_18
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_LSB        18
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_MSB        18
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_SET_MSK    0x00040000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_CLR_MSK    0xfffbffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_SET(value) (((value) << 18) & 0x00040000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_19
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_19
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_19
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_LSB        19
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_MSB        19
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_SET_MSK    0x00080000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_CLR_MSK    0xfff7ffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_SET(value) (((value) << 19) & 0x00080000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_20
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_20
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_20
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_LSB        20
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_MSB        20
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_SET_MSK    0x00100000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_CLR_MSK    0xffefffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_SET(value) (((value) << 20) & 0x00100000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_21
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_21
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_21
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_LSB        21
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_MSB        21
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_WIDTH      1
+/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_SET_MSK    0x00200000
+/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_CLR_MSK    0xffdfffff
+/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_RESET      0x0
+/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 field value from a register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21)
+/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value suitable for setting the register. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_SET(value) (((value) << 21) & 0x00200000)
+
+/*
+ * Field : TxRqst96-65 - TxRqst_22
+ * 
+ * Transmission request bits for Message Objects 65 to 96. Array index i
+ * corresponds to Message Object i+65.
+ * 
+ * Field Enumeration Values:
+ * 
+ *  Enum                                         | Value | Description                               
+ * :---------------------------------------------|:------|:-------------------------------------------
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_NOTWAITING | 0x0   | This Message Object is not waiting for    
+ * :                                             |       | transmission.                             
+ *  ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_PENDING    | 0x1   | The transmission of this Message Object is
+ * :                                             |       | requested and is not yet done.            
+ * 
+ * Field Access Macros:
+ * 
+ */
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_22
+ * 
+ * This Message Object is not waiting for transmission.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_NOTWAITING    0x0
+/*
+ * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_22
+ * 
+ * The transmission of this Message Object is requested and is not yet done.
+ */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_PENDING       0x1
+
+/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_LSB        22
+/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */
+#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_MSB        22
+/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 re