sleep time is doubled, xilinx_zynq_zedboard

[Giovanni Macciocu]

There is only one type of zynz zedboard
(http://www.zedboard.org/product/zedboard). This board has the
Zynq®-7000 All Programmable SoC XC7Z020-CLG484-1 
which runs at a default clock speed of 666 MHz. This can be downscaled
ofcourse but not upgraded. Maximum and default clock speed is thus 
666MHz. 

The value of BSP_ARM9MPCORE_PERIPHCLK can thus never be 666666667U as
this is equal to the max. clock speed, the ARM documentation states that
PERIPHCLK must be synchronous with CLK, 
and that the PERIPHCLK clock period, N, must be configured as a
multiple of the CLK clock period.


>>> Joel Sherrill <Joel.Sherrill at OARcorp.com> 5/1/2014 3:03 PM >>> 

On May 1, 2014 7:35 AM, Thomas Doerfler
<Thomas.Doerfler at embedded-brains.de> wrote:
>
> Giovanni,
>
> without knowing the BSP: You are talking about CPU clock, the macro
is
> call Periphclk. Can it be that the peripheral bus is clocked with
half
> of the CPU frequency?

In was thinking something similar Thomas (also in ignorance of this
specific BSP). The main frequency may be correct but their may be two
independent divider settings which can vary per implementation. This is
"soft" hardware and could have a lot if potential tweak points. The BSP
may or may not have the defaults to match your board instance and may or
may not address all potential tweak points yet.

Are there dividers?

--joel

> wkr,
>
> Thomas.
>
> Am 01.05.2014 12:52, schrieb Giovanni Macciocu:
> > I've made some tests by changing the value of 
BSP_ARM_A9MPCORE_PERIPHCLK.
> > The value should be 666666667U as this is my cpu clock speed.
> >
> > However in the following cases
> >
> > #define BSP_ARM_A9MPCORE_PERIPHCLK (2 * 666666667U)
> >
> > --> a Sleep now takes 4 times as long
> >
> > #define BSP_ARM_A9MPCORE_PERIPHCLK 2 (666666667U / 2)
> >
> > --> The sleep is now correct
> >
> > In all cases the serial port keeps working at half of the normal
buadrate.
> >
> > Regards,
> >
> > Giovanni
> >
> >
> >>>> "Giovanni Macciocu" <G.Macciocu at sron.nl> 5/1/2014 10:53 AM >>>
> > In my bspopt.h
> >
> > /* ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz */
> > #define BSP_ARM_A9MPCORE_PERIPHCLK 666666667U
> >
> > This is the correct processor speed for my platform.
> >
> >>>> Chris Johns <chrisj at rtems.org> 5/1/2014 10:24 AM >>>
> > t you take a look at the BSPOPTS for the zync BSP. There are
> > some clocks you can set and one of these may help. I think
> > BSP_ARM_A9MPCORE_PERIPHCLK is the one.
> >
> > Chris
> >
> >
> >
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> >
> >
> >
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>
>
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