[GSOC] RPi BSP memory barrier

[Sebastian Huber]

On 2014-05-08 18:51, Andre Marques wrote:
> On 05/05/14 11:50, Sebastian Huber wrote:
>> On 2014-05-05 12:43, Andre Marques wrote:
>>>
>>> Any thoughts on this?
>>
>> Why not use C11 atomic operations?
>>
>
> Well, I didn't know they existed, thank you!
>
> Since I have not used them before, please check if I'm thinking this right.
>
> 1. Include rtems/score/atomic.h
>
> 2. Initialize variable with ATOMIC_INITIALIZER_* as per
>
> http://www.rtems.org/onlinedocs/doxygen/cpukit/html/group__RTEMS.html#ga676563e3ec750e9faa2727eea8ed99e1
>
> 3. Use _Atomic_Load_* to read the variable value and _Atomic_Store_* to set a
> new value to the variable
>
> 4. As for memory models I'm thinking in using ATOMIC_ORDER_ACQUIRE to load and
> ATOMIC_ORDER_RELEASE to store.

You can also use the _Atomic_Fence() in some situations.  If you work with 
devices, then the C11 atomic operations may be not sufficient.

In cpu.h we have on the ARM:

static inline void _ARM_Data_memory_barrier( void )
{
   __asm__ volatile ( "dmb" : : : "memory" );
}

static inline void _ARM_Data_synchronization_barrier( void )
{
   __asm__ volatile ( "dsb" : : : "memory" );
}

static inline void _ARM_Instruction_synchronization_barrier( void )
{
   __asm__ volatile ( "isb" : : : "memory" );
}


-- 
Sebastian Huber, embedded brains GmbH

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