[PATCH] (2 commits squashed into one) Beagle BSP for review

Ben Gras beng at shrike-systems.com
Mon Nov 3 19:40:18 UTC 2014


All,

I have new patches with some last-minute smoothings added; removed obsolete
beagle.cfg, TODO, and separated the more generic ARM headers into a
separate commit. The new 3 commits are attached (and in my RTEMS github
repo).

Gedare, there is also a diff w.r.t. the previous submission attached as
requested.



On Mon, Nov 3, 2014 at 3:01 PM, Gedare Bloom <gedare at rtems.org> wrote:

> Hi,
>
> I don't have time to review, but am OK in principle with committing
> this code as it is tested, with the caveat that my previous comments
> be addressed post-merge.
>
> If you have a diff / commits on top of what you sent before, I'd be
> glad to give those a quick look.
>
> Thanks for your contribution!
> Gedare
>
> On Mon, Nov 3, 2014 at 7:20 AM, Ben Gras <beng at shrike-systems.com> wrote:
> > All,
> >
> > Ok, as promised, I rebased and re-tested and have found & included a
> > portable way of making the SD card image (included in sdcard.sh), to be
> > merged with RSB (i.e. some of the tools sdcard.sh relies on are missing
> in
> > mainline RSB). Some of Gedare's initial feedback is processed thanks to
> > Brandon Matthews. It's tested to run on the original beaglebone,
> beaglebone
> > black and qemu linaro. (The assumption is it'll run on the bbxm hardware
> as
> > well as it was before rebasing.)
> >
> > The result is split into 2 patches to show what was Claas's initial work.
> > This makes them a bit unreadable for the final result from the patches
> > unfortunately.
> >
> > As before, see
> >
> http://www.shrike-systems.com/beagleboard-xm-beaglebone-black-and-everything-else-rtems-on-the-beagles.html
> > on how to build all the tools, RTEMS executables, sdcard images, and run
> the
> > test set from linaro qemu.
> >
> >
> >
> > On Sat, Aug 30, 2014 at 5:50 PM, Ben Gras <beng at shrike-systems.com>
> wrote:
> >>
> >> All,
> >>
> >> OK, that seems like a fruitful way to proceed to me.
> >>
> >> Then I will do some minor cleanups, rebase, do all the tests again, and
> >> re-submit. There's just one problem I know of that I want to fix before
> the
> >> first commit happens, and that is that the FAT fs made by mtools doesn't
> >> boot on the HW it seems. (It does on the emulator.) A last-minute
> change -
> >> switching to mtools instead of dosfstools to use to make the SD card
> image
> >> because the latter is so linux-only.
> >>
> >> Stay tuned.
> >>
> >>
> >>
> >>
> >> On Wed, Aug 20, 2014 at 4:20 PM, Gedare Bloom <gedare at rtems.org> wrote:
> >>>
> >>> Ben, As far as getting this merged, all of my comments can be done as
> >>> a follow-on commit. -Gedare
> >>>
> >>> On Thu, Jul 24, 2014 at 4:28 PM, Ben Gras <beng at shrike-systems.com>
> >>> wrote:
> >>> > Thanks for the fast & detailed review. Let me get back to it/you.
> >>> >
> >>> > In the meantime, any other feedback? From anyone I mean.
> >>> >
> >>> >
> >>> >
> >>> > On Thu, Jul 24, 2014 at 4:45 PM, Gedare Bloom <gedare at rtems.org>
> wrote:
> >>> >>
> >>> >> Hi Ben,
> >>> >> Great work. I have a few comments. I skipped the i2c.h and i2c.c
> >>> >> files. Most of my comments are about style and a few requests to
> >>> >> refactor some of the larger files. The refactoring can be added to
> >>> >> your TODO if you like. Please fix the style issues if it is not a
> >>> >> burden.
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/README
> >>> >> +$ ../claas-rtems/configure --target=arm-rtems4.11
> >>> >> --enable-rtemsbsp="beaglebonewhite beagleboardxm"
> >>> >> Replace claas-rtems with rtems. If RSB support is available, make a
> >>> >> note about it.
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/TODO
> >>> >> [...]
> >>> >> open:
> >>> >> + . how to handle the interrupt?
> >>> >>
> >>> >> What does this mean?
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/clock.c
> >>> >> Why is the entire file ifdef'd on ARM_MULTILIB_ARCH_V4?
> >>> >>
> >>> >> It might be sensible to put the struct definitions in a .h file if
> >>> >> these omap registers might be re-usable.
> >>> >>
> >>> >> +static struct omap_timer_registers regs_v2 = {
> >>> >> This might be better to put behind an #if IS_AM335X since it is not
> >>> >> used otherwise?
> >>> >>
> >>> >> +
> >>> >> +
> >>> >> +
> >>> >> Avoid more than one blank line in a row.
> >>> >>
> >>> >> +static int done = 0;
> >>> >> It would be nice if you got rid of this, but otherwise give it a
> more
> >>> >> useful name like "mmio_init_done"
> >>> >>
> >>> >> +static void beagle_clock_handler_install(rtems_interrupt_handler
> isr)
> >>> >> +  if (sc != RTEMS_SUCCESSFUL) {
> >>> >> +    rtems_fatal_error_occurred(0xdeadbeef);
> >>> >> I think there is some capabilities in ARM for bsp fatal error codes
> >>> >> now. They should be preferred to be used to help debug these fatal
> >>> >> conditions.
> >>> >>
> >>> >> +static inline uint32_t
> beagle_clock_nanoseconds_since_last_tick(void)
> >>> >> +  return (read_frc() - (uint64_t) last_tick_nanoseconds) *
> 1000000000
> >>> >> / FRCLOCK_HZ;
> >>> >> This line is > 80 characters, please break it or shrink it.
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/console/console-config.c
> >>> >> +#define CONSOLE_UART_LSR (*(volatile unsigned int
> >>> >> *)(BSP_CONSOLE_UART_BASE+0x14))
> >>> >> Line > 80 characters, even with the spacing modified.
> >>> >>
> >>> >> +static void beagle_console_init(void)
> >>> >>
> >>> >> +    while ((CONSOLE_SYSS & 1) == 0)
> >>> >> +      ;
> >>> >> Is this a fatal loop or is it waiting for hardware to clear
> something?
> >>> >>
> >>> >> +    if ((CONSOLE_LSR & (CONSOLE_LSR_THRE | CONSOLE_LSR_TEMT)) ==
> >>> >> CONSOLE_LSR_THRE) {
> >>> >> Again > 80 characters. Is the test logically equivalent to: if (
> >>> >> (CONSOLE_LSR & CONSOLE_LSR_THRE) == CONSOLE_LSR_THRE)
> >>> >>
> >>> >> +    while ((CONSOLE_LSR & CONSOLE_LSR_TEMT) == 0)
> >>> >> +      ;
> >>> >> Is this a fatal loop or is it waiting for hardware?
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/include/bsp.h
> >>> >> This bsp.h is really long. Probably it should be refactored into
> other
> >>> >> headers, including non-public ones.
> >>> >>
> >>> >> +static inline void dsb(void)
> >>> >> +{
> >>> >> +        asm volatile("dsb" : : : "memory");
> >>> >> Fix the indentation.
> >>> >>
> >>> >> +static inline void flush_data_cache(void)
> >>> >> Perhaps this should be using _CPU_cache_flush_entire_data()? Perhaps
> >>> >> there is a difference in that the cache manager code flushes and
> >>> >> "cleans" the cache...
> >>> >>
> >>> >> +
> >>> >> +
> >>> >> +
> >>> >> +
> >>> >> Excess newlines. Done a few places in this file.
> >>> >>
> >>> >> The comments following the defines for various AM33X_INT_ values go
> >>> >> off the end of the 80 column character width. Same for some other
> >>> >> comments following defines for OMAP3_TIMER, AM33X_DMTIMER1, and
> >>> >> AM335X_TIMER_. And further below for the CM_ WKUP and CM_PER_TIMER7
> >>> >> defines, and CLKSEL_TIMER1MS_CLK_SEL_SEL5.
> >>> >>
> >>> >> +#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot
> mode
> >>> >> */
> >>> >> +#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
> >>> >> +#define OMAP3_TCLR_PTV      2
> >>> >> This PTV is odd compared to the other defines here. Is it 2 ==
> (1<<1),
> >>> >> or is there a typo here?
> >>> >>
> >>> >> Tabs are used in the OMAP3_CM_ defines, it should be space
> characters.
> >>> >> Also tabs are used in the read/write actlr, ttbcr, dacr, rrbr0
> >>> >> functions and the refresh_tlb function.
> >>> >>
> >>> >> +/* i2c stuff */
> >>> >> +typedef struct {
> >>> >> ...
> >>> >> +} beagle_i2c;
> >>> >> Shouldn't this go in beagle/include/i2c.h?
> >>> >>
> >>> >> All of this mmu handling code should be refactored. Where possible,
> it
> >>> >> should use the existing code in arm-cp15.h
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/include/i2c.h
> >>> >> This header defines static, non-inline functions. This doesn't make
> >>> >> sense.
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/irq.c
> >>> >> +static int irqs_enabled[BSP_INTERRUPT_VECTOR_MAX+1];
> >>> >> This is an array of 512 bytes. You could use a bit vector
> comprising 4
> >>> >> unsigned ints for the same purpose.
> >>> >>
> >>> >> +volatile static int level = 0;
> >>> >> Unused variable?
> >>> >>
> >>> >> +static uint32_t get_mir_reg(int vector, uint32_t *mask)
> >>> >> +  if(vector <   0) while(1) ;
> >>> >> Make this a fatal error?
> >>> >>
> >>> >> +  if(vector <  32) return OMAP3_INTCPS_MIR0;
> >>> >> +  if(vector <  32) return OMAP3_INTCPS_MIR0;
> >>> >> duplicate code.
> >>> >>
> >>> >> +  while(1) ;
> >>> >> Make this a fatal error?
> >>> >>
> >>> >> +rtems_status_code bsp_interrupt_facility_initialize(void)
> >>> >> +  mmio_write(omap_intr.base + OMAP3_INTCPS_SYSCONFIG,
> >>> >> OMAP3_SYSCONFIG_AUTOIDLE);
> >>> >> Line length > 80.
> >>> >>
> >>> >> +++ b/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
> >>> >>
> >>> >> +//static uint32_t pagetable[ARM_SECTIONS] __attribute__((aligned
> >>> >> (1024*16)));
> >>> >> commented-out.. delete it?
> >>> >>
> >>> >> +BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void)
> >>> >> __attribute__ ((weak));
> >>> >> More than 80 characters.
> >>> >>
> >>> >> diff --git a/c/src/lib/libbsp/bfin/acinclude.m4
> >>> >> b/c/src/lib/libbsp/bfin/acinclude.m4
> >>> >> index ab6082e..828fd89 100644
> >>> >> --- a/c/src/lib/libbsp/bfin/acinclude.m4
> >>> >> +++ b/c/src/lib/libbsp/bfin/acinclude.m4
> >>> >> diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4
> >>> >> b/c/src/lib/libbsp/powerpc/acinclude.m4
> >>> >> index 6442399..e46fa2b 100644
> >>> >> --- a/c/src/lib/libbsp/powerpc/acinclude.m4
> >>> >> +++ b/c/src/lib/libbsp/powerpc/acinclude.m4
> >>> >> Don't include these changes. Check your tool versions, and if the
> >>> >> correct version of tools does this, provide a separate patch for
> >>> >> generated files.
> >>> >>
> >>> >> -Gedare
> >>> >>
> >>> >> On Wed, Jul 23, 2014 at 9:00 PM, Ben Gras <beng at shrike-systems.com>
> >>> >> wrote:
> >>> >> > All,
> >>> >> >
> >>> >> > Full details on how to reproduce all the work from source
> >>> >> > repositories
> >>> >> > to
> >>> >> > scripts & utilities to write a complete sd card booting RTEMS and
> >>> >> > test
> >>> >> > the
> >>> >> > whole thing:
> >>> >> >
> >>> >> >
> >>> >> >
> >>> >> >
> http://www.shrike-systems.com/beagleboard-xm-beaglebone-black-and-everything-else-rtems-on-the-beagles.html
> >>> >> >
> >>> >> > I am submitting the attached patch for review for merging. If
> >>> >> > accepted
> >>> >> > for
> >>> >> > merging, please use the top two commits on
> >>> >> >
> >>> >> > https://github.com/bengras/rtems/tree/beaglebone-wip
> >>> >> >
> >>> >> > which have the same net effect but preserve Claas' work because of
> >>> >> > the
> >>> >> > earlier commit. The squashed version attached is for more
> convenient
> >>> >> > review.
> >>> >> >
> >>> >> > I was ironing out more wrinkles but given recent interest it seems
> >>> >> > smarter
> >>> >> > to merge sooner and keep polishing from mainline. Nevertheless I
> >>> >> > have
> >>> >> > put a
> >>> >> > lot of work into getting it into good shape already.
> >>> >> >
> >>> >> > I have rebased everything on the very latest master and verified
> >>> >> >
> >>> >> > That building all the tools and utilities from scratch work, using
> >>> >> > the
> >>> >> > RTEMS
> >>> >> > Source Builder repository (Ubuntu + FreeBSD).
> >>> >> > That building the beaglebone and bbxm BSPs and linking them with
> all
> >>> >> > the
> >>> >> > testsuite programs works (Ubuntu + FreeBSD).
> >>> >> > That the beaglexm-emulating linaro qemu executes all of those
> tests
> >>> >> > properly, invoked using a single command line with the scripts in
> >>> >> > the
> >>> >> > RTEMS
> >>> >> > tools repository, even though not all pass currently (Ubuntu +
> >>> >> > FreeBSD).
> >>> >> > That loading & running over JTAG works, both interactively with
> gdb
> >>> >> > and
> >>> >> > in a
> >>> >> > batch using gdb and the test runner.
> >>> >> > That running RTEMS executables using u-boot on the beaglebones
> from
> >>> >> > sd
> >>> >> > card
> >>> >> > work; both with and without MMU enabled at RTEMS start time.
> >>> >> > That Claas' earlier commit builds.
> >>> >> >
> >>> >> > Thanks so far to Chris and Brandon for help, support, instructions
> >>> >> > and
> >>> >> > advice in various forms :)
> >>> >> >
> >>> >> > Test results on qemu:
> >>> >> > Passed:   497 Failed:     3 Timeouts:   1 Invalid:    0
> >>> >> >
> >>> >> > The test results on bbxm over jtag (older):
> >>> >> > Passed:   475 Failed:     7 Timeouts:  10 Invalid:    0
> >>> >> >
> >>> >> > I want to iron out more wrinkles and build support (ethernet) but
> >>> >> > giving
> >>> >> > the
> >>> >> > bsp more exposure and having it in mainline so i don't have to
> keep
> >>> >> > rebasing
> >>> >> > & testing would be nice at this point.
> >>> >> >
> >>> >> >
> >>> >> >
> >>> >> >
> >>> >> > _______________________________________________
> >>> >> > devel mailing list
> >>> >> > devel at rtems.org
> >>> >> > http://lists.rtems.org/mailman/listinfo/devel
> >>> >
> >>> >
> >>
> >>
> >
>
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diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4
index a15de34..327650e 100644
--- a/c/src/lib/libbsp/arm/acinclude.m4
+++ b/c/src/lib/libbsp/arm/acinclude.m4
@@ -4,6 +4,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
   case "$1" in
   altera-cyclone-v )
     AC_CONFIG_SUBDIRS([altera-cyclone-v]);;
+  beagle )
+    AC_CONFIG_SUBDIRS([beagle]);;
   csb336 )
     AC_CONFIG_SUBDIRS([csb336]);;
   csb337 )
@@ -42,8 +44,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
     AC_CONFIG_SUBDIRS([tms570]);;
   xilinx-zynq )
     AC_CONFIG_SUBDIRS([xilinx-zynq]);;
-  beagle )
-    AC_CONFIG_SUBDIRS([beagle]);;
   *)
     AC_MSG_ERROR([Invalid BSP]);;
   esac
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am
index 8050b88..988c2b3 100644
--- a/c/src/lib/libbsp/arm/beagle/Makefile.am
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am
@@ -32,7 +32,6 @@ include_bsp_HEADERS += ../../shared/include/irq-generic.h
 include_bsp_HEADERS += ../../shared/include/irq-info.h
 include_bsp_HEADERS += ../../shared/include/stackalloc.h
 include_bsp_HEADERS += ../../shared/include/uart-output-char.h
-include_bsp_HEADERS += ../../shared/tod.h
 include_bsp_HEADERS += ../shared/include/arm-a8core-start.h
 include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
 include_bsp_HEADERS += ../shared/include/arm-errata.h
@@ -41,7 +40,11 @@ include_bsp_HEADERS += ../shared/include/start.h
 include_bsp_HEADERS += include/irq.h
 include_bsp_HEADERS += include/i2c.h
 
-include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
+include_libcpu_HEADERS = 
+include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/arm-cp15.h
+include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/omap3.h
+include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/am335x.h
+include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/omap_timer.h
 
 ###############################################################################
 #                  Data                                                       #
diff --git a/c/src/lib/libbsp/arm/beagle/README b/c/src/lib/libbsp/arm/beagle/README
index abdb176..9f02c11 100644
--- a/c/src/lib/libbsp/arm/beagle/README
+++ b/c/src/lib/libbsp/arm/beagle/README
@@ -4,10 +4,6 @@ original beagleboard isn't tested.
 
 wiki: http://www.rtems.org/wiki/index.php/Beagleboard
 
-My blog post detailing all the building and using; there is more detail there
-than in this README:
-http://www.shrike-systems.com/beagleboard-xm-beaglebone-black-and-everything-else-rtems-on-the-beagles.html
-
 1.   *** CONFIGURING ************
 
 bsp-specific build options in the environment at build time:
@@ -28,11 +24,12 @@ usage.
 
 2.   *** BUILDING    ************
 
-To build BSPs for the beaglebone white and beagleboard xm:
+To build BSPs for the beaglebone white and beagleboard xm, starting from
+a directory in which you have this source tree in rtems-src:
 
 $ mkdir b-beagle
 $ cd b-beagle
-$ ../claas-rtems/configure --target=arm-rtems4.11 --enable-rtemsbsp="beaglebonewhite beagleboardxm"
+$ ../rtems-src/configure --target=arm-rtems4.11 --enable-rtemsbsp="beaglebonewhite beagleboardxm"
 $ make all
 
 This should give you .exes somewhere.
@@ -91,13 +88,14 @@ uboot# tftp 0x80800000 rtems-app.img
 uboot# dcache off ; icache off
 uboot# bootm 0x80800000
 
-
 4.   *** SD CARD ****************
 
 There is a script here that automatically writes an SD card for any of
 the beagle targets.
 
-Let's write one for the Beaglebone Black:
+Let's write one for the Beaglebone Black. Assuming your source tree is
+at $HOME/development/rtems/rtems-src and your bsp is built and linked
+with examples and installed at $HOME/development/rtems/4.11.
 
     % cd $HOME/development/rtems/rtems-src/c/src/lib/libbsp/arm/beagle/simscripts
     % sh sdcard.sh $HOME/development/rtems/4.11 $HOME/development/rtems/b-beagle/arm-rtems4.11/c/beagleboneblack/testsuites/samples/hello/hello.exe
@@ -108,9 +106,10 @@ The script should give you a whole bunch of output, ending in:
 
 There you go. dd that to an SD card and boot!
 
-The script needs to know whether it's for a Beagleboard xM or one of
-the Beaglebones. This is to know which uboot to use. It will detect this
-from the path the executable is in, so you have to specify the full path.
+The script needs to know whether it's for a Beagleboard xM or one of the
+Beaglebones. This is to know which uboot to use. It will detect this
+from the path the executable is in (in the above example, it contains
+'beagleboneblack'), so you have to specify the full path.
 
 
 Good luck & enjoy!
diff --git a/c/src/lib/libbsp/arm/beagle/TODO b/c/src/lib/libbsp/arm/beagle/TODO
deleted file mode 100644
index 087b761..0000000
--- a/c/src/lib/libbsp/arm/beagle/TODO
+++ /dev/null
@@ -1,21 +0,0 @@
- . run testsuite
- . test reset xm and clock xm
- . waf compatability
-
-verified:
- . printk, printf, interrupt uart, timer (+nsec), clocks
- . different Hz
- . warnings
- . timer wraparound is ok
- . reset bbone
- . i turn caches and mmu on
- . works when booted with and without mmu on (cache off/on in uboot)
- . needed vbar; used standard arm_cp15_set_vector_base_address
- . minimize irq.h
- . coding conventions, spacing
- . doxygen
-
-open:
- . how to handle the interrupt?
- . uboot env
- . minimize Makefile.am
diff --git a/c/src/lib/libbsp/arm/beagle/clock.c b/c/src/lib/libbsp/arm/beagle/clock.c
index d58cb97..92f9a62 100644
--- a/c/src/lib/libbsp/arm/beagle/clock.c
+++ b/c/src/lib/libbsp/arm/beagle/clock.c
@@ -17,43 +17,11 @@
 #include <rtems.h>
 #include <bsp.h>
 
-#ifdef ARM_MULTILIB_ARCH_V4
-
-struct omap_timer_registers;
-
-struct omap_timer
-{
-  uint32_t base;
-  int irq_nr;
-  struct omap_timer_registers *regs;
-};
-
-struct omap_timer_registers
-{
-  uint32_t TIDR;
-  uint32_t TIOCP_CFG;
-  uint32_t TISTAT;
-  uint32_t TISR;
-  uint32_t TIER;
-  uint32_t TWER;
-  uint32_t TCLR;
-  uint32_t TCRR;
-  uint32_t TLDR;
-  uint32_t TTGR;
-  uint32_t TWPS;
-  uint32_t TMAR;
-  uint32_t TCAR1;
-  uint32_t TSICR;
-  uint32_t TCAR2;
-  uint32_t TPIR;
-  uint32_t TNIR;
-  uint32_t TCVR;
-  uint32_t TOCR;
-  uint32_t TOWR;
+#include <libcpu/omap_timer.h>
 
-};
+#ifdef ARM_MULTILIB_ARCH_V4
 
-static struct omap_timer_registers regs_v1 = {
+static omap_timer_registers_t regs_v1 = {
   .TIDR = OMAP3_TIMER_TIDR,
   .TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG,
   .TISTAT = OMAP3_TIMER_TISTAT,
@@ -77,7 +45,7 @@ static struct omap_timer_registers regs_v1 = {
 };
 
 /* AM335X has a different ip block for the non 1ms timers */
-static struct omap_timer_registers regs_v2 = {
+static omap_timer_registers_t regs_v2 = {
   .TIDR = AM335X_TIMER_TIDR,
   .TIOCP_CFG = AM335X_TIMER_TIOCP_CFG,
   .TISTAT = AM335X_TIMER_IRQSTATUS_RAW,
@@ -99,19 +67,21 @@ static struct omap_timer_registers regs_v2 = {
   .TOCR = -1,		/* UNDEF */
   .TOWR = -1		/* UNDEF */
 };
+
 /* which timers are in use? target-dependent.
  * initialize at compile time.
  */
+
 #if IS_DM3730
 
-static struct omap_timer dm37xx_timer = {
+static omap_timer_t dm37xx_timer = {
   .base = OMAP3_GPTIMER1_BASE,
   .irq_nr = OMAP3_GPT1_IRQ,
   .regs = &regs_v1
 };
 
 /* free running timer */
-static struct omap_timer dm37xx_fr_timer = {
+static omap_timer_t dm37xx_fr_timer = {
   .base = OMAP3_GPTIMER10_BASE,
   .irq_nr = OMAP3_GPT10_IRQ,
   .regs = &regs_v1
@@ -119,28 +89,28 @@ static struct omap_timer dm37xx_fr_timer = {
 
 static struct omap_timer *fr_timer = &dm37xx_fr_timer;
 static struct omap_timer *timer = &dm37xx_timer;
-#endif
+
+#endif 
 
 #if IS_AM335X
 
 /* normal timer */
-static struct omap_timer am335x_timer = {
+static omap_timer_t am335x_timer = {
   .base = AM335X_DMTIMER1_1MS_BASE,
   .irq_nr = AM335X_INT_TINT1_1MS,
   .regs = &regs_v1
 };
 
 /* free running timer */
-static struct omap_timer am335x_fr_timer = {
+static omap_timer_t am335x_fr_timer = {
   .base = AM335X_DMTIMER7_BASE,
   .irq_nr = AM335X_INT_TINT7,
   .regs = &regs_v2
 };
 
-
-
 static struct omap_timer *fr_timer = &am335x_fr_timer;
 static struct omap_timer *timer = &am335x_timer;
+
 #endif
 
 static int done = 0;
diff --git a/c/src/lib/libbsp/arm/beagle/include/bsp.h b/c/src/lib/libbsp/arm/beagle/include/bsp.h
index fc001dd1..cc3d687 100644
--- a/c/src/lib/libbsp/arm/beagle/include/bsp.h
+++ b/c/src/lib/libbsp/arm/beagle/include/bsp.h
@@ -35,6 +35,9 @@
 #include <rtems.h>
 #include <rtems/irq-extension.h>
 
+#include <libcpu/omap3.h>
+#include <libcpu/am335x.h>
+
 #define BSP_FEATURE_IRQ_EXTENSION
 
 /* UART base clock frequency */
@@ -56,443 +59,61 @@
 static inline void
 write32(uint32_t address, uint32_t value)
 {
-  REG(address) = value;
+    REG(address) = value;
 }
 
 /* Read an uint32_t from a memory address */
 static inline uint32_t
 read32(uint32_t address)
 {
-  return REG(address);
+    return REG(address);
 }
 
 /* Set a 32 bits value depending on a mask */
 static inline void
 set32(uint32_t address, uint32_t mask, uint32_t value)
 {
-  uint32_t val;
-  val = read32(address);
-  /* clear the bits */
-  val &= ~(mask);
-  /* apply the value using the mask */
-  val |= (value & mask);
-  write32(address, val);
+    uint32_t val;
+    val = read32(address);
+    /* clear the bits */
+    val &= ~(mask);
+    /* apply the value using the mask */
+    val |= (value & mask);
+    write32(address, val);
 }
 
 /* Write a uint16_t value to a memory address. */
 static inline void
 write16(uint32_t address, uint16_t value)
 {
-  REG16(address) = value;
+    REG16(address) = value;
 }
 
 /* Read an uint16_t from a memory address */
 static inline uint16_t
 read16(uint32_t address)
 {
-  return REG16(address);
+    return REG16(address);
 }
 
 /* Data synchronization barrier */
 static inline void dsb(void)
 {
-        asm volatile("dsb" : : : "memory");
+    asm volatile("dsb" : : : "memory");
 }
 
 /* Instruction synchronization barrier */
 static inline void isb(void)
 {
-        asm volatile("isb" : : : "memory");
+    asm volatile("isb" : : : "memory");
 }
 
 /* flush data cache */
 static inline void flush_data_cache(void)
 {
-        asm volatile("mov r0, #0; mcr p15, #0, r0, c7, c10, #4" : : : "memory");
+    asm volatile("mov r0, #0; mcr p15, #0, r0, c7, c10, #4" : : : "memory");
 }
 
-/* Interrupt controller memory map */
-#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-
-/* Interrupt controller memory map */
-#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
-
-/* Interrupt controller registers */
-#define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
-#define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
-#define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
-#define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
-#define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
-#define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
-#define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
-#define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
-#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
-#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
-#define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
-#define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
-#define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
-#define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
-#define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
-#define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
-#define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
-#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
-#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
-#define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
-
-/* SYSCONFIG */
-#define OMAP3_SYSCONFIG_AUTOIDLE	0x01	/* SYSCONFIG.AUTOIDLE bit */
-
-#define OMAP3_INTR_ITR(base,n) \
-    (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR(base,n) \
-    (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR_CLEAR(base,n)	\
-    (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
-#define OMAP3_INTR_MIR_SET(base,n) \
-    (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
-#define OMAP3_INTR_ISR_SET(base,n) \
-    (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
-#define OMAP3_INTR_ISR_CLEAR(base,n) \
-    (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
-#define OMAP3_INTR_PENDING_IRQ(base,n) \
-    (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
-#define OMAP3_INTR_PENDING_FIQ(base,n) \
-    (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
-#define OMAP3_INTR_ILR(base,m) \
-    (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
-
-#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7f /* Active IRQ mask for SIR_IRQ */
-#define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
-
-
-
-
-#define OMAP3_DM337X_NR_IRQ_VECTORS    96
-
-/* Interrupt mappings */
-#define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
-#define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
-#define OMAP3_SYS_NIRQ       7  /* External source (active low) */
-#define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
-#define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
-#define OMAP3_PRCM_IRQ      11  /* PRCM module */
-#define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
-#define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
-#define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
-#define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
-#define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
-#define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
-#define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
-#define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
-#define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
-#define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
-#define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
-#define OMAP3_DSS_IRQ       25  /* Display subsystem module */
-#define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
-#define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
-#define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
-#define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
-#define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
-#define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
-#define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
-#define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
-#define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
-#define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
-#define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
-#define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
-#define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
-#define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
-#define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
-#define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
-#define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
-#define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
-#define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
-#define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
-#define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
-#define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
-#define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
-#define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
-#define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
-#define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
-#define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
-#define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
-#define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
-#define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
-#define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
-#define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
-#define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
-#define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
-#define OMAP3_UART1_IRQ     72  /* UART module 1 */
-#define OMAP3_UART2_IRQ     73  /* UART module 2 */
-#define OMAP3_UART3_IRQ     74  /* UART module 3 */
-#define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
-#define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
-#define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
-#define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
-#define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
-#define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
-#define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
-#define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
-#define OMAP3_ICR_IRQ       87  /* MPU ICR */
-#define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
-#define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
-#define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
-#define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
-#define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
-#define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
-#define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
-
-
-#define AM335X_INT_EMUINT                         0	/* Emulation interrupt (EMUICINTR) */
-#define AM335X_INT_COMMTX                         1	/* CortexA8 COMMTX */
-#define AM335X_INT_COMMRX                         2	/* CortexA8 COMMRX */
-#define AM335X_INT_BENCH                          3	/* CortexA8 NPMUIRQ */
-#define AM335X_INT_ELM_IRQ                        4	/* Sinterrupt (Error location process completion) */
-#define AM335X_INT_NMI                            7	/* nmi_int */
-#define AM335X_INT_L3DEBUG                        9	/* l3_FlagMux_top_FlagOut1 */
-#define AM335X_INT_L3APPINT                       10	/* l3_FlagMux_top_FlagOut0  */
-#define AM335X_INT_PRCMINT                        11	/* irq_mpu */
-#define AM335X_INT_EDMACOMPINT                    12	/* tpcc_int_pend_po0 */
-#define AM335X_INT_EDMAMPERR                      13	/* tpcc_mpint_pend_po */
-#define AM335X_INT_EDMAERRINT                     14	/* tpcc_errint_pend_po */
-#define AM335X_INT_ADC_TSC_GENINT                 16	/* gen_intr_pend */
-#define AM335X_INT_USBSSINT                       17	/* usbss_intr_pend */
-#define AM335X_INT_USB0                           18	/* usb0_intr_pend */
-#define AM335X_INT_USB1                           19	/* usb1_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT0                 20	/* pr1_host_intr0_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT1                 21	/* pr1_host_intr1_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT2                 22	/* pr1_host_intr2_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT3                 23	/* pr1_host_intr3_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT4                 24	/* pr1_host_intr4_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT5                 25	/* pr1_host_intr5_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT6                 26	/* pr1_host_intr6_intr_pend */
-#define AM335X_INT_PRUSS1_EVTOUT7                 27	/* pr1_host_intr7_intr_pend */
-#define AM335X_INT_MMCSD1INT                      28	/* MMCSD1  SINTERRUPTN */
-#define AM335X_INT_MMCSD2INT                      29	/* MMCSD2  SINTERRUPT */
-#define AM335X_INT_I2C2INT                        30	/* I2C2  POINTRPEND */
-#define AM335X_INT_eCAP0INT                       31	/* ecap_intr_intr_pend */
-#define AM335X_INT_GPIOINT2A                      32	/* GPIO 2  POINTRPEND1 */
-#define AM335X_INT_GPIOINT2B                      33	/* GPIO 2  POINTRPEND2 */
-#define AM335X_INT_USBWAKEUP                      34	/* USBSS  slv0p_Swakeup */
-#define AM335X_INT_LCDCINT                        36	/* LCDC  lcd_irq */
-#define AM335X_INT_GFXINT                         37	/* SGX530  THALIAIRQ */
-#define AM335X_INT_ePWM2INT                       39	/* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_3PGSWRXTHR0                    40	/* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
-#define AM335X_INT_3PGSWRXINT0                    41	/* CPSW (Ethernet)  c0_rx_pend */
-#define AM335X_INT_3PGSWTXINT0                    42	/* CPSW (Ethernet)  c0_tx_pend */
-#define AM335X_INT_3PGSWMISC0                     43	/* CPSW (Ethernet)  c0_misc_pend */
-#define AM335X_INT_UART3INT                       44	/* UART3  niq */
-#define AM335X_INT_UART4INT                       45	/* UART4  niq */
-#define AM335X_INT_UART5INT                       46	/* UART5  niq */
-#define AM335X_INT_eCAP1INT                       47	/* (PWM Subsystem)  ecap_intr_intr_pend */
-#define AM335X_INT_DCAN0_INT0                     52	/* DCAN0  dcan_intr0_intr_pend */
-#define AM335X_INT_DCAN0_INT1                     53	/* DCAN0  dcan_intr1_intr_pend */
-#define AM335X_INT_DCAN0_PARITY                   54	/* DCAN0  dcan_uerr_intr_pend */
-#define AM335X_INT_DCAN1_INT0                     55	/* DCAN1  dcan_intr0_intr_pend */
-#define AM335X_INT_DCAN1_INT1                     56	/* DCAN1  dcan_intr1_intr_pend */
-#define AM335X_INT_DCAN1_PARITY                   57	/* DCAN1  dcan_uerr_intr_pend */
-#define AM335X_INT_ePWM0_TZINT                    58	/* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_ePWM1_TZINT                    59	/* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_ePWM2_TZINT                    60	/* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
-#define AM335X_INT_eCAP2INT                       61	/* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
-#define AM335X_INT_GPIOINT3A                      62	/* GPIO 3  POINTRPEND1 */
-#define AM335X_INT_GPIOINT3B                      63	/* GPIO 3  POINTRPEND2 */
-#define AM335X_INT_MMCSD0INT                      64	/* MMCSD0  SINTERRUPTN */
-#define AM335X_INT_SPI0INT                        65	/* McSPI0  SINTERRUPTN */
-#define AM335X_INT_TINT0                          66	/* Timer0  POINTR_PEND */
-#define AM335X_INT_TINT1_1MS                      67	/* DMTIMER_1ms  POINTR_PEND */
-#define AM335X_INT_TINT2                          68	/* DMTIMER2  POINTR_PEND */
-#define AM335X_INT_TINT3                          69	/* DMTIMER3  POINTR_PEND */
-#define AM335X_INT_I2C0INT                        70	/* I2C0  POINTRPEND */
-#define AM335X_INT_I2C1INT                        71	/* I2C1  POINTRPEND */
-#define AM335X_INT_UART0INT                       72	/* UART0  niq */
-#define AM335X_INT_UART1INT                       73	/* UART1  niq */
-#define AM335X_INT_UART2INT                       74	/* UART2  niq */
-#define AM335X_INT_RTCINT                         75	/* RTC  timer_intr_pend */
-#define AM335X_INT_RTCALARMINT                    76	/* RTC  alarm_intr_pend */
-#define AM335X_INT_MBINT0                         77	/* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
-#define AM335X_INT_M3_TXEV                        78	/* Wake M3 Subsystem  TXEV */
-#define AM335X_INT_eQEP0INT                       79	/* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_MCATXINT0                      80	/* McASP0  mcasp_x_intr_pend */
-#define AM335X_INT_MCARXINT0                      81	/* McASP0  mcasp_r_intr_pend */
-#define AM335X_INT_MCATXINT1                      82	/* McASP1  mcasp_x_intr_pend */
-#define AM335X_INT_MCARXINT1                      83	/* McASP1  mcasp_r_intr_pend */
-#define AM335X_INT_ePWM0INT                       86	/* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_ePWM1INT                       87	/* (PWM Subsystem)  epwm_intr_intr_pend */
-#define AM335X_INT_eQEP1INT                       88	/* (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_eQEP2INT                       89	/* (PWM Subsystem)  eqep_intr_intr_pend */
-#define AM335X_INT_DMA_INTR_PIN2                  90	/* External DMA/Interrupt Pin2  pi_x_dma_event_intr2 (xdma_event_intr2) */
-#define AM335X_INT_WDT1INT                        91	/* (Public Watchdog)  WDTIMER1  PO_INT_PEND */
-#define AM335X_INT_TINT4                          92	/* DMTIMER4  POINTR_PEN */
-#define AM335X_INT_TINT5                          93	/* DMTIMER5  POINTR_PEN */
-#define AM335X_INT_TINT6                          94	/* DMTIMER6  POINTR_PEND */
-#define AM335X_INT_TINT7                          95	/* DMTIMER7  POINTR_PEND */
-#define AM335X_INT_GPIOINT0A                      96	/* GPIO 0  POINTRPEND1 */
-#define AM335X_INT_GPIOINT0B                      97	/* GPIO 0  POINTRPEND2 */
-#define AM335X_INT_GPIOINT1A                      98	/* GPIO 1  POINTRPEND1 */
-#define AM335X_INT_GPIOINT1B                      99	/* GPIO 1  POINTRPEND2 */
-#define AM335X_INT_GPMCINT                        100	/* GPMC  gpmc_sinterrupt */
-#define AM335X_INT_DDRERR0                        101	/* EMIF  sys_err_intr_pend */
-#define AM335X_INT_TCERRINT0                      112	/* TPTC0  tptc_erint_pend_po */
-#define AM335X_INT_TCERRINT1                      113	/* TPTC1  tptc_erint_pend_po */
-#define AM335X_INT_TCERRINT2                      114	/* TPTC2  tptc_erint_pend_po */
-#define AM335X_INT_ADC_TSC_PENINT                 115	/* ADC_TSC  pen_intr_pend */
-#define AM335X_INT_SMRFLX_Sabertooth              120	/* Smart Reflex 0  intrpen */
-#define AM335X_INT_SMRFLX_Core                    121	/* Smart Reflex 1  intrpend */
-#define AM335X_INT_DMA_INTR_PIN0                  123	/* pi_x_dma_event_intr0 (xdma_event_intr0) */
-#define AM335X_INT_DMA_INTR_PIN1                  124	/* pi_x_dma_event_intr1 (xdma_event_intr1) */
-#define AM335X_INT_SPI1INT                        125	/* McSPI1  SINTERRUPTN */
-
-#define OMAP3_AM335X_NR_IRQ_VECTORS    125
-
-/* General-purpose timer register map */
-#define OMAP3_GPTIMER1_BASE  0x48318000 /* GPTIMER1 physical address */
-#define OMAP3_GPTIMER2_BASE  0x49032000 /* GPTIMER2 physical address */
-#define OMAP3_GPTIMER3_BASE  0x49034000 /* GPTIMER3 physical address */
-#define OMAP3_GPTIMER4_BASE  0x49036000 /* GPTIMER4 physical address */
-#define OMAP3_GPTIMER5_BASE  0x49038000 /* GPTIMER5 physical address */
-#define OMAP3_GPTIMER6_BASE  0x4903A000 /* GPTIMER6 physical address */
-#define OMAP3_GPTIMER7_BASE  0x4903C000 /* GPTIMER7 physical address */
-#define OMAP3_GPTIMER8_BASE  0x4903E000 /* GPTIMER8 physical address */
-#define OMAP3_GPTIMER9_BASE  0x49040000 /* GPTIMER9 physical address */
-#define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */
-#define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */
-
-
-/* General-purpose timer registers */
-#define OMAP3_TIMER_TIDR      0x000 /* IP revision code */
-#define OMAP3_TIMER_TIOCP_CFG 0x010 /* Controls params for GP timer L4 interface */
-#define OMAP3_TIMER_TISTAT    0x014 /* Status (excl. interrupt status) */
-#define OMAP3_TIMER_TISR      0x018 /* Pending interrupt status */
-#define OMAP3_TIMER_TIER      0x01C /* Interrupt enable */
-#define OMAP3_TIMER_TWER      0x020 /* Wakeup enable */
-#define OMAP3_TIMER_TCLR      0x024 /* Controls optional features */
-#define OMAP3_TIMER_TCRR      0x028 /* Internal counter value */
-#define OMAP3_TIMER_TLDR      0x02C /* Timer load value */
-#define OMAP3_TIMER_TTGR      0x030 /* Triggers counter reload */
-#define OMAP3_TIMER_TWPS      0x034 /* Indicates if Write-Posted pending */
-#define OMAP3_TIMER_TMAR      0x038 /* Value to be compared with counter */
-#define OMAP3_TIMER_TCAR1     0x03C /* First captured value of counter register */
-#define OMAP3_TIMER_TSICR     0x040 /* Control posted mode and functional SW reset */
-#define OMAP3_TIMER_TCAR2     0x044 /* Second captured value of counter register */
-#define OMAP3_TIMER_TPIR      0x048 /* Positive increment (1 ms tick) */
-#define OMAP3_TIMER_TNIR      0x04C /* Negative increment (1 ms tick) */
-#define OMAP3_TIMER_TCVR      0x050 /* Defines TCRR is sub/over-period (1 ms tick) */
-#define OMAP3_TIMER_TOCR      0x054 /* Masks tick interrupt */
-#define OMAP3_TIMER_TOWR      0x058 /* Number of masked overflow interrupts */
-
-#define AM335X_DMTIMER0_BASE      0x44E05000  /* DMTimer0 Registers */
-#define AM335X_DMTIMER1_1MS_BASE  0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */
-#define AM335X_DMTIMER2_BASE      0x48040000 /*  DMTimer2 Registers */
-#define AM335X_DMTIMER3_BASE      0x48042000 /*  DMTimer3 Registers */
-#define AM335X_DMTIMER4_BASE      0x48044000 /* DMTimer4 Registers  */
-#define AM335X_DMTIMER5_BASE      0x48046000 /* DMTimer5 Registers  */
-#define AM335X_DMTIMER6_BASE      0x48048000 /*  DMTimer6 Registers */
-#define AM335X_DMTIMER7_BASE      0x4804A000 /*  DMTimer7 Registers */
-
-/* General-purpose timer registers  AM335x non 1MS timers have different offsets */
-#define AM335X_TIMER_TIDR             0x000 /* IP revision code */
-#define AM335X_TIMER_TIOCP_CFG        0x010 /* Controls params for GP timer L4 interface */
-#define AM335X_TIMER_IRQSTATUS_RAW    0x024 /* Timer IRQSTATUS Raw Register */
-#define AM335X_TIMER_IRQSTATUS        0x028 /* Timer IRQSTATUS Register */
-#define AM335X_TIMER_IRQENABLE_SET    0x02C /* Timer IRQENABLE Set Register */
-#define AM335X_TIMER_IRQENABLE_CLR    0x030 /* Timer IRQENABLE Clear Register */
-#define AM335X_TIMER_IRQWAKEEN        0x034 /* Timer IRQ Wakeup Enable Register */
-#define AM335X_TIMER_TCLR      0x038 /* Controls optional features */
-#define AM335X_TIMER_TCRR      0x03C /* Internal counter value */
-#define AM335X_TIMER_TLDR      0x040 /* Timer load value */
-#define AM335X_TIMER_TTGR      0x044 /* Triggers counter reload */
-#define AM335X_TIMER_TWPS      0x048 /* Indicates if Write-Posted pending */
-#define AM335X_TIMER_TMAR      0x04C /* Value to be compared with counter */
-#define AM335X_TIMER_TCAR1     0x050 /* First captured value of counter register */
-#define AM335X_TIMER_TSICR     0x054 /* Control posted mode and functional SW reset */
-#define AM335X_TIMER_TCAR2     0x058 /* Second captured value of counter register */
-
-
-
-/* Interrupt status register fields */
-#define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
-#define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
-#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
-
-/* Interrupt enable register fields */
-#define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
-#define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
-#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
-
-/* Timer control fields */
-#define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
-#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
-#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
-#define OMAP3_TCLR_PTV      2
-#define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
-
-
-#define OMAP3_CM_CLKSEL_GFX		0x48004b40
-#define OMAP3_CM_CLKEN_PLL		0x48004d00
-#define OMAP3_CM_FCLKEN1_CORE	0x48004A00
-#define OMAP3_CM_CLKSEL_CORE	0x48004A40 /* GPT10 src clock sel. */
-#define OMAP3_CM_FCLKEN_PER		0x48005000
-#define OMAP3_CM_CLKSEL_PER		0x48005040
-#define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
-
-
-#define CM_MODULEMODE_MASK (0x3 << 0)
-#define CM_MODULEMODE_ENABLE      (0x2 << 0)
-#define CM_MODULEMODE_DISABLED     (0x0 << 0)
-
-#define CM_CLKCTRL_IDLEST         (0x3 << 16)
-#define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
-#define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
-#define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
-#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
-
-#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
-
-#define CM_WKUP_TIMER1_CLKCTRL	(CM_WKUP_BASE + 0xC4) /* This register manages the TIMER1 clocks. [Memory Mapped] */
-
-
-#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
-#define CM_PER_TIMER7_CLKCTRL	(CM_PER_BASE + 0x7C) /* This register manages the TIMER7 clocks. [Memory Mapped] */
-
-
-
-/* CM_DPLL registers */
-
-
-#define CM_DPLL_BASE 	0x44E00500 /* Clock Module PLL Registers */
-
-#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
-
-
-#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) /* Select CLK_M_OSC clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_32KHZ clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) /* Select TCLKIN clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) /* Select CLK_RC32K clock */
-#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) /* Selects the CLK_32768 from 32KHz Crystal Osc */
-
-#define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
-#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
-#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
-#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
-
-
-
-
-#define OMAP3_CLKSEL_GPT1    (1 << 0)
-#define OMAP3_CLKSEL_GPT10    (1 << 6)
-#define OMAP3_CLKSEL_GPT11    (1 << 7)
-
 
 #define TIMER_FREQ  1000    /* clock frequency for OMAP timer (1ms) */
 #define TIMER_COUNT(freq) (TIMER_FREQ/(freq)) /* initial value for counter*/
@@ -518,96 +139,91 @@ static inline void flush_data_cache(void)
 #define SYSTEM_CLOCK_192      19200000
 #define SYSTEM_CLOCK_96       96000000
 
-#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
-
 #if !defined(IS_DM3730) && !defined(IS_AM335X)
 #error Unrecognized BSP configured.
 #endif
 
 #if IS_DM3730
-#define BSP_DEVICEMEM_START	0x48000000
-#define BSP_DEVICEMEM_END	0x5F000000
+#define BSP_DEVICEMEM_START 0x48000000
+#define BSP_DEVICEMEM_END   0x5F000000
 #endif
 
 #if IS_AM335X
-#define BSP_DEVICEMEM_START	0x44000000
-#define BSP_DEVICEMEM_END	0x57000000
+#define BSP_DEVICEMEM_START 0x44000000
+#define BSP_DEVICEMEM_END   0x57000000
 #endif
 
 /* per-target uart config */
 #if IS_AM335X
-#define BSP_CONSOLE_UART	1
-#define BSP_CONSOLE_UART_BASE	BEAGLE_BASE_UART_1
-#define BSP_CONSOLE_UART_IRQ	OMAP3_UART1_IRQ
-#define BEAGLE_BASE_UART_1	0x44E09000
-#define BEAGLE_BASE_UART_2	0x48022000
-#define BEAGLE_BASE_UART_3	0x48024000
+#define BSP_CONSOLE_UART        1
+#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_1
+#define BSP_CONSOLE_UART_IRQ    OMAP3_UART1_IRQ
+#define BEAGLE_BASE_UART_1      0x44E09000
+#define BEAGLE_BASE_UART_2      0x48022000
+#define BEAGLE_BASE_UART_3      0x48024000
 #endif
 
 /* per-target uart config */
 #if IS_DM3730
-#define BSP_CONSOLE_UART	3
-#define BSP_CONSOLE_UART_BASE	BEAGLE_BASE_UART_3
-#define BSP_CONSOLE_UART_IRQ	OMAP3_UART3_IRQ
-#define BEAGLE_BASE_UART_1	0x4806A000
-#define BEAGLE_BASE_UART_2	0x4806C000
-#define BEAGLE_BASE_UART_3	0x49020000
+#define BSP_CONSOLE_UART        3
+#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_3
+#define BSP_CONSOLE_UART_IRQ    OMAP3_UART3_IRQ
+#define BEAGLE_BASE_UART_1      0x4806A000
+#define BEAGLE_BASE_UART_2      0x4806C000
+#define BEAGLE_BASE_UART_3      0x49020000
 #endif
 
 /* i2c stuff */
 typedef struct {
-  uint32_t rx_or_tx;
-  uint32_t stat;
-  uint32_t ctrl;
-  uint32_t clk_hi;
-  uint32_t clk_lo;
-  uint32_t adr;
-  uint32_t rxfl;
-  uint32_t txfl;
-  uint32_t rxb;
-  uint32_t txb;
-  uint32_t s_tx;
-  uint32_t s_txfl;
+    uint32_t rx_or_tx;
+    uint32_t stat;
+    uint32_t ctrl;
+    uint32_t clk_hi;
+    uint32_t clk_lo;
+    uint32_t adr;
+    uint32_t rxfl;
+    uint32_t txfl;
+    uint32_t rxb;
+    uint32_t txb;
+    uint32_t s_tx;
+    uint32_t s_txfl;
 } beagle_i2c;
 
 /* sctlr */
 /* Read System Control Register */
 static inline uint32_t read_sctlr()
 {
-  uint32_t ctl;
-
-  asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
-    : [ctl] "=r" (ctl));
+    uint32_t ctl;
 
-  return ctl;
+    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+        : [ctl] "=r" (ctl));
+    return ctl;
 }
 
 /* Write System Control Register */
 static inline void write_sctlr(uint32_t ctl)
 {
-  asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
-    : : [ctl] "r" (ctl));
-  isb();
+    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+        : : [ctl] "r" (ctl));
+    isb();
 }
 
 /* Read Auxiliary Control Register */
 static inline uint32_t read_actlr()
 {
-  uint32_t ctl;
+    uint32_t ctl;
 
-       	asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
-       		: [ctl] "=r" (ctl));
-
-       	return ctl;
+    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+            : [ctl] "=r" (ctl));
+    return ctl;
 }
 
 /* Write Auxiliary Control Register */
 static inline void write_actlr(uint32_t ctl)
 {
-  asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
-    : : [ctl] "r" (ctl));
-
-       	isb();
+    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+        : : [ctl] "r" (ctl));
+    isb();
 }
 
 /* Write Translation Table Base Control Register */
@@ -640,146 +256,75 @@ static inline void write_dacr(uint32_t dacr)
         isb();
 }
 
-#define ARM_TTBR_ADDR_MASK (0xffffc000)
-#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
-#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
-#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
-#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
-#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
-
 static inline void refresh_tlb(void)
 {
-        dsb();
+    dsb();
 
-        /* Invalidate entire unified TLB */
-        asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" : : [zero] "r" (0));
+    /* Invalidate entire unified TLB */
+    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" 
+        : : [zero] "r" (0));
 
-#if 0
-        /* Invalidate entire data TLB */
-        asm volatile("mcr p15, 0, %[zero], c8, c6, 0" : : [zero] "r" (0));
+    /* Invalidate all instruction caches to PoU.
+     * Also flushes branch target cache. */
+    asm volatile("mcr p15, 0, %[zero], c7, c5, 0" 
+        : : [zero] "r" (0));
 
-        /* Invalidate entire instruction TLB */
-        asm volatile("mcr p15, 0, %[zero], c8, c5, 0" : : [zero] "r" (0));
-#endif
-
-        /*
-         * Invalidate all instruction caches to PoU.
-         * Also flushes branch target cache.
-         */
-        asm volatile("mcr p15, 0, %[zero], c7, c5, 0" : : [zero] "r" (0));
-
-        /* Invalidate entire branch predictor array */
-        asm volatile("mcr p15, 0, %[zero], c7, c5, 6" : : [zero] "r" (0)); /* flush BTB */
+    /* Invalidate entire branch predictor array */
+    asm volatile("mcr p15, 0, %[zero], c7, c5, 6" 
+        : : [zero] "r" (0)); /* flush BTB */
 
-        dsb();
-        isb();
+    dsb();
+    isb();
 }
 
 /* Read Translation Table Base Register 0 */
 static inline uint32_t read_ttbr0()
 {
-        uint32_t bar;
+    uint32_t bar;
 
-        asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
-                        : [bar] "=r" (bar));
+    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+        : [bar] "=r" (bar));
 
-        return bar & ARM_TTBR_ADDR_MASK;
+    return bar & ARM_TTBR_ADDR_MASK;
 }
 
 
 /* Read Translation Table Base Register 0 */
 static inline uint32_t read_ttbr0_unmasked()
 {
-        uint32_t bar;
+    uint32_t bar;
 
-        asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
-                        : [bar] "=r" (bar));
+    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+        : [bar] "=r" (bar));
 
-        return bar;
+    return bar;
 }
 
 /* Write Translation Table Base Register 0 */
 static inline void write_ttbr0(uint32_t bar)
 {
-        dsb();
-        isb();
-        /* In our setup TTBR contains the base address *and* the flags
-           but other pieces of the kernel code expect ttbr to be the
-           base address of the l1 page table. We therefore add the
-           flags here and remove them in the read_ttbr0 */
-        uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
-        asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
-                        : : [bar] "r" (v));
-
-        refresh_tlb();
+    dsb();
+    isb();
+    /* In our setup TTBR contains the base address *and* the flags
+       but other pieces of the kernel code expect ttbr to be the
+       base address of the l1 page table. We therefore add the
+       flags here and remove them in the read_ttbr0 */
+    uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
+    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+        : : [bar] "r" (v));
+
+    refresh_tlb();
 }
 
-/* cpu control flags */
-/* CPU control register (CP15 register 1) */
-#define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
-#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
-#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
-#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
-#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
-#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
-#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
-#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
-#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
-#define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
-#define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
-#define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
-#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
-#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
-#define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
-#define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
-#define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
-#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
-#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
-#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
-#define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
-#define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
-#define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
-#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
-#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
-#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
-
-#define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
-
-/* VM bits */
-/* Big page (1MB section) specific flags. */
-#define ARM_VM_SECTION                  (1 << 1)  /* 1MB section */
-#define ARM_VM_SECTION_PRESENT          (1 << 1)  /* Section is present */
-#define ARM_VM_SECTION_B                (1 << 2)  /* B Bit */
-#define ARM_VM_SECTION_C                (1 << 3)  /* C Bit */
-#define ARM_VM_SECTION_DOMAIN           (0xF << 5) /* Domain Number */
-#define ARM_VM_SECTION_SUPER            (0x1 << 10) /* Super access only AP[1:0] */
-#define ARM_VM_SECTION_USER             (0x3 << 10) /* Super/User access AP[1:0] */
-#define ARM_VM_SECTION_TEX0             (1 << 12) /* TEX[0] */
-#define ARM_VM_SECTION_TEX1             (1 << 13) /* TEX[1] */
-#define ARM_VM_SECTION_TEX2             (1 << 14) /* TEX[2] */
-#define ARM_VM_SECTION_RO               (1 << 15)   /* Read only access AP[2] */
-#define ARM_VM_SECTION_SHAREABLE        (1 << 16)  /* Shareable */
-#define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)  /* Not Global */
-
-/* inner and outer write-back, write-allocate */
-#define ARM_VM_SECTION_WB       (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
-/* inner and outer write-through, no write-allocate */
-#define ARM_VM_SECTION_WT       (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
-/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
-#define ARM_VM_SECTION_WTWB     (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
-/* shareable device */
-
-#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB
-
-#define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)
-
 /* Behaviour on fatal error; default: test-friendly.
  * set breakpoint to bsp_fatal_extension.
  */
-/* don't do this to allow tests to fail noninteractively */
-/* #define BSP_PRESS_KEY_FOR_RESET	1 */ 
-#define BSP_PRINT_EXCEPTION_CONTEXT 1	/* human-readable exception info */
-#define BSP_RESET_BOARD_AT_EXIT 1	/* causes qemu to exit, signaling end of test */
+/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
+/*#define  BSP_PRESS_KEY_FOR_RESET     1 */ 
+#define    BSP_PRINT_EXCEPTION_CONTEXT 1
+    /* human-readable exception info */
+#define    BSP_RESET_BOARD_AT_EXIT 1
+    /* causes qemu to exit, signaling end of test */
 
 
 /**
diff --git a/c/src/lib/libbsp/arm/beagle/irq.c b/c/src/lib/libbsp/arm/beagle/irq.c
index 6055eb8..8aa00df 100644
--- a/c/src/lib/libbsp/arm/beagle/irq.c
+++ b/c/src/lib/libbsp/arm/beagle/irq.c
@@ -83,7 +83,6 @@ static uint32_t get_mir_reg(int vector, uint32_t *mask)
 
   if(vector <   0) while(1) ;
   if(vector <  32) return OMAP3_INTCPS_MIR0;
-  if(vector <  32) return OMAP3_INTCPS_MIR0;
   if(vector <  64) return OMAP3_INTCPS_MIR1;
   if(vector <  96) return OMAP3_INTCPS_MIR2;
   if(vector < 128) return OMAP3_INTCPS_MIR3;
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg
deleted file mode 100644
index 06c13ee..0000000
--- a/c/src/lib/libbsp/arm/beagle/make/custom/beagle.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-#  Config file for BeagleBoard
-#
-
-include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
index 447a51e..ec0d2d2 100644
--- a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboardxm.cfg
@@ -1,2 +1,2 @@
-#  Config file for Original BeagleBoard
+#  Config file for BeagleBoard XM
 include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
index 447a51e..f947dce 100644
--- a/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beagleboneblack.cfg
@@ -1,2 +1,2 @@
-#  Config file for Original BeagleBoard
+#  Config file for BeagleBone Black
 include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg b/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
index 447a51e..4b035c0 100644
--- a/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
+++ b/c/src/lib/libbsp/arm/beagle/make/custom/beaglebonewhite.cfg
@@ -1,2 +1,2 @@
-#  Config file for Original BeagleBoard
+#  Config file for Original BeagleBone (aka BeagleBone White)
 include $(RTEMS_ROOT)/make/custom/beagle.inc
diff --git a/c/src/lib/libbsp/arm/beagle/preinstall.am b/c/src/lib/libbsp/arm/beagle/preinstall.am
index 50957d8..dd1ec95 100644
--- a/c/src/lib/libbsp/arm/beagle/preinstall.am
+++ b/c/src/lib/libbsp/arm/beagle/preinstall.am
@@ -8,15 +8,15 @@ endif
 PREINSTALL_DIRS =
 DISTCLEANFILES += $(PREINSTALL_DIRS)
 
-all-local: $(TMPINSTALL_FILES)
-
-TMPINSTALL_FILES =
-CLEANFILES = $(TMPINSTALL_FILES)
-
 all-am: $(PREINSTALL_FILES)
 
 PREINSTALL_FILES =
-CLEANFILES += $(PREINSTALL_FILES)
+CLEANFILES = $(PREINSTALL_FILES)
+
+all-local: $(TMPINSTALL_FILES)
+
+TMPINSTALL_FILES =
+CLEANFILES += $(TMPINSTALL_FILES)
 
 $(PROJECT_LIB)/$(dirstamp):
 	@$(MKDIR_P) $(PROJECT_LIB)
@@ -82,10 +82,6 @@ $(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h
 
-$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
-
 $(PROJECT_INCLUDE)/bsp/arm-a8core-start.h: ../shared/include/arm-a8core-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a8core-start.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a8core-start.h
@@ -118,6 +114,18 @@ $(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp1
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
 
+$(PROJECT_INCLUDE)/libcpu/omap3.h: ../../../libcpu/arm/shared/include/omap3.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/omap3.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/omap3.h
+
+$(PROJECT_INCLUDE)/libcpu/am335x.h: ../../../libcpu/arm/shared/include/am335x.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/am335x.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/am335x.h
+
+$(PROJECT_INCLUDE)/libcpu/omap_timer.h: ../../../libcpu/arm/shared/include/omap_timer.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/omap_timer.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/omap_timer.h
+
 $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
 TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
diff --git a/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh b/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
index 58ac911..becd2c7 100644
--- a/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
+++ b/c/src/lib/libbsp/arm/beagle/simscripts/sdcard.sh
@@ -2,10 +2,9 @@
 TMPDIR=tmp_sdcard_dir.$$
 
 FATIMG=$TMPDIR/bbxm_boot_fat.img
+SIZE=65536
 OFFSET=2048
-FATSIZE_KB=2880
-FATSIZE=`expr $FATSIZE_KB \* 2`
-SIZE=`expr $FATSIZE + $OFFSET`
+FATSIZE=`expr $SIZE - $OFFSET`
 UENV=uEnv.txt
 
 rm -rf $TMPDIR
@@ -52,15 +51,11 @@ set -e
 IMG=${imgtype}_`basename $2`-sdcard.img
 
 # Make an empty image
-dd if=/dev/zero of=$IMG bs=512 seek=$SIZE count=1
-# Make an ms-dos FS image
-rm -f $FATIMG
-export MTOOLSRC=$TMPDIR/mtools-conf
-echo "drive a:
-       file=\"$FATIMG\"
-       fat_bits=16
-" >$MTOOLSRC
-$PREFIX/bin/mformat -C -f $FATSIZE_KB a:
+dd if=/dev/zero of=$IMG bs=512 seek=`expr $SIZE - 1` count=1
+dd if=/dev/zero of=$FATIMG bs=512 seek=`expr $FATSIZE - 1` count=1
+
+# Make an ms-dos FS on it
+$PREFIX/bin/newfs_msdos -r 1 -m 0xf8 -c 4 -F16  -h 64 -u 32 -S 512 -s $FATSIZE -o 0 ./$FATIMG
 
 # Prepare the executable.
 base=`basename $executable`
@@ -78,7 +73,7 @@ $PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$app ::$app
 $PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$UENV ::$UENV
 
 # Just a single FAT partition (type C) that uses all of the image
-$PREFIX/bin/partition $IMG $OFFSET 'c:0*+'
+$PREFIX/bin/partition -m $IMG $OFFSET c:${FATSIZE}\*
 
 # Put the FAT image into the SD image
 dd if=$FATIMG of=$IMG seek=$OFFSET
diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h
new file mode 100644
index 0000000..4b5ea73
--- /dev/null
+++ b/c/src/lib/libcpu/arm/shared/include/am335x.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng at shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+/* Interrupt controller memory map */
+#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller memory map */
+#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+#define AM335X_INT_EMUINT             0
+    /* Emulation interrupt (EMUICINTR) */
+#define AM335X_INT_COMMTX             1
+    /* CortexA8 COMMTX */
+#define AM335X_INT_COMMRX             2
+    /* CortexA8 COMMRX */
+#define AM335X_INT_BENCH              3
+    /* CortexA8 NPMUIRQ */
+#define AM335X_INT_ELM_IRQ            4
+    /* Sinterrupt (Error location process completion) */
+#define AM335X_INT_NMI                7
+    /* nmi_int */
+#define AM335X_INT_L3DEBUG            9
+    /* l3_FlagMux_top_FlagOut1 */
+#define AM335X_INT_L3APPINT           10
+    /* l3_FlagMux_top_FlagOut0  */
+#define AM335X_INT_PRCMINT            11
+    /* irq_mpu */
+#define AM335X_INT_EDMACOMPINT        12
+    /* tpcc_int_pend_po0 */
+#define AM335X_INT_EDMAMPERR          13
+    /* tpcc_mpint_pend_po */
+#define AM335X_INT_EDMAERRINT         14
+    /* tpcc_errint_pend_po */
+#define AM335X_INT_ADC_TSC_GENINT     16
+    /* gen_intr_pend */
+#define AM335X_INT_USBSSINT           17
+    /* usbss_intr_pend */
+#define AM335X_INT_USB0               18
+    /* usb0_intr_pend */
+#define AM335X_INT_USB1               19
+    /* usb1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT0     20
+    /* pr1_host_intr0_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT1     21
+    /* pr1_host_intr1_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT2     22
+    /* pr1_host_intr2_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT3     23
+    /* pr1_host_intr3_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT4     24
+    /* pr1_host_intr4_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT5     25
+    /* pr1_host_intr5_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT6     26
+    /* pr1_host_intr6_intr_pend */
+#define AM335X_INT_PRUSS1_EVTOUT7     27
+    /* pr1_host_intr7_intr_pend */
+#define AM335X_INT_MMCSD1INT          28
+    /* MMCSD1  SINTERRUPTN */
+#define AM335X_INT_MMCSD2INT          29
+    /* MMCSD2  SINTERRUPT */
+#define AM335X_INT_I2C2INT            30
+    /* I2C2  POINTRPEND */
+#define AM335X_INT_eCAP0INT           31
+    /* ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT2A          32
+    /* GPIO 2  POINTRPEND1 */
+#define AM335X_INT_GPIOINT2B          33
+    /* GPIO 2  POINTRPEND2 */
+#define AM335X_INT_USBWAKEUP          34
+    /* USBSS  slv0p_Swakeup */
+#define AM335X_INT_LCDCINT            36
+    /* LCDC  lcd_irq */
+#define AM335X_INT_GFXINT             37
+    /* SGX530  THALIAIRQ */
+#define AM335X_INT_ePWM2INT           39
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_3PGSWRXTHR0        40
+    /* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
+#define AM335X_INT_3PGSWRXINT0        41
+    /* CPSW (Ethernet)  c0_rx_pend */
+#define AM335X_INT_3PGSWTXINT0        42
+    /* CPSW (Ethernet)  c0_tx_pend */
+#define AM335X_INT_3PGSWMISC0         43
+    /* CPSW (Ethernet)  c0_misc_pend */
+#define AM335X_INT_UART3INT           44
+    /* UART3  niq */
+#define AM335X_INT_UART4INT           45
+    /* UART4  niq */
+#define AM335X_INT_UART5INT           46
+    /* UART5  niq */
+#define AM335X_INT_eCAP1INT           47
+    /* (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_DCAN0_INT0         52
+    /* DCAN0  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN0_INT1         53
+    /* DCAN0  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN0_PARITY       54
+    /* DCAN0  dcan_uerr_intr_pend */
+#define AM335X_INT_DCAN1_INT0         55
+    /* DCAN1  dcan_intr0_intr_pend */
+#define AM335X_INT_DCAN1_INT1         56
+    /* DCAN1  dcan_intr1_intr_pend */
+#define AM335X_INT_DCAN1_PARITY       57
+    /* DCAN1  dcan_uerr_intr_pend */
+#define AM335X_INT_ePWM0_TZINT        58
+    /* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM1_TZINT        59
+    /* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_ePWM2_TZINT        60
+    /* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
+#define AM335X_INT_eCAP2INT           61
+    /* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
+#define AM335X_INT_GPIOINT3A          62
+    /* GPIO 3  POINTRPEND1 */
+#define AM335X_INT_GPIOINT3B          63
+    /* GPIO 3  POINTRPEND2 */
+#define AM335X_INT_MMCSD0INT          64
+    /* MMCSD0  SINTERRUPTN */
+#define AM335X_INT_SPI0INT            65
+    /* McSPI0  SINTERRUPTN */
+#define AM335X_INT_TINT0              66
+    /* Timer0  POINTR_PEND */
+#define AM335X_INT_TINT1_1MS          67
+    /* DMTIMER_1ms  POINTR_PEND */
+#define AM335X_INT_TINT2              68
+    /* DMTIMER2  POINTR_PEND */
+#define AM335X_INT_TINT3              69
+    /* DMTIMER3  POINTR_PEND */
+#define AM335X_INT_I2C0INT            70
+    /* I2C0  POINTRPEND */
+#define AM335X_INT_I2C1INT            71
+    /* I2C1  POINTRPEND */
+#define AM335X_INT_UART0INT           72
+    /* UART0  niq */
+#define AM335X_INT_UART1INT           73
+    /* UART1  niq */
+#define AM335X_INT_UART2INT           74
+    /* UART2  niq */
+#define AM335X_INT_RTCINT             75
+    /* RTC  timer_intr_pend */
+#define AM335X_INT_RTCALARMINT        76
+    /* RTC  alarm_intr_pend */
+#define AM335X_INT_MBINT0             77
+    /* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
+#define AM335X_INT_M3_TXEV            78
+    /* Wake M3 Subsystem  TXEV */
+#define AM335X_INT_eQEP0INT           79
+    /* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_MCATXINT0          80
+    /* McASP0  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT0          81
+    /* McASP0  mcasp_r_intr_pend */
+#define AM335X_INT_MCATXINT1          82
+    /* McASP1  mcasp_x_intr_pend */
+#define AM335X_INT_MCARXINT1          83
+    /* McASP1  mcasp_r_intr_pend */
+#define AM335X_INT_ePWM0INT           86
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_ePWM1INT           87
+    /* (PWM Subsystem)  epwm_intr_intr_pend */
+#define AM335X_INT_eQEP1INT           88
+    /* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_eQEP2INT           89
+    /* (PWM Subsystem)  eqep_intr_intr_pend */
+#define AM335X_INT_DMA_INTR_PIN2      90
+    /* External DMA/Interrupt Pin2  */
+#define AM335X_INT_WDT1INT            91
+    /* (Public Watchdog) WDTIMER1 PO_INT_PEND */
+#define AM335X_INT_TINT4              92
+    /* DMTIMER4  POINTR_PEN */
+#define AM335X_INT_TINT5              93
+    /* DMTIMER5  POINTR_PEN */
+#define AM335X_INT_TINT6              94
+    /* DMTIMER6  POINTR_PEND */
+#define AM335X_INT_TINT7              95
+    /* DMTIMER7  POINTR_PEND */
+#define AM335X_INT_GPIOINT0A          96
+    /* GPIO 0  POINTRPEND1 */
+#define AM335X_INT_GPIOINT0B          97
+    /* GPIO 0  POINTRPEND2 */
+#define AM335X_INT_GPIOINT1A          98
+    /* GPIO 1  POINTRPEND1 */
+#define AM335X_INT_GPIOINT1B          99
+    /* GPIO 1  POINTRPEND2 */
+#define AM335X_INT_GPMCINT            100
+    /* GPMC  gpmc_sinterrupt */
+#define AM335X_INT_DDRERR0            101
+    /* EMIF  sys_err_intr_pend */
+#define AM335X_INT_TCERRINT0          112
+    /* TPTC0  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT1          113
+    /* TPTC1  tptc_erint_pend_po */
+#define AM335X_INT_TCERRINT2          114
+    /* TPTC2  tptc_erint_pend_po */
+#define AM335X_INT_ADC_TSC_PENINT     115
+    /* ADC_TSC  pen_intr_pend */
+#define AM335X_INT_SMRFLX_Sabertooth  120
+    /* Smart Reflex 0  intrpen */
+#define AM335X_INT_SMRFLX_Core        121
+    /* Smart Reflex 1  intrpend */
+#define AM335X_INT_DMA_INTR_PIN0      123
+    /* pi_x_dma_event_intr0 (xdma_event_intr0) */
+#define AM335X_INT_DMA_INTR_PIN1      124
+    /* pi_x_dma_event_intr1 (xdma_event_intr1) */
+#define AM335X_INT_SPI1INT            125
+    /* McSPI1  SINTERRUPTN */
+
+#define OMAP3_AM335X_NR_IRQ_VECTORS    125
+
+#define AM335X_DMTIMER0_BASE      0x44E05000
+    /* DMTimer0 Registers */
+#define AM335X_DMTIMER1_1MS_BASE  0x44E31000
+    /* DMTimer1 1ms Registers (Accurate 1ms timer) */
+#define AM335X_DMTIMER2_BASE      0x48040000
+    /*  DMTimer2 Registers */
+#define AM335X_DMTIMER3_BASE      0x48042000
+    /*  DMTimer3 Registers */
+#define AM335X_DMTIMER4_BASE      0x48044000
+    /* DMTimer4 Registers  */
+#define AM335X_DMTIMER5_BASE      0x48046000
+    /* DMTimer5 Registers  */
+#define AM335X_DMTIMER6_BASE      0x48048000
+    /*  DMTimer6 Registers */
+#define AM335X_DMTIMER7_BASE      0x4804A000
+    /*  DMTimer7 Registers */
+
+/* General-purpose timer registers
+   AM335x non 1MS timers have different offsets */
+#define AM335X_TIMER_TIDR             0x000
+    /* IP revision code */
+#define AM335X_TIMER_TIOCP_CFG        0x010
+    /* Controls params for GP timer L4 interface */
+#define AM335X_TIMER_IRQSTATUS_RAW    0x024
+    /* Timer IRQSTATUS Raw Register */
+#define AM335X_TIMER_IRQSTATUS        0x028
+    /* Timer IRQSTATUS Register */
+#define AM335X_TIMER_IRQENABLE_SET    0x02C
+    /* Timer IRQENABLE Set Register */
+#define AM335X_TIMER_IRQENABLE_CLR    0x030
+    /* Timer IRQENABLE Clear Register */
+#define AM335X_TIMER_IRQWAKEEN        0x034
+    /* Timer IRQ Wakeup Enable Register */
+#define AM335X_TIMER_TCLR             0x038
+    /* Controls optional features */
+#define AM335X_TIMER_TCRR             0x03C
+    /* Internal counter value */
+#define AM335X_TIMER_TLDR             0x040
+    /* Timer load value */
+#define AM335X_TIMER_TTGR             0x044
+    /* Triggers counter reload */
+#define AM335X_TIMER_TWPS             0x048
+    /* Indicates if Write-Posted pending */
+#define AM335X_TIMER_TMAR             0x04C
+    /* Value to be compared with counter */
+#define AM335X_TIMER_TCAR1            0x050
+    /* First captured value of counter register */
+#define AM335X_TIMER_TSICR            0x054
+    /* Control posted mode and functional SW reset */
+#define AM335X_TIMER_TCAR2            0x058
+    /* Second captured value of counter register */
diff --git a/c/src/lib/libcpu/arm/shared/include/omap3.h b/c/src/lib/libcpu/arm/shared/include/omap3.h
new file mode 100644
index 0000000..2c044a1
--- /dev/null
+++ b/c/src/lib/libcpu/arm/shared/include/omap3.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ *  Claas Ziemke
+ *  Kernerstrasse 11
+ *  70182 Stuttgart
+ *  Germany
+ *  <claas.ziemke at gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * Modified by Ben Gras <beng at shrike-systems.com> to add lots
+ * of beagleboard/beaglebone definitions, delete lpc32xx specific
+ * ones, and merge with some other header files.
+ */
+
+/* Interrupt controller memory map */
+#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller memory map */
+#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
+
+/* Interrupt controller registers */
+#define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
+#define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
+#define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
+#define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
+#define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
+#define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
+#define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
+#define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
+#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
+#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
+#define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
+#define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
+#define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
+#define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
+#define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
+#define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
+#define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
+#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
+#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
+#define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
+
+/* SYSCONFIG */
+#define OMAP3_SYSCONFIG_AUTOIDLE	0x01	/* SYSCONFIG.AUTOIDLE bit */
+
+#define OMAP3_INTR_ITR(base,n) \
+    (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR(base,n) \
+    (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_CLEAR(base,n)	\
+    (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_MIR_SET(base,n) \
+    (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_SET(base,n) \
+    (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
+#define OMAP3_INTR_ISR_CLEAR(base,n) \
+    (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_IRQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
+#define OMAP3_INTR_PENDING_FIQ(base,n) \
+    (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
+#define OMAP3_INTR_ILR(base,m) \
+    (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
+
+#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7f /* Active IRQ mask for SIR_IRQ */
+#define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
+
+#define OMAP3_DM337X_NR_IRQ_VECTORS    96
+
+/* Interrupt mappings */
+#define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
+#define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
+#define OMAP3_SYS_NIRQ       7  /* External source (active low) */
+#define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
+#define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
+#define OMAP3_PRCM_IRQ      11  /* PRCM module */
+#define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
+#define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
+#define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
+#define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
+#define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
+#define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
+#define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
+#define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
+#define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
+#define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
+#define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
+#define OMAP3_DSS_IRQ       25  /* Display subsystem module */
+#define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
+#define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
+#define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
+#define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
+#define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
+#define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
+#define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
+#define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
+#define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
+#define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
+#define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
+#define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
+#define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
+#define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
+#define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
+#define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
+#define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
+#define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
+#define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
+#define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
+#define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
+#define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
+#define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
+#define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
+#define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
+#define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
+#define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
+#define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
+#define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
+#define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
+#define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
+#define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
+#define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
+#define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
+#define OMAP3_UART1_IRQ     72  /* UART module 1 */
+#define OMAP3_UART2_IRQ     73  /* UART module 2 */
+#define OMAP3_UART3_IRQ     74  /* UART module 3 */
+#define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
+#define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
+#define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
+#define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
+#define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
+#define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
+#define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
+#define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
+#define OMAP3_ICR_IRQ       87  /* MPU ICR */
+#define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
+#define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
+#define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
+#define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
+#define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
+#define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
+#define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
+
+/* General-purpose timer register map */
+#define OMAP3_GPTIMER1_BASE  0x48318000
+    /* GPTIMER1 physical address */
+#define OMAP3_GPTIMER2_BASE  0x49032000
+    /* GPTIMER2 physical address */
+#define OMAP3_GPTIMER3_BASE  0x49034000
+    /* GPTIMER3 physical address */
+#define OMAP3_GPTIMER4_BASE  0x49036000
+    /* GPTIMER4 physical address */
+#define OMAP3_GPTIMER5_BASE  0x49038000
+    /* GPTIMER5 physical address */
+#define OMAP3_GPTIMER6_BASE  0x4903A000
+    /* GPTIMER6 physical address */
+#define OMAP3_GPTIMER7_BASE  0x4903C000
+    /* GPTIMER7 physical address */
+#define OMAP3_GPTIMER8_BASE  0x4903E000
+    /* GPTIMER8 physical address */
+#define OMAP3_GPTIMER9_BASE  0x49040000
+    /* GPTIMER9 physical address */
+#define OMAP3_GPTIMER10_BASE 0x48086000
+    /* GPTIMER10 physical address */
+#define OMAP3_GPTIMER11_BASE 0x48088000
+    /* GPTIMER11 physical address */
+
+
+/* General-purpose timer registers */
+#define OMAP3_TIMER_TIDR      0x000
+    /* IP revision code */
+#define OMAP3_TIMER_TIOCP_CFG 0x010
+    /* Controls params for GP timer L4 iface */
+#define OMAP3_TIMER_TISTAT    0x014
+    /* Status (excl. interrupt status) */
+#define OMAP3_TIMER_TISR      0x018
+    /* Pending interrupt status */
+#define OMAP3_TIMER_TIER      0x01C
+    /* Interrupt enable */
+#define OMAP3_TIMER_TWER      0x020
+    /* Wakeup enable */
+#define OMAP3_TIMER_TCLR      0x024
+    /* Controls optional features */
+#define OMAP3_TIMER_TCRR      0x028
+    /* Internal counter value */
+#define OMAP3_TIMER_TLDR      0x02C
+    /* Timer load value */
+#define OMAP3_TIMER_TTGR      0x030
+    /* Triggers counter reload */
+#define OMAP3_TIMER_TWPS      0x034
+    /* Indicates if Write-Posted pending */
+#define OMAP3_TIMER_TMAR      0x038
+    /* Value to be compared with counter */
+#define OMAP3_TIMER_TCAR1     0x03C
+    /* First captured value of counter reg */
+#define OMAP3_TIMER_TSICR     0x040
+    /* Control posted mode and functional SW rst */
+#define OMAP3_TIMER_TCAR2     0x044
+    /* Second captured value of counter register */
+#define OMAP3_TIMER_TPIR      0x048
+    /* Positive increment (1 ms tick) */
+#define OMAP3_TIMER_TNIR      0x04C
+    /* Negative increment (1 ms tick) */
+#define OMAP3_TIMER_TCVR      0x050
+    /* Defines TCRR is sub/over-period (1 ms tick) */
+#define OMAP3_TIMER_TOCR      0x054
+    /* Masks tick interrupt */
+#define OMAP3_TIMER_TOWR      0x058
+    /* Number of masked overflow interrupts */
+
+/* Interrupt status register fields */
+#define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
+#define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
+#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
+
+/* Interrupt enable register fields */
+#define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
+#define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
+#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
+
+/* Timer control fields */
+#define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
+#define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
+#define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
+#define OMAP3_TCLR_PTV      (1 << 1)  /* looks like "bleed" from Minix */
+#define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
+
+
+#define OMAP3_CM_CLKSEL_GFX		0x48004b40
+#define OMAP3_CM_CLKEN_PLL		0x48004d00
+#define OMAP3_CM_FCLKEN1_CORE	0x48004A00
+#define OMAP3_CM_CLKSEL_CORE	0x48004A40 /* GPT10 src clock sel. */
+#define OMAP3_CM_FCLKEN_PER		0x48005000
+#define OMAP3_CM_CLKSEL_PER		0x48005040
+#define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
+
+
+#define CM_MODULEMODE_MASK        (0x3 << 0)
+#define CM_MODULEMODE_ENABLE      (0x2 << 0)
+#define CM_MODULEMODE_DISABLED    (0x0 << 0)
+
+#define CM_CLKCTRL_IDLEST         (0x3 << 16)
+#define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
+#define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
+#define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
+#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
+
+#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
+
+#define CM_WKUP_TIMER1_CLKCTRL	(CM_WKUP_BASE + 0xC4)
+    /* This register manages the TIMER1 clocks. [Memory Mapped] */
+
+#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
+#define CM_PER_TIMER7_CLKCTRL	(CM_PER_BASE + 0x7C)
+    /* This register manages the TIMER7 clocks. [Memory Mapped] */
+
+/* CM_DPLL registers */
+
+#define CM_DPLL_BASE 	0x44E00500 /* Clock Module PLL Registers */
+
+#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
+
+#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
+    /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
+    /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
+    /* Select TCLKIN clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
+    /* Select CLK_RC32K clock */
+#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
+    /* Selects the CLK_32768 from 32KHz Crystal Osc */
+
+#define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
+#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
+#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
+#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
+
+#define OMAP3_CLKSEL_GPT1    (1 << 0)
+#define OMAP3_CLKSEL_GPT10   (1 << 6)
+#define OMAP3_CLKSEL_GPT11   (1 << 7)
+
+#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
+
+#define ARM_TTBR_ADDR_MASK (0xffffc000)
+#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
+#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
+#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
+#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
+#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
+
+/* cpu control flags */
+/* CPU control register (CP15 register 1) */
+#define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
+#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
+#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
+#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
+#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
+#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
+#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
+#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
+#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
+#define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
+#define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
+#define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
+#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
+#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
+#define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
+#define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
+#define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
+#define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
+#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
+#define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
+#define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
+#define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
+#define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
+#define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
+#define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
+#define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
+
+#define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
+
+/* VM bits */
+
+/* Big page (1MB section) specific flags. */
+#define ARM_VM_SECTION                  (1 << 1)
+    /* 1MB section */
+#define ARM_VM_SECTION_PRESENT          (1 << 1)
+    /* Section is present */
+#define ARM_VM_SECTION_B                (1 << 2)
+    /* B Bit */
+#define ARM_VM_SECTION_C                (1 << 3)
+    /* C Bit */
+#define ARM_VM_SECTION_DOMAIN           (0xF << 5)
+    /* Domain Number */
+#define ARM_VM_SECTION_SUPER            (0x1 << 10)
+    /* Super access only AP[1:0] */
+#define ARM_VM_SECTION_USER             (0x3 << 10)
+    /* Super/User access AP[1:0] */
+#define ARM_VM_SECTION_TEX0             (1 << 12)
+    /* TEX[0] */
+#define ARM_VM_SECTION_TEX1             (1 << 13)
+    /* TEX[1] */
+#define ARM_VM_SECTION_TEX2             (1 << 14)
+    /* TEX[2] */
+#define ARM_VM_SECTION_RO               (1 << 15)
+    /* Read only access AP[2] */
+#define ARM_VM_SECTION_SHAREABLE        (1 << 16)
+    /* Shareable */
+#define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)
+    /* Not Global */
+
+#define ARM_VM_SECTION_WB \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
+/* inner and outer write-back, write-allocate */
+#define ARM_VM_SECTION_WT \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
+/* inner and outer write-through, no write-allocate */
+#define ARM_VM_SECTION_WTWB \
+    (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
+/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
+
+/* shareable device */
+#define ARM_VM_SECTION_CACHED   ARM_VM_SECTION_WTWB
+#define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)
diff --git a/c/src/lib/libcpu/arm/shared/include/omap_timer.h b/c/src/lib/libcpu/arm/shared/include/omap_timer.h
new file mode 100644
index 0000000..47310b1
--- /dev/null
+++ b/c/src/lib/libcpu/arm/shared/include/omap_timer.h
@@ -0,0 +1,40 @@
+/**
+ * @file
+ *
+ * @brief Clock driver configuration.
+ */
+
+#include <stdint.h>
+
+typedef struct omap_timer_registers
+{
+  uint32_t TIDR;
+  uint32_t TIOCP_CFG;
+  uint32_t TISTAT;
+  uint32_t TISR;
+  uint32_t TIER;
+  uint32_t TWER;
+  uint32_t TCLR;
+  uint32_t TCRR;
+  uint32_t TLDR;
+  uint32_t TTGR;
+  uint32_t TWPS;
+  uint32_t TMAR;
+  uint32_t TCAR1;
+  uint32_t TSICR;
+  uint32_t TCAR2;
+  uint32_t TPIR;
+  uint32_t TNIR;
+  uint32_t TCVR;
+  uint32_t TOCR;
+  uint32_t TOWR;
+
+} omap_timer_registers_t;
+
+typedef struct omap_timer
+{
+  uint32_t base;
+  int irq_nr;
+  struct omap_timer_registers *regs;
+} omap_timer_t;
+
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